1/*
2 Copyright (C) Intel Corp.  2006.  All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26**********************************************************************/
27
28/*
29 * Authors:
30 *   Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#include "main/glheader.h"
34#include "main/mtypes.h"
35#include "main/imports.h"
36#include "main/macros.h"
37#include "main/colormac.h"
38#include "main/renderbuffer.h"
39#include "main/framebuffer.h"
40
41#include "intel_batchbuffer.h"
42#include "intel_regions.h"
43#include "intel_fbo.h"
44
45#include "brw_context.h"
46#include "brw_defines.h"
47#include "brw_state.h"
48#include "brw_draw.h"
49#include "brw_vs.h"
50#include "brw_wm.h"
51
52#include "gen6_blorp.h"
53#include "gen7_blorp.h"
54
55#include "glsl/ralloc.h"
56
57static void
58dri_bo_release(drm_intel_bo **bo)
59{
60   drm_intel_bo_unreference(*bo);
61   *bo = NULL;
62}
63
64
65/**
66 * called from intelDestroyContext()
67 */
68static void brw_destroy_context( struct intel_context *intel )
69{
70   struct brw_context *brw = brw_context(&intel->ctx);
71
72   brw_destroy_state(brw);
73   brw_draw_destroy( brw );
74
75   ralloc_free(brw->wm.compile_data);
76
77   dri_bo_release(&brw->curbe.curbe_bo);
78   dri_bo_release(&brw->vs.const_bo);
79   dri_bo_release(&brw->wm.const_bo);
80
81   free(brw->curbe.last_buf);
82   free(brw->curbe.next_buf);
83
84   drm_intel_gem_context_destroy(intel->hw_ctx);
85}
86
87/**
88 * Update the hardware state for drawing into a window or framebuffer object.
89 *
90 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other
91 * places within the driver.
92 *
93 * Basically, this needs to be called any time the current framebuffer
94 * changes, the renderbuffers change, or we need to draw into different
95 * color buffers.
96 */
97static void
98brw_update_draw_buffer(struct intel_context *intel)
99{
100   struct gl_context *ctx = &intel->ctx;
101   struct gl_framebuffer *fb = ctx->DrawBuffer;
102
103   if (!fb) {
104      /* this can happen during the initial context initialization */
105      return;
106   }
107
108   /* Do this here, not core Mesa, since this function is called from
109    * many places within the driver.
110    */
111   if (ctx->NewState & _NEW_BUFFERS) {
112      /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */
113      _mesa_update_framebuffer(ctx);
114      /* this updates the DrawBuffer's Width/Height if it's a FBO */
115      _mesa_update_draw_buffer_bounds(ctx);
116   }
117
118   if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
119      /* this may occur when we're called by glBindFrameBuffer() during
120       * the process of someone setting up renderbuffers, etc.
121       */
122      /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/
123      return;
124   }
125
126   /* Mesa's Stencil._Enabled field is updated when
127    * _NEW_BUFFERS | _NEW_STENCIL, but i965 code assumes that the value
128    * only changes with _NEW_STENCIL (which seems sensible).  So flag it
129    * here since this is the _NEW_BUFFERS path.
130    */
131   intel->NewGLState |= (_NEW_DEPTH | _NEW_STENCIL);
132
133   /* The driver uses this in places that need to look up
134    * renderbuffers' buffer objects.
135    */
136   intel->NewGLState |= _NEW_BUFFERS;
137
138   /* update viewport/scissor since it depends on window size */
139   intel->NewGLState |= _NEW_VIEWPORT | _NEW_SCISSOR;
140
141   /* Update culling direction which changes depending on the
142    * orientation of the buffer:
143    */
144   intel->NewGLState |= _NEW_POLYGON;
145}
146
147/**
148 * called from intel_batchbuffer_flush and children before sending a
149 * batchbuffer off.
150 *
151 * Note that ALL state emitted here must fit in the reserved space
152 * at the end of a batchbuffer.  If you add more GPU state, increase
153 * the BATCH_RESERVED macro.
154 */
155static void brw_finish_batch(struct intel_context *intel)
156{
157   struct brw_context *brw = brw_context(&intel->ctx);
158   brw_emit_query_end(brw);
159
160   if (brw->curbe.curbe_bo) {
161      drm_intel_gem_bo_unmap_gtt(brw->curbe.curbe_bo);
162      drm_intel_bo_unreference(brw->curbe.curbe_bo);
163      brw->curbe.curbe_bo = NULL;
164   }
165}
166
167
168/**
169 * called from intelFlushBatchLocked
170 */
171static void brw_new_batch( struct intel_context *intel )
172{
173   struct brw_context *brw = brw_context(&intel->ctx);
174
175   /* If the kernel supports hardware contexts, then most hardware state is
176    * preserved between batches; we only need to re-emit state that is required
177    * to be in every batch.  Otherwise we need to re-emit all the state that
178    * would otherwise be stored in the context (which for all intents and
179    * purposes means everything).
180    */
181   if (intel->hw_ctx == NULL)
182      brw->state.dirty.brw |= BRW_NEW_CONTEXT;
183
184   brw->state.dirty.brw |= BRW_NEW_BATCH;
185
186   /* Assume that the last command before the start of our batch was a
187    * primitive, for safety.
188    */
189   intel->batch.need_workaround_flush = true;
190
191   brw->state_batch_count = 0;
192
193   /* Gen7 needs to track what the real transform feedback vertex count was at
194    * the start of the batch, since the kernel will be resetting the offset to
195    * 0.
196    */
197   brw->sol.offset_0_batch_start = brw->sol.svbi_0_starting_index;
198
199   brw->vb.nr_current_buffers = 0;
200   brw->ib.type = -1;
201
202   /* Mark that the current program cache BO has been used by the GPU.
203    * It will be reallocated if we need to put new programs in for the
204    * next batch.
205    */
206   brw->cache.bo_used_by_gpu = true;
207}
208
209static void brw_invalidate_state( struct intel_context *intel, GLuint new_state )
210{
211   /* nothing */
212}
213
214/**
215 * \see intel_context.vtbl.is_hiz_depth_format
216 */
217static bool brw_is_hiz_depth_format(struct intel_context *intel,
218                                    gl_format format)
219{
220   if (!intel->has_hiz)
221      return false;
222
223   switch (format) {
224   case MESA_FORMAT_Z32_FLOAT:
225   case MESA_FORMAT_Z32_FLOAT_X24S8:
226   case MESA_FORMAT_X8_Z24:
227   case MESA_FORMAT_S8_Z24:
228      return true;
229   default:
230      return false;
231   }
232}
233
234void brwInitVtbl( struct brw_context *brw )
235{
236   brw->intel.vtbl.check_vertex_size = 0;
237   brw->intel.vtbl.emit_state = 0;
238   brw->intel.vtbl.reduced_primitive_state = 0;
239   brw->intel.vtbl.render_start = 0;
240   brw->intel.vtbl.update_texture_state = 0;
241
242   brw->intel.vtbl.invalidate_state = brw_invalidate_state;
243   brw->intel.vtbl.new_batch = brw_new_batch;
244   brw->intel.vtbl.finish_batch = brw_finish_batch;
245   brw->intel.vtbl.destroy = brw_destroy_context;
246   brw->intel.vtbl.update_draw_buffer = brw_update_draw_buffer;
247   brw->intel.vtbl.debug_batch = brw_debug_batch;
248   brw->intel.vtbl.annotate_aub = brw_annotate_aub;
249   brw->intel.vtbl.render_target_supported = brw_render_target_supported;
250   brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format;
251
252   assert(brw->intel.gen >= 4);
253   if (brw->intel.gen >= 7) {
254      gen7_init_vtable_surface_functions(brw);
255   } else if (brw->intel.gen >= 4) {
256      gen4_init_vtable_surface_functions(brw);
257   }
258}
259