1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#ifndef COMMON_CONTEXT_H 3f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define COMMON_CONTEXT_H 4f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 5f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/mm.h" 6f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "math/m_vector.h" 7f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "tnl/t_context.h" 8f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/colormac.h" 9f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 10f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_debug.h" 11f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_screen.h" 12f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_drm.h" 13f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "dri_util.h" 14f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "tnl/t_vertex.h" 15f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "swrast/s_context.h" 16f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 17f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_context; 18f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 19f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_bo_gem.h" 20f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_cs_gem.h" 21f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 22f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* This union is used to avoid warnings/miscompilation 23f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org with float to uint32_t casts due to strict-aliasing */ 24f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef union { GLfloat f; uint32_t ui32; } float_ui32_type; 25f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 26f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_context; 27f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef struct radeon_context radeonContextRec; 28f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef struct radeon_context *radeonContextPtr; 29f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 30f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 31f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TEX_0 0x1 32f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TEX_1 0x2 33f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TEX_2 0x4 34f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TEX_3 0x8 35f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TEX_4 0x10 36f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TEX_5 0x20 37f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 38f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Rasterizing fallbacks */ 39f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* See correponding strings in r200_swtcl.c */ 40f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_TEXTURE 0x0001 41f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 42f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_STENCIL 0x0004 43f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_RENDER_MODE 0x0008 44f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_BLEND_EQ 0x0010 45f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_BLEND_FUNC 0x0020 46f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_DISABLE 0x0040 47f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_BORDER_MODE 0x0080 48f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_DEPTH_BUFFER 0x0100 49f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FALLBACK_STENCIL_BUFFER 0x0200 50f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 51f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_FALLBACK_TEXTURE 0x01 52f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_FALLBACK_DRAW_BUFFER 0x02 53f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_FALLBACK_STENCIL 0x04 54f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_FALLBACK_RENDER_MODE 0x08 55f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_FALLBACK_DISABLE 0x10 56f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_FALLBACK_BORDER_MODE 0x20 57f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 58f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ 59f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ 60f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ 61f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ 62f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ 63f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ 64f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ 65f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ 66f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ 67f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 68f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* The blit width for texture uploads 69f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 70f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define BLIT_WIDTH_BYTES 1024 71f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 72f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Use the templated vertex format: 73f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 74f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define COLOR_IS_RGBA 75f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define TAG(x) radeon##x 76f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "tnl_dd/t_dd_vertex.h" 77f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#undef TAG 78f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 79f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB_CLASS 0xdeadbeef 80f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 81f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_renderbuffer 82f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 83f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct swrast_renderbuffer base; 84f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 85f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 86f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned int cpp; 87f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* unsigned int offset; */ 88f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned int pitch; 89f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 90f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *map_bo; 91f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLbitfield map_mode; 92f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int map_x, map_y, map_w, map_h; 93f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int map_pitch; 94f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void *map_buffer; 95f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 96f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org uint32_t draw_offset; /* FBO */ 97f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* boo Xorg 6.8.2 compat */ 98f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int has_surface; 99f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 100f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pf_pending; /**< sequence number of pending flip */ 101f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __DRIdrawable *dPriv; 102f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 103f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 104f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_framebuffer 105f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 106f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct gl_framebuffer base; 107f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 108f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_renderbuffer *color_rb[2]; 109f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 110f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 111f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 112f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_colorbuffer_state { 113f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int roundEnable; 114f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct gl_renderbuffer *rb; 115f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org uint32_t draw_offset; /* offset into color renderbuffer - FBOs */ 116f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 117f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 118f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_depthbuffer_state { 119f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct gl_renderbuffer *rb; 120f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 121f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 122f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_scissor_state { 123f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drm_clip_rect_t rect; 124f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean enabled; 125f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 126f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 127f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_state_atom { 128f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_state_atom *next, *prev; 129f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org const char *name; /* for debug */ 130f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int cmd_size; /* size in bytes */ 131f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint idx; 132f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint is_tcl; 133f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint *cmd; /* one or more cmd's */ 134f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint *lastcmd; /* one or more cmd's */ 135f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean dirty; /* dirty-mark in emit_state_list */ 136f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */ 137f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*emit) (struct gl_context *, struct radeon_state_atom *atom); 138f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 139f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 140f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_hw_state { 141f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Head of the linked list of state atoms. */ 142f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_state_atom atomlist; 143f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int max_state_size; /* Number of bytes necessary for a full state emit. */ 144f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int max_post_flush_size; /* Number of bytes necessary for post flushing emits */ 145f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean is_dirty, all_dirty; 146f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 147f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 148f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 149f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Texture related */ 150f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef struct _radeon_texture_image radeon_texture_image; 151f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 152f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 153f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/** 154f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * This is a subclass of swrast_texture_image since we use swrast 155f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * for software fallback rendering. 156f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 157f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct _radeon_texture_image { 158f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct swrast_texture_image base; 159f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 160f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /** 161f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * If mt != 0, the image is stored in hardware format in the 162f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * given mipmap tree. In this case, base.Data may point into the 163f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * mapping of the buffer object that contains the mipmap tree. 164f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 165f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * If mt == 0, the image is stored in normal memory pointed to 166f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * by base.Data. 167f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 168f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct _radeon_mipmap_tree *mt; 169f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 170f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean used_as_render_target; 171f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 172f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 173f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 174f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstatic INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image) 175f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 176f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return (radeon_texture_image*)image; 177f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 178f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 179f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 180f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 181f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 182f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TXO_MICRO_TILE (1 << 3) 183f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 184f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Texture object in locally shared texture space. 185f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 186f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_tex_obj { 187f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct gl_texture_object base; 188f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct _radeon_mipmap_tree *mt; 189f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 190f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /** 191f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * This is true if we've verified that the mipmap tree above is complete 192f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * and so on. 193f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 194f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean validated; 195f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Minimum LOD to be used during rendering */ 196f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned minLod; 197f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Miximum LOD to be used during rendering */ 198f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned maxLod; 199f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 200f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint override_offset; 201f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ 202f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint tile_bits; /* hw texture tile bits used on this texture */ 203f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 204f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 205f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_txfilter; /* hardware register values */ 206f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_txformat; 207f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_txformat_x; 208f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_txsize; /* npot only */ 209f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_txpitch; /* npot only */ 210f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_border_color; 211f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 212f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 213f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean border_fallback; 214f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 215f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 216f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstatic INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj) 217f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 218f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return (radeonTexObj*)texObj; 219f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 220f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 221f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* occlusion query */ 222f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_query_object { 223f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct gl_query_object Base; 224f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 225f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int curr_offset; 226f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean emitted_begin; 227f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 228f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Double linked list of not flushed query objects */ 229f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_query_object *prev, *next; 230f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 231f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 232f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Need refcounting on dma buffers: 233f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 234f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_dma_buffer { 235f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int refcount; /* the number of retained regions in buf */ 236f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drmBufPtr buf; 237f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 238f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 239f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_aos { 240f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; /** Buffer object where vertex data is stored */ 241f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int offset; /** Offset into buffer object, in bytes */ 242f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int components; /** Number of components per vertex */ 243f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int stride; /** Stride in dwords (may be 0 for repeating) */ 244f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int count; /** Number of vertices */ 245f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 246f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 247f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define DMA_BO_FREE_TIME 100 248f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 249f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_dma_bo { 250f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_dma_bo *next, *prev; 251f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 252f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int expire_counter; 253f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 254f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 255f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_dma { 256f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Active dma region. Allocations for vertices and retained 257f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * regions come from here. Also used for emitting random vertices, 258f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * these may be flushed by calling flush_current(); 259f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 260f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_dma_bo free; 261f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_dma_bo wait; 262f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_dma_bo reserved; 263f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org size_t current_used; /** Number of bytes allocated and forgotten about */ 264f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org size_t current_vertexptr; /** End of active vertex region */ 265f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org size_t minimum_size; 266f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 267f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /** 268f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * If current_vertexptr != current_used then flush must be non-zero. 269f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * flush must be called before non-active vertex allocations can be 270f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * performed. 271f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 272f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*flush) (struct gl_context *); 273f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 274f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 275f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* radeon_swtcl.c 276f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 277f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_swtcl_info { 278f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 279f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint RenderIndex; 280f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_size; 281f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLubyte *verts; 282f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 283f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Fallback rasterization functions 284f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 285f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint hw_primitive; 286f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLenum render_primitive; 287f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint numverts; 288f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 289f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 290f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_attr_count; 291f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 292f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint emit_prediction; 293f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 294f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 295f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 296f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MAX_AOS_ARRAYS 16 297f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_tcl_info { 298f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS]; 299f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint aos_count; 300f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ 301f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int elt_dma_offset; /** Offset into this buffer object, in bytes */ 302f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 303f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 304f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_ioctl { 305f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_offset; 306f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_max; 307f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo; 308f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_size; 309f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 310f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 311f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MAX_PRIMS 64 312f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 313f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_prim { 314f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint start; 315f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint end; 316f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint prim; 317f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 318f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 319f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstatic INLINE GLuint radeonPackColor(GLuint cpp, 320f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLubyte r, GLubyte g, 321f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLubyte b, GLubyte a) 322f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 323f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org switch (cpp) { 324f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case 2: 325f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return PACK_COLOR_565(r, g, b); 326f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org case 4: 327f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return PACK_COLOR_8888(a, r, g, b); 328f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org default: 329f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return 0; 330f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 331f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 332f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 333f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define MAX_CMD_BUF_SZ (16*1024) 334f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 335f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define MAX_DMA_BUF_SZ (64*1024) 336f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 337f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_store { 338f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint statenr; 339f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint primnr; 340f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org char cmd_buf[MAX_CMD_BUF_SZ]; 341f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int cmd_used; 342f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int elts_start; 343f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 344f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 345f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_dri_mirror { 346f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __DRIcontext *context; /* DRI context */ 347f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __DRIscreen *screen; /* DRI screen */ 348f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 349f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drm_context_t hwContext; 350f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drm_hw_lock_t *hwLock; 351f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int hwLockCount; 352f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int fd; 353f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int drmMinor; 354f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 355f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 356f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef void (*radeon_tri_func) (radeonContextPtr, 357f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonVertex *, 358f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonVertex *, radeonVertex *); 359f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 360f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef void (*radeon_line_func) (radeonContextPtr, 361f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonVertex *, radeonVertex *); 362f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 363f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgtypedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); 364f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 365f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MAX_BOS 32 366f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_state { 367f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_colorbuffer_state color; 368f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_depthbuffer_state depth; 369f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_scissor_state scissor; 370f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 371f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 372f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/** 373f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * This structure holds the command buffer while it is being constructed. 374f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 375f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * The first batch of commands in the buffer is always the state that needs 376f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * to be re-emitted when the context is lost. This batch can be skipped 377f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * otherwise. 378f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 379f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_cmdbuf { 380f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_cs_manager *csm; 381f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_cs *cs; 382f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int size; /** # of dwords total */ 383f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ 384f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 385f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 386f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstruct radeon_context { 387f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct gl_context *glCtx; 388f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonScreenPtr radeonScreen; /* Screen private DRI data */ 389f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 390f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Texture object bookkeeping 391f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 392f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int texture_depth; 393f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org float initialMaxAnisotropy; 394f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org uint32_t texture_row_align; 395f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org uint32_t texture_rect_row_align; 396f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org uint32_t texture_compressed_row_align; 397f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 398f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_dma dma; 399f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_hw_state hw; 400f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Rasterization and vertex state: 401f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 402f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint TclFallback; 403f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint Fallback; 404f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint NewGLState; 405f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLbitfield64 tnl_index_bitset; /* index of bits for last tnl_install_attrs */ 406f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 407f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Drawable information */ 408f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned int lastStamp; 409f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drm_radeon_sarea_t *sarea; /* Private SAREA data */ 410f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 411f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Mirrors of some DRI state */ 412f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_dri_mirror dri; 413f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 414f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Busy waiting */ 415f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint do_usleeps; 416f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint do_irqs; 417f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint irqsEmitted; 418f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drm_radeon_irq_wait_t iw; 419f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 420f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Derived state - for r300 only */ 421f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_state state; 422f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 423f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_swtcl_info swtcl; 424f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_tcl_info tcl; 425f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Configuration cache 426f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 427f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org driOptionCache optionCache; 428f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 429f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_cmdbuf cmdbuf; 430f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 431f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_debug debug; 432f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 433f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org drm_clip_rect_t fboRect; 434f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean front_cliprects; 435f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 436f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /** 437f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Set if rendering has occured to the drawable's front buffer. 438f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 439f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * This is used in the DRI2 case to detect that glFlush should also copy 440f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * the contents of the fake front buffer to the real front buffer. 441f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 442f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean front_buffer_dirty; 443f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 444f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /** 445f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Track whether front-buffer rendering is currently enabled 446f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 447f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * A separate flag is used to track this in order to support MRT more 448f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * easily. 449f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 450f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean is_front_buffer_rendering; 451f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 452f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /** 453f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Track whether front-buffer is the current read target. 454f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 455f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * This is closely associated with is_front_buffer_rendering, but may 456f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * be set separately. The DRI2 fake front buffer must be referenced 457f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * either way. 458f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 459f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean is_front_buffer_reading; 460f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 461f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct { 462f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_query_object *current; 463f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_state_atom queryobj; 464f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } query; 465f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 466f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct { 467f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*get_lock)(radeonContextPtr radeon); 468f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*update_viewport_offset)(struct gl_context *ctx); 469f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); 470f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset); 471f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*pre_emit_atoms)(radeonContextPtr rmesa); 472f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*pre_emit_state)(radeonContextPtr rmesa); 473f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode); 474f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*free_context)(struct gl_context *ctx); 475f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*emit_query_finish)(radeonContextPtr radeon); 476f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void (*update_scissor)(struct gl_context *ctx); 477f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned (*check_blit)(gl_format mesa_format, uint32_t dst_pitch); 478f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned (*blit)(struct gl_context *ctx, 479f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *src_bo, 480f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org intptr_t src_offset, 481f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org gl_format src_mesaformat, 482f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned src_pitch, 483f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned src_width, 484f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned src_height, 485f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned src_x_offset, 486f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned src_y_offset, 487f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *dst_bo, 488f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org intptr_t dst_offset, 489f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org gl_format dst_mesaformat, 490f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned dst_pitch, 491f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned dst_width, 492f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned dst_height, 493f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned dst_x_offset, 494f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned dst_y_offset, 495f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned reg_width, 496f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned reg_height, 497f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned flip_y); 498f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org unsigned (*is_format_renderable)(gl_format mesa_format); 499f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } vtbl; 500f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org}; 501f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 502f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) 503f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 504f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstatic inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon) 505f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 506f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return radeon->dri.context->driDrawablePriv; 507f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 508f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 509f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstatic inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon) 510f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 511f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return radeon->dri.context->driReadablePriv; 512f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 513f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 514f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgGLboolean radeonInitContext(radeonContextPtr radeon, 515f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct dd_function_table* functions, 516f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org const struct gl_config * glVisual, 517f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __DRIcontext * driContextPriv, 518f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org void *sharedContextPrivate); 519f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 520f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid radeonCleanupContext(radeonContextPtr radeon); 521f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgGLboolean radeonUnbindContext(__DRIcontext * driContextPriv); 522f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable, 523f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLboolean front_only); 524f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgGLboolean radeonMakeCurrent(__DRIcontext * driContextPriv, 525f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __DRIdrawable * driDrawPriv, 526f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __DRIdrawable * driReadPriv); 527f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgextern void radeonDestroyContext(__DRIcontext * driContextPriv); 528f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid radeon_prepare_render(radeonContextPtr radeon); 529f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 530f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#endif 531