1// Protocol Buffers - Google's data interchange format
2// Copyright 2012 Google Inc.  All rights reserved.
3// http://code.google.com/p/protobuf/
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30
31// This module gets enough CPU information to optimize the
32// atomicops module on x86.
33
34#include <cstring>
35
36#include <google/protobuf/stubs/atomicops.h>
37
38// This file only makes sense with atomicops_internals_x86_gcc.h -- it
39// depends on structs that are defined in that file.  If atomicops.h
40// doesn't sub-include that file, then we aren't needed, and shouldn't
41// try to do anything.
42#ifdef GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_X86_GCC_H_
43
44// Inline cpuid instruction.  In PIC compilations, %ebx contains the address
45// of the global offset table.  To avoid breaking such executables, this code
46// must preserve that register's value across cpuid instructions.
47#if defined(__i386__)
48#define cpuid(a, b, c, d, inp) \
49  asm("mov %%ebx, %%edi\n"     \
50      "cpuid\n"                \
51      "xchg %%edi, %%ebx\n"    \
52      : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
53#elif defined(__x86_64__)
54#define cpuid(a, b, c, d, inp) \
55  asm("mov %%rbx, %%rdi\n"     \
56      "cpuid\n"                \
57      "xchg %%rdi, %%rbx\n"    \
58      : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp))
59#endif
60
61#if defined(cpuid)        // initialize the struct only on x86
62
63namespace google {
64namespace protobuf {
65namespace internal {
66
67// Set the flags so that code will run correctly and conservatively, so even
68// if we haven't been initialized yet, we're probably single threaded, and our
69// default values should hopefully be pretty safe.
70struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
71  false,          // bug can't exist before process spawns multiple threads
72  false,          // no SSE2
73};
74
75namespace {
76
77// Initialize the AtomicOps_Internalx86CPUFeatures struct.
78void AtomicOps_Internalx86CPUFeaturesInit() {
79  uint32_t eax;
80  uint32_t ebx;
81  uint32_t ecx;
82  uint32_t edx;
83
84  // Get vendor string (issue CPUID with eax = 0)
85  cpuid(eax, ebx, ecx, edx, 0);
86  char vendor[13];
87  memcpy(vendor, &ebx, 4);
88  memcpy(vendor + 4, &edx, 4);
89  memcpy(vendor + 8, &ecx, 4);
90  vendor[12] = 0;
91
92  // get feature flags in ecx/edx, and family/model in eax
93  cpuid(eax, ebx, ecx, edx, 1);
94
95  int family = (eax >> 8) & 0xf;        // family and model fields
96  int model = (eax >> 4) & 0xf;
97  if (family == 0xf) {                  // use extended family and model fields
98    family += (eax >> 20) & 0xff;
99    model += ((eax >> 16) & 0xf) << 4;
100  }
101
102  // Opteron Rev E has a bug in which on very rare occasions a locked
103  // instruction doesn't act as a read-acquire barrier if followed by a
104  // non-locked read-modify-write instruction.  Rev F has this bug in
105  // pre-release versions, but not in versions released to customers,
106  // so we test only for Rev E, which is family 15, model 32..63 inclusive.
107  if (strcmp(vendor, "AuthenticAMD") == 0 &&       // AMD
108      family == 15 &&
109      32 <= model && model <= 63) {
110    AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
111  } else {
112    AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
113  }
114
115  // edx bit 26 is SSE2 which we use to tell use whether we can use mfence
116  AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
117}
118
119class AtomicOpsx86Initializer {
120 public:
121  AtomicOpsx86Initializer() {
122    AtomicOps_Internalx86CPUFeaturesInit();
123  }
124};
125
126// A global to get use initialized on startup via static initialization :/
127AtomicOpsx86Initializer g_initer;
128
129}  // namespace
130
131}  // namespace internal
132}  // namespace protobuf
133}  // namespace google
134
135#endif  // __i386__
136
137#endif  // GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_X86_GCC_H_
138