1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6#define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// ARM-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15  V(ArmAdd)                        \
16  V(ArmAnd)                        \
17  V(ArmBic)                        \
18  V(ArmCmp)                        \
19  V(ArmCmn)                        \
20  V(ArmTst)                        \
21  V(ArmTeq)                        \
22  V(ArmOrr)                        \
23  V(ArmEor)                        \
24  V(ArmSub)                        \
25  V(ArmRsb)                        \
26  V(ArmMul)                        \
27  V(ArmMla)                        \
28  V(ArmMls)                        \
29  V(ArmSdiv)                       \
30  V(ArmUdiv)                       \
31  V(ArmMov)                        \
32  V(ArmMvn)                        \
33  V(ArmBfc)                        \
34  V(ArmUbfx)                       \
35  V(ArmVcmpF64)                    \
36  V(ArmVaddF64)                    \
37  V(ArmVsubF64)                    \
38  V(ArmVmulF64)                    \
39  V(ArmVmlaF64)                    \
40  V(ArmVmlsF64)                    \
41  V(ArmVdivF64)                    \
42  V(ArmVmodF64)                    \
43  V(ArmVnegF64)                    \
44  V(ArmVsqrtF64)                   \
45  V(ArmVcvtF64S32)                 \
46  V(ArmVcvtF64U32)                 \
47  V(ArmVcvtS32F64)                 \
48  V(ArmVcvtU32F64)                 \
49  V(ArmVldr32)                     \
50  V(ArmVstr32)                     \
51  V(ArmVldr64)                     \
52  V(ArmVstr64)                     \
53  V(ArmLdrb)                       \
54  V(ArmLdrsb)                      \
55  V(ArmStrb)                       \
56  V(ArmLdrh)                       \
57  V(ArmLdrsh)                      \
58  V(ArmStrh)                       \
59  V(ArmLdr)                        \
60  V(ArmStr)                        \
61  V(ArmPush)                       \
62  V(ArmStoreWriteBarrier)
63
64
65// Addressing modes represent the "shape" of inputs to an instruction.
66// Many instructions support multiple addressing modes. Addressing modes
67// are encoded into the InstructionCode of the instruction and tell the
68// code generator after register allocation which assembler method to call.
69#define TARGET_ADDRESSING_MODE_LIST(V)  \
70  V(Offset_RI)        /* [%r0 + K] */   \
71  V(Offset_RR)        /* [%r0 + %r1] */ \
72  V(Operand2_I)       /* K */           \
73  V(Operand2_R)       /* %r0 */         \
74  V(Operand2_R_ASR_I) /* %r0 ASR K */   \
75  V(Operand2_R_LSL_I) /* %r0 LSL K */   \
76  V(Operand2_R_LSR_I) /* %r0 LSR K */   \
77  V(Operand2_R_ROR_I) /* %r0 ROR K */   \
78  V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
79  V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
80  V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
81  V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
82
83}  // namespace compiler
84}  // namespace internal
85}  // namespace v8
86
87#endif  // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
88