1//===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TableGen definitions from which the ARM NEON header 11// file will be generated. See ARM document DUI0348B. 12// 13//===----------------------------------------------------------------------===// 14// 15// Each intrinsic is a subclass of the Inst class. An intrinsic can either 16// generate a __builtin_* call or it can expand to a set of generic operations. 17// 18// The operations are subclasses of Operation providing a list of DAGs, the 19// last of which is the return value. The available DAG nodes are documented 20// below. 21// 22//===----------------------------------------------------------------------===// 23 24// The base Operation class. All operations must subclass this. 25class Operation<list<dag> ops=[]> { 26 list<dag> Ops = ops; 27 bit Unavailable = 0; 28} 29// An operation that only contains a single DAG. 30class Op<dag op> : Operation<[op]>; 31// A shorter version of Operation - takes a list of DAGs. The last of these will 32// be the return value. 33class LOp<list<dag> ops> : Operation<ops>; 34 35// These defs and classes are used internally to implement the SetTheory 36// expansion and should be ignored. 37foreach Index = 0-63 in 38 def sv##Index; 39class MaskExpand; 40 41//===----------------------------------------------------------------------===// 42// Available operations 43//===----------------------------------------------------------------------===// 44 45// DAG arguments can either be operations (documented below) or variables. 46// Variables are prefixed with '$'. There are variables for each input argument, 47// with the name $pN, where N starts at zero. So the zero'th argument will be 48// $p0, the first $p1 etc. 49 50// op - Binary or unary operator, depending on the number of arguments. The 51// operator itself is just treated as a raw string and is not checked. 52// example: (op "+", $p0, $p1) -> "__p0 + __p1". 53// (op "-", $p0) -> "-__p0" 54def op; 55// call - Invoke another intrinsic. The input types are type checked and 56// disambiguated. If there is no intrinsic defined that takes 57// the given types (or if there is a type ambiguity) an error is 58// generated at tblgen time. The name of the intrinsic is the raw 59// name as given to the Inst class (not mangled). 60// example: (call "vget_high", $p0) -> "vgetq_high_s16(__p0)" 61// (assuming $p0 has type int16x8_t). 62def call; 63// cast - Perform a cast to a different type. This gets emitted as a static 64// C-style cast. For a pure reinterpret cast (T x = *(T*)&y), use 65// "bitcast". 66// 67// The syntax is (cast MOD* VAL). The last argument is the value to 68// cast, preceded by a sequence of type modifiers. The target type 69// starts off as the type of VAL, and is modified by MOD in sequence. 70// The available modifiers are: 71// - $X - Take the type of parameter/variable X. For example: 72// (cast $p0, $p1) would cast $p1 to the type of $p0. 73// - "R" - The type of the return type. 74// - A typedef string - A NEON or stdint.h type that is then parsed. 75// for example: (cast "uint32x4_t", $p0). 76// - "U" - Make the type unsigned. 77// - "S" - Make the type signed. 78// - "H" - Halve the number of lanes in the type. 79// - "D" - Double the number of lanes in the type. 80// - "8" - Convert type to an equivalent vector of 8-bit signed 81// integers. 82// example: (cast "R", "U", $p0) -> "(uint32x4_t)__p0" (assuming the return 83// value is of type "int32x4_t". 84// (cast $p0, "D", "8", $p1) -> "(int8x16_t)__p1" (assuming __p0 85// has type float64x1_t or any other vector type of 64 bits). 86// (cast "int32_t", $p2) -> "(int32_t)__p2" 87def cast; 88// bitcast - Same as "cast", except a reinterpret-cast is produced: 89// (bitcast "T", $p0) -> "*(T*)&__p0". 90// The VAL argument is saved to a temprary so it can be used 91// as an l-value. 92def bitcast; 93// dup - Take a scalar argument and create a vector by duplicating it into 94// all lanes. The type of the vector is the base type of the intrinsic. 95// example: (dup $p1) -> "(uint32x2_t) {__p1, __p1}" (assuming the base type 96// is uint32x2_t). 97def dup; 98// splat - Take a vector and a lane index, and return a vector of the same type 99// containing repeated instances of the source vector at the lane index. 100// example: (splat $p0, $p1) -> 101// "__builtin_shufflevector(__p0, __p0, __p1, __p1, __p1, __p1)" 102// (assuming __p0 has four elements). 103def splat; 104// save_temp - Create a temporary (local) variable. The variable takes a name 105// based on the zero'th parameter and can be referenced using 106// using that name in subsequent DAGs in the same 107// operation. The scope of a temp is the operation. If a variable 108// with the given name already exists, an error will be given at 109// tblgen time. 110// example: [(save_temp $var, (call "foo", $p0)), 111// (op "+", $var, $p1)] -> 112// "int32x2_t __var = foo(__p0); return __var + __p1;" 113def save_temp; 114// name_replace - Return the name of the current intrinsic with the first 115// argument replaced by the second argument. Raises an error if 116// the first argument does not exist in the intrinsic name. 117// example: (call (name_replace "_high_", "_"), $p0) (to call the non-high 118// version of this intrinsic). 119def name_replace; 120// literal - Create a literal piece of code. The code is treated as a raw 121// string, and must be given a type. The type is a stdint.h or 122// NEON intrinsic type as given to (cast). 123// example: (literal "int32_t", "0") 124def literal; 125// shuffle - Create a vector shuffle. The syntax is (shuffle ARG0, ARG1, MASK). 126// The MASK argument is a set of elements. The elements are generated 127// from the two special defs "mask0" and "mask1". "mask0" expands to 128// the lane indices in sequence for ARG0, and "mask1" expands to 129// the lane indices in sequence for ARG1. They can be used as-is, e.g. 130// 131// (shuffle $p0, $p1, mask0) -> $p0 132// (shuffle $p0, $p1, mask1) -> $p1 133// 134// or, more usefully, they can be manipulated using the SetTheory 135// operators plus some extra operators defined in the NEON emitter. 136// The operators are described below. 137// example: (shuffle $p0, $p1, (add (highhalf mask0), (highhalf mask1))) -> 138// A concatenation of the high halves of the input vectors. 139def shuffle; 140 141// add, interleave, decimate: These set operators are vanilla SetTheory 142// operators and take their normal definition. 143def add; 144def interleave; 145def decimate; 146// rotl - Rotate set left by a number of elements. 147// example: (rotl mask0, 3) -> [3, 4, 5, 6, 0, 1, 2] 148def rotl; 149// rotl - Rotate set right by a number of elements. 150// example: (rotr mask0, 3) -> [4, 5, 6, 0, 1, 2, 3] 151def rotr; 152// highhalf - Take only the high half of the input. 153// example: (highhalf mask0) -> [4, 5, 6, 7] (assuming mask0 had 8 elements) 154def highhalf; 155// highhalf - Take only the low half of the input. 156// example: (lowhalf mask0) -> [0, 1, 2, 3] (assuming mask0 had 8 elements) 157def lowhalf; 158// rev - Perform a variable-width reversal of the elements. The zero'th argument 159// is a width in bits to reverse. The lanes this maps to is determined 160// based on the element width of the underlying type. 161// example: (rev 32, mask0) -> [3, 2, 1, 0, 7, 6, 5, 4] (if 8-bit elements) 162// example: (rev 32, mask0) -> [1, 0, 3, 2] (if 16-bit elements) 163def rev; 164// mask0 - The initial sequence of lanes for shuffle ARG0 165def mask0 : MaskExpand; 166// mask0 - The initial sequence of lanes for shuffle ARG1 167def mask1 : MaskExpand; 168 169def OP_NONE : Operation; 170def OP_UNAVAILABLE : Operation { 171 let Unavailable = 1; 172} 173 174//===----------------------------------------------------------------------===// 175// Instruction definitions 176//===----------------------------------------------------------------------===// 177 178// Every intrinsic subclasses "Inst". An intrinsic has a name, a prototype and 179// a sequence of typespecs. 180// 181// The name is the base name of the intrinsic, for example "vget_lane". This is 182// then mangled by the tblgen backend to add type information ("vget_lane_s16"). 183// 184// A typespec is a sequence of uppercase characters (modifiers) followed by one 185// lowercase character. A typespec encodes a particular "base type" of the 186// intrinsic. 187// 188// An example typespec is "Qs" - quad-size short - uint16x8_t. The available 189// typespec codes are given below. 190// 191// The string given to an Inst class is a sequence of typespecs. The intrinsic 192// is instantiated for every typespec in the sequence. For example "sdQsQd". 193// 194// The prototype is a string that defines the return type of the intrinsic 195// and the type of each argument. The return type and every argument gets a 196// "modifier" that can change in some way the "base type" of the intrinsic. 197// 198// The modifier 'd' means "default" and does not modify the base type in any 199// way. The available modifiers are given below. 200// 201// Typespecs 202// --------- 203// c: char 204// s: short 205// i: int 206// l: long 207// k: 128-bit long 208// f: float 209// h: half-float 210// d: double 211// 212// Typespec modifiers 213// ------------------ 214// S: scalar, only used for function mangling. 215// U: unsigned 216// Q: 128b 217// H: 128b without mangling 'q' 218// P: polynomial 219// 220// Prototype modifiers 221// ------------------- 222// prototype: return (arg, arg, ...) 223// 224// v: void 225// t: best-fit integer (int/poly args) 226// x: signed integer (int/float args) 227// u: unsigned integer (int/float args) 228// f: float (int args) 229// F: double (int args) 230// d: default 231// g: default, ignore 'Q' size modifier. 232// j: default, force 'Q' size modifier. 233// w: double width elements, same num elts 234// n: double width elements, half num elts 235// h: half width elements, double num elts 236// q: half width elements, quad num elts 237// e: half width elements, double num elts, unsigned 238// m: half width elements, same num elts 239// i: constant int 240// l: constant uint64 241// s: scalar of element type 242// z: scalar of half width element type, signed 243// r: scalar of double width element type, signed 244// a: scalar of element type (splat to vector type) 245// b: scalar of unsigned integer/long type (int/float args) 246// $: scalar of signed integer/long type (int/float args) 247// y: scalar of float 248// o: scalar of double 249// k: default elt width, double num elts 250// 2,3,4: array of default vectors 251// B,C,D: array of default elts, force 'Q' size modifier. 252// p: pointer type 253// c: const pointer type 254 255// Every intrinsic subclasses Inst. 256class Inst <string n, string p, string t, Operation o> { 257 string Name = n; 258 string Prototype = p; 259 string Types = t; 260 string ArchGuard = ""; 261 262 Operation Operation = o; 263 bit CartesianProductOfTypes = 0; 264 bit BigEndianSafe = 0; 265 bit isShift = 0; 266 bit isScalarShift = 0; 267 bit isScalarNarrowShift = 0; 268 bit isVCVT_N = 0; 269 // For immediate checks: the immediate will be assumed to specify the lane of 270 // a Q register. Only used for intrinsics which end up calling polymorphic 271 // builtins. 272 bit isLaneQ = 0; 273 274 // Certain intrinsics have different names than their representative 275 // instructions. This field allows us to handle this correctly when we 276 // are generating tests. 277 string InstName = ""; 278 279 // Certain intrinsics even though they are not a WOpInst or LOpInst, 280 // generate a WOpInst/LOpInst instruction (see below for definition 281 // of a WOpInst/LOpInst). For testing purposes we need to know 282 // this. Ex: vset_lane which outputs vmov instructions. 283 bit isHiddenWInst = 0; 284 bit isHiddenLInst = 0; 285} 286 287// The following instruction classes are implemented via builtins. 288// These declarations are used to generate Builtins.def: 289// 290// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 291// IInst: Instruction with generic integer suffix (e.g., "i8") 292// WInst: Instruction with only bit size suffix (e.g., "8") 293class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 294class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 295class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 296 297// The following instruction classes are implemented via operators 298// instead of builtins. As such these declarations are only used for 299// the purpose of generating tests. 300// 301// SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 302// "u8", "p8"). 303// IOpInst: Instruction with generic integer suffix (e.g., "i8"). 304// WOpInst: Instruction with bit size only suffix (e.g., "8"). 305// LOpInst: Logical instruction with no bit size suffix. 306// NoTestOpInst: Intrinsic that has no corresponding instruction. 307class SOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 308class IOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 309class WOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 310class LOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 311class NoTestOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 312 313//===----------------------------------------------------------------------===// 314// Operations 315//===----------------------------------------------------------------------===// 316 317def OP_ADD : Op<(op "+", $p0, $p1)>; 318def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>; 319def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0), 320 (call "vmovl_high", $p1))>; 321def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>; 322def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>; 323def OP_SUB : Op<(op "-", $p0, $p1)>; 324def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>; 325def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0), 326 (call "vmovl_high", $p1))>; 327def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>; 328def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>; 329def OP_MUL : Op<(op "*", $p0, $p1)>; 330def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>; 331def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>; 332def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0), 333 (call "vget_high", $p1))>; 334def OP_MULLHi_P64 : Op<(call "vmull", 335 (cast "poly64_t", (call "vget_high", $p0)), 336 (cast "poly64_t", (call "vget_high", $p1)))>; 337def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>; 338def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1), 339 (call "vget_high", $p2))>; 340def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>; 341def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>; 342def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>; 343def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1), 344 (call "vget_high", $p2))>; 345def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 346def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>; 347def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>; 348def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>; 349def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>; 350def OP_FMLS_N : Op<(call "vfms", $p0, $p1, (dup $p2))>; 351def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>; 352def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>; 353def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>; 354def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>; 355def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>; 356def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>; 357def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>; 358def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>; 359def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 360def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1), 361 (splat $p2, $p3)))>; 362def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 363def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1), 364 (splat $p2, $p3)))>; 365def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>; 366def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0), 367 (splat $p1, $p2))>; 368def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (splat $p2, $p3))>; 369def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 370 (splat $p2, $p3))>; 371def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>; 372def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 373 (splat $p2, $p3))>; 374def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>; 375def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>; 376def OP_FMS_LN : Op<(call "vfma_lane", $p0, $p1, (op "-", $p2), $p3)>; 377def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, $p1, (op "-", $p2), $p3)>; 378def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2), 379 (decimate mask1, 2)))>; 380def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>; 381def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2), 382 (decimate mask1, 2)))>; 383def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave 384 (decimate (rotl mask0, 1), 2), 385 (decimate (rotl mask1, 1), 2)))>; 386def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>; 387def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2), 388 (decimate (rotl mask1, 1), 2)))>; 389def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>; 390def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>; 391def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>; 392def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>; 393def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>; 394def OP_NEG : Op<(op "-", $p0)>; 395def OP_NOT : Op<(op "~", $p0)>; 396def OP_AND : Op<(op "&", $p0, $p1)>; 397def OP_OR : Op<(op "|", $p0, $p1)>; 398def OP_XOR : Op<(op "^", $p0, $p1)>; 399def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>; 400def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>; 401def OP_CAST : Op<(cast "R", $p0)>; 402def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>; 403def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>; 404def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>; 405def OP_DUP : Op<(dup $p0)>; 406def OP_DUP_LN : Op<(splat $p0, $p1)>; 407def OP_SEL : Op<(cast "R", (op "|", 408 (op "&", $p0, (cast $p0, $p1)), 409 (op "&", (op "~", $p0), (cast $p0, $p2))))>; 410def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>; 411def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>; 412def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>; 413def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>; 414def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0), 415 (call "vqmovun", $p1))>; 416def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>; 417def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16", $p1))>; 418def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>; 419def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>; 420def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>; 421def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>; 422def OP_REINT : Op<(cast "R", $p0)>; 423def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>; 424def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>; 425def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>; 426def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>; 427def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U", 428 (call "vabd", $p0, $p1))))>; 429def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0), 430 (call "vget_high", $p1))>; 431def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>; 432def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>; 433def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1), 434 (call "vget_high", $p2))>; 435def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0), 436 (call "vget_high", $p1))>; 437def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>; 438def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 439 (call "vget_high", $p2))>; 440def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>; 441def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 442 (call "vget_high", $p2))>; 443def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 444def OP_DIV : Op<(op "/", $p0, $p1)>; 445def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"), 446 (call "vget_high", $p0), $p1))>; 447def OP_NARROW_HI : Op<(cast "R", (call "vcombine", 448 (cast "R", "H", $p0), 449 (cast "R", "H", 450 (call (name_replace "_high_", "_"), 451 $p1, $p2))))>; 452def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)), 453 (cast "R", 454 (call "vshll_n", $a1, (literal "int32_t", "0")))]>; 455def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>; 456def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>; 457def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>; 458def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0, 459 (literal "int32_t", "0"))), 460 (save_temp $y, (call "vget_lane", $p1, $p2)), 461 (save_temp $z, (call "vmulx", $x, $y)), 462 (call "vset_lane", $z, $p0, $p2)]>; 463def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0, 464 (literal "int32_t", "0"))), 465 (save_temp $y, (call "vget_lane", $p1, $p2)), 466 (save_temp $z, (call "vmulx", $x, $y)), 467 (call "vset_lane", $z, $p0, (literal "int32_t", 468 "0"))]>; 469class ScalarMulOp<string opname> : 470 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>; 471 472def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">; 473def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">; 474def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">; 475 476def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t", 477 (call "vget_lane", 478 (bitcast "int16x4_t", $p0), $p1))>; 479def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t", 480 (call "vget_lane", 481 (bitcast "int16x8_t", $p0), $p1))>; 482def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t", 483 (call "vset_lane", 484 (bitcast "int16_t", $p0), 485 (bitcast "int16x4_t", $p1), $p2))>; 486def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t", 487 (call "vset_lane", 488 (bitcast "int16_t", $p0), 489 (bitcast "int16x8_t", $p1), $p2))>; 490 491//===----------------------------------------------------------------------===// 492// Instructions 493//===----------------------------------------------------------------------===// 494 495//////////////////////////////////////////////////////////////////////////////// 496// E.3.1 Addition 497def VADD : IOpInst<"vadd", "ddd", 498 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 499def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 500def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 501def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 502def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 503def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 504def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 505def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 506 507//////////////////////////////////////////////////////////////////////////////// 508// E.3.2 Multiplication 509def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 510def VMULP : SInst<"vmul", "ddd", "PcQPc">; 511def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 512def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 513def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 514def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 515def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 516def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 517def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 518def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 519def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 520def VQDMULL : SInst<"vqdmull", "wdd", "si">; 521 522//////////////////////////////////////////////////////////////////////////////// 523// E.3.3 Subtraction 524def VSUB : IOpInst<"vsub", "ddd", 525 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 526def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 527def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 528def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 529def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 530def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 531def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 532 533//////////////////////////////////////////////////////////////////////////////// 534// E.3.4 Comparison 535def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 536def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 537let InstName = "vcge" in 538def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 539def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 540let InstName = "vcgt" in 541def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 542let InstName = "vacge" in { 543def VCAGE : IInst<"vcage", "udd", "fQf">; 544def VCALE : IInst<"vcale", "udd", "fQf">; 545} 546let InstName = "vacgt" in { 547def VCAGT : IInst<"vcagt", "udd", "fQf">; 548def VCALT : IInst<"vcalt", "udd", "fQf">; 549} 550def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">; 551 552//////////////////////////////////////////////////////////////////////////////// 553// E.3.5 Absolute Difference 554def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 555def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 556def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 557def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 558 559//////////////////////////////////////////////////////////////////////////////// 560// E.3.6 Max/Min 561def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 562def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 563 564//////////////////////////////////////////////////////////////////////////////// 565// E.3.7 Pairwise Addition 566def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 567def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 568def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 569 570//////////////////////////////////////////////////////////////////////////////// 571// E.3.8-9 Folding Max/Min 572def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 573def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 574 575//////////////////////////////////////////////////////////////////////////////// 576// E.3.10 Reciprocal/Sqrt 577def VRECPS : IInst<"vrecps", "ddd", "fQf">; 578def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 579 580//////////////////////////////////////////////////////////////////////////////// 581// E.3.11 Shifts by signed variable 582def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 583def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 584def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 585def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 586 587//////////////////////////////////////////////////////////////////////////////// 588// E.3.12 Shifts by constant 589let isShift = 1 in { 590def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 591def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 592def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 593def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 594def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 595def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 596def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 597def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 598def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 599def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 600def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 601def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 602def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 603def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 604 605//////////////////////////////////////////////////////////////////////////////// 606// E.3.13 Shifts with insert 607def VSRI_N : WInst<"vsri_n", "dddi", 608 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 609def VSLI_N : WInst<"vsli_n", "dddi", 610 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 611} 612 613//////////////////////////////////////////////////////////////////////////////// 614// E.3.14 Loads and stores of a single vector 615def VLD1 : WInst<"vld1", "dc", 616 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 617def VLD1_LANE : WInst<"vld1_lane", "dcdi", 618 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 619def VLD1_DUP : WInst<"vld1_dup", "dc", 620 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 621def VST1 : WInst<"vst1", "vpd", 622 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 623def VST1_LANE : WInst<"vst1_lane", "vpdi", 624 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 625 626//////////////////////////////////////////////////////////////////////////////// 627// E.3.15 Loads and stores of an N-element structure 628def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 629def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 630def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 631def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 632def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 633def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 634def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 635def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 636def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 637def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 638def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 639def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 640def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 641def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 642def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 643 644//////////////////////////////////////////////////////////////////////////////// 645// E.3.16 Extract lanes from a vector 646let InstName = "vmov" in 647def VGET_LANE : IInst<"vget_lane", "sdi", 648 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 649 650//////////////////////////////////////////////////////////////////////////////// 651// E.3.17 Set lanes within a vector 652let InstName = "vmov" in 653def VSET_LANE : IInst<"vset_lane", "dsdi", 654 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 655 656//////////////////////////////////////////////////////////////////////////////// 657// E.3.18 Initialize a vector from bit pattern 658def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST> { 659 let BigEndianSafe = 1; 660} 661 662//////////////////////////////////////////////////////////////////////////////// 663// E.3.19 Set all lanes to same value 664let InstName = "vmov" in { 665def VDUP_N : WOpInst<"vdup_n", "ds", 666 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 667 OP_DUP>; 668def VMOV_N : WOpInst<"vmov_n", "ds", 669 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 670 OP_DUP>; 671} 672let InstName = "" in 673def VDUP_LANE: WOpInst<"vdup_lane", "dgi", 674 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 675 OP_DUP_LN>; 676 677//////////////////////////////////////////////////////////////////////////////// 678// E.3.20 Combining vectors 679def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 680 681//////////////////////////////////////////////////////////////////////////////// 682// E.3.21 Splitting vectors 683let InstName = "vmov" in { 684def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 685def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 686} 687 688//////////////////////////////////////////////////////////////////////////////// 689// E.3.22 Converting vectors 690def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 691def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 692def VCVT_F16 : SInst<"vcvt_f16", "hk", "f">; 693def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 694def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "fd", "h">; 695let isVCVT_N = 1 in { 696def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 697def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 698def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 699} 700def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 701def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 702def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 703def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 704 705//////////////////////////////////////////////////////////////////////////////// 706// E.3.23-24 Table lookup, Extended table lookup 707let InstName = "vtbl" in { 708def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 709def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 710def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 711def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 712} 713let InstName = "vtbx" in { 714def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 715def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 716def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 717def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 718} 719 720//////////////////////////////////////////////////////////////////////////////// 721// E.3.25 Operations with a scalar value 722def VMLA_LANE : IOpInst<"vmla_lane", "dddgi", 723 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 724def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 725def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 726def VMLS_LANE : IOpInst<"vmls_lane", "dddgi", 727 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 728def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 729def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 730def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 731def VMUL_LANE : IOpInst<"vmul_lane", "ddgi", 732 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 733def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 734def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 735def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 736def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 737def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 738def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 739def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 740def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 741def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 742def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 743def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 744def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 745def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 746def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 747 748//////////////////////////////////////////////////////////////////////////////// 749// E.3.26 Vector Extract 750def VEXT : WInst<"vext", "dddi", 751 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 752 753//////////////////////////////////////////////////////////////////////////////// 754// E.3.27 Reverse vector elements 755def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 756 OP_REV64>; 757def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 758def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 759 760//////////////////////////////////////////////////////////////////////////////// 761// E.3.28 Other single operand arithmetic 762def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 763def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 764def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 765def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 766def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 767def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 768def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 769def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 770def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 771 772//////////////////////////////////////////////////////////////////////////////// 773// E.3.29 Logical operations 774def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 775def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 776def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 777def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 778def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 779def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 780let isHiddenLInst = 1 in 781def VBSL : SInst<"vbsl", "dudd", 782 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 783 784//////////////////////////////////////////////////////////////////////////////// 785// E.3.30 Transposition operations 786def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 787def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 788def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 789 790//////////////////////////////////////////////////////////////////////////////// 791// E.3.31 Vector reinterpret cast operations 792def VREINTERPRET 793 : NoTestOpInst<"vreinterpret", "dd", 794 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> { 795 let CartesianProductOfTypes = 1; 796 let ArchGuard = "!defined(__aarch64__)"; 797 let BigEndianSafe = 1; 798} 799 800//////////////////////////////////////////////////////////////////////////////// 801// Vector fused multiply-add operations 802 803def VFMA : SInst<"vfma", "dddd", "fQf">; 804 805//////////////////////////////////////////////////////////////////////////////// 806// AArch64 Intrinsics 807 808let ArchGuard = "defined(__aarch64__)" in { 809 810//////////////////////////////////////////////////////////////////////////////// 811// Load/Store 812def LD1 : WInst<"vld1", "dc", "dQdPlQPl">; 813def LD2 : WInst<"vld2", "2c", "QUlQldQdPlQPl">; 814def LD3 : WInst<"vld3", "3c", "QUlQldQdPlQPl">; 815def LD4 : WInst<"vld4", "4c", "QUlQldQdPlQPl">; 816def ST1 : WInst<"vst1", "vpd", "dQdPlQPl">; 817def ST2 : WInst<"vst2", "vp2", "QUlQldQdPlQPl">; 818def ST3 : WInst<"vst3", "vp3", "QUlQldQdPlQPl">; 819def ST4 : WInst<"vst4", "vp4", "QUlQldQdPlQPl">; 820 821def LD1_X2 : WInst<"vld1_x2", "2c", 822 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 823def LD3_x3 : WInst<"vld1_x3", "3c", 824 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 825def LD4_x4 : WInst<"vld1_x4", "4c", 826 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 827 828def ST1_X2 : WInst<"vst1_x2", "vp2", 829 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 830def ST1_X3 : WInst<"vst1_x3", "vp3", 831 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 832def ST1_X4 : WInst<"vst1_x4", "vp4", 833 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 834 835def LD1_LANE : WInst<"vld1_lane", "dcdi", "dQdPlQPl">; 836def LD2_LANE : WInst<"vld2_lane", "2c2i", "lUlQcQUcQPcQlQUldQdPlQPl">; 837def LD3_LANE : WInst<"vld3_lane", "3c3i", "lUlQcQUcQPcQlQUldQdPlQPl">; 838def LD4_LANE : WInst<"vld4_lane", "4c4i", "lUlQcQUcQPcQlQUldQdPlQPl">; 839def ST1_LANE : WInst<"vst1_lane", "vpdi", "dQdPlQPl">; 840def ST2_LANE : WInst<"vst2_lane", "vp2i", "lUlQcQUcQPcQlQUldQdPlQPl">; 841def ST3_LANE : WInst<"vst3_lane", "vp3i", "lUlQcQUcQPcQlQUldQdPlQPl">; 842def ST4_LANE : WInst<"vst4_lane", "vp4i", "lUlQcQUcQPcQlQUldQdPlQPl">; 843 844def LD1_DUP : WInst<"vld1_dup", "dc", "dQdPlQPl">; 845def LD2_DUP : WInst<"vld2_dup", "2c", 846 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 847def LD3_DUP : WInst<"vld3_dup", "3c", 848 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 849def LD4_DUP : WInst<"vld4_dup", "4c", 850 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 851 852def VLDRQ : WInst<"vldrq", "sc", "Pk">; 853def VSTRQ : WInst<"vstrq", "vps", "Pk">; 854 855//////////////////////////////////////////////////////////////////////////////// 856// Addition 857def ADD : IOpInst<"vadd", "ddd", "dQd", OP_ADD>; 858 859//////////////////////////////////////////////////////////////////////////////// 860// Subtraction 861def SUB : IOpInst<"vsub", "ddd", "dQd", OP_SUB>; 862 863//////////////////////////////////////////////////////////////////////////////// 864// Multiplication 865def MUL : IOpInst<"vmul", "ddd", "dQd", OP_MUL>; 866def MLA : IOpInst<"vmla", "dddd", "dQd", OP_MLA>; 867def MLS : IOpInst<"vmls", "dddd", "dQd", OP_MLS>; 868 869//////////////////////////////////////////////////////////////////////////////// 870// Multiplication Extended 871def MULX : SInst<"vmulx", "ddd", "fdQfQd">; 872 873//////////////////////////////////////////////////////////////////////////////// 874// Division 875def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>; 876 877//////////////////////////////////////////////////////////////////////////////// 878// Vector fused multiply-add operations 879def FMLA : SInst<"vfma", "dddd", "dQd">; 880def FMLS : SInst<"vfms", "dddd", "fdQfQd">; 881 882//////////////////////////////////////////////////////////////////////////////// 883// MUL, MLA, MLS, FMA, FMS definitions with scalar argument 884def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>; 885 886def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>; 887def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>; 888 889def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>; 890def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>; 891 892//////////////////////////////////////////////////////////////////////////////// 893// Logical operations 894def BSL : SInst<"vbsl", "dudd", "dPlQdQPl">; 895 896//////////////////////////////////////////////////////////////////////////////// 897// Absolute Difference 898def ABD : SInst<"vabd", "ddd", "dQd">; 899 900//////////////////////////////////////////////////////////////////////////////// 901// saturating absolute/negate 902def ABS : SInst<"vabs", "dd", "dQdlQl">; 903def QABS : SInst<"vqabs", "dd", "lQl">; 904def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>; 905def QNEG : SInst<"vqneg", "dd", "lQl">; 906 907//////////////////////////////////////////////////////////////////////////////// 908// Signed Saturating Accumulated of Unsigned Value 909def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">; 910 911//////////////////////////////////////////////////////////////////////////////// 912// Unsigned Saturating Accumulated of Signed Value 913def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">; 914 915//////////////////////////////////////////////////////////////////////////////// 916// Reciprocal/Sqrt 917def FRECPS : IInst<"vrecps", "ddd", "dQd">; 918def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">; 919 920//////////////////////////////////////////////////////////////////////////////// 921// bitwise reverse 922def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">; 923 924//////////////////////////////////////////////////////////////////////////////// 925// Integer extract and narrow to high 926def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>; 927 928//////////////////////////////////////////////////////////////////////////////// 929// Signed integer saturating extract and unsigned narrow to high 930def SQXTUN2 : SOpInst<"vqmovun_high", "qhk", "sil", OP_SQXTUN>; 931 932//////////////////////////////////////////////////////////////////////////////// 933// Integer saturating extract and narrow to high 934def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>; 935 936//////////////////////////////////////////////////////////////////////////////// 937// Converting vectors 938def VCVT_HIGH_F16 : SOpInst<"vcvt_high_f16", "qhj", "f", OP_VCVT_NA_HI_F16>; 939def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>; 940def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "md", "Qd">; 941def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>; 942def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">; 943def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">; 944def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>; 945def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; 946def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>; 947def FRINTN : SInst<"vrndn", "dd", "fdQfQd">; 948def FRINTA : SInst<"vrnda", "dd", "fdQfQd">; 949def FRINTP : SInst<"vrndp", "dd", "fdQfQd">; 950def FRINTM : SInst<"vrndm", "dd", "fdQfQd">; 951def FRINTX : SInst<"vrndx", "dd", "fdQfQd">; 952def FRINTZ : SInst<"vrnd", "dd", "fdQfQd">; 953def FRINTI : SInst<"vrndi", "dd", "fdQfQd">; 954def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">; 955def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">; 956def FRECPE : SInst<"vrecpe", "dd", "dQd">; 957def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">; 958def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; 959 960//////////////////////////////////////////////////////////////////////////////// 961// Comparison 962def FCAGE : IInst<"vcage", "udd", "dQd">; 963def FCAGT : IInst<"vcagt", "udd", "dQd">; 964def FCALE : IInst<"vcale", "udd", "dQd">; 965def FCALT : IInst<"vcalt", "udd", "dQd">; 966def CMTST : WInst<"vtst", "udd", "lUlPlQlQUlQPl">; 967def CFMEQ : SOpInst<"vceq", "udd", "lUldQdQlQUlPlQPl", OP_EQ>; 968def CFMGE : SOpInst<"vcge", "udd", "lUldQdQlQUl", OP_GE>; 969def CFMLE : SOpInst<"vcle", "udd", "lUldQdQlQUl", OP_LE>; 970def CFMGT : SOpInst<"vcgt", "udd", "lUldQdQlQUl", OP_GT>; 971def CFMLT : SOpInst<"vclt", "udd", "lUldQdQlQUl", OP_LT>; 972 973def CMEQ : SInst<"vceqz", "ud", 974 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; 975def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">; 976def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">; 977def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">; 978def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">; 979 980//////////////////////////////////////////////////////////////////////////////// 981// Max/Min Integer 982def MAX : SInst<"vmax", "ddd", "dQd">; 983def MIN : SInst<"vmin", "ddd", "dQd">; 984 985//////////////////////////////////////////////////////////////////////////////// 986// MaxNum/MinNum Floating Point 987def FMAXNM : SInst<"vmaxnm", "ddd", "fdQfQd">; 988def FMINNM : SInst<"vminnm", "ddd", "fdQfQd">; 989 990//////////////////////////////////////////////////////////////////////////////// 991// Pairwise Max/Min 992def MAXP : SInst<"vpmax", "ddd", "QcQsQiQUcQUsQUiQfQd">; 993def MINP : SInst<"vpmin", "ddd", "QcQsQiQUcQUsQUiQfQd">; 994 995//////////////////////////////////////////////////////////////////////////////// 996// Pairwise MaxNum/MinNum Floating Point 997def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">; 998def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">; 999 1000//////////////////////////////////////////////////////////////////////////////// 1001// Pairwise Addition 1002def ADDP : IInst<"vpadd", "ddd", "QcQsQiQlQUcQUsQUiQUlQfQd">; 1003 1004//////////////////////////////////////////////////////////////////////////////// 1005// Shifts by constant 1006let isShift = 1 in { 1007// Left shift long high 1008def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi", 1009 OP_LONG_HI>; 1010 1011//////////////////////////////////////////////////////////////////////////////// 1012def SRI_N : WInst<"vsri_n", "dddi", "PlQPl">; 1013def SLI_N : WInst<"vsli_n", "dddi", "PlQPl">; 1014 1015// Right shift narrow high 1016def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi", 1017 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1018def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi", 1019 "HsHiHl", OP_NARROW_HI>; 1020def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi", 1021 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1022def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi", 1023 "HsHiHl", OP_NARROW_HI>; 1024def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi", 1025 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1026def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi", 1027 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1028} 1029 1030//////////////////////////////////////////////////////////////////////////////// 1031// Converting vectors 1032def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>; 1033 1034let isVCVT_N = 1 in { 1035def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">; 1036def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">; 1037def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">; 1038} 1039 1040//////////////////////////////////////////////////////////////////////////////// 1041// 3VDiff class using high 64-bit in operands 1042def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>; 1043def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>; 1044def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>; 1045def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>; 1046 1047def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>; 1048def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>; 1049 1050def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>; 1051def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>; 1052def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>; 1053def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>; 1054def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>; 1055def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>; 1056 1057def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>; 1058def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>; 1059def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>; 1060def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>; 1061 1062def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>; 1063def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>; 1064def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>; 1065def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>; 1066def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>; 1067def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>; 1068def VMULL_P64 : SInst<"vmull", "rss", "Pl">; 1069def VMULL_HIGH_P64 : SOpInst<"vmull_high", "rdd", "HPl", OP_MULLHi_P64>; 1070 1071 1072//////////////////////////////////////////////////////////////////////////////// 1073// Extract or insert element from vector 1074def GET_LANE : IInst<"vget_lane", "sdi", "dQdPlQPl">; 1075def SET_LANE : IInst<"vset_lane", "dsdi", "dQdPlQPl">; 1076def COPY_LANE : IOpInst<"vcopy_lane", "ddidi", 1077 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>; 1078def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi", 1079 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 1080def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki", 1081 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>; 1082def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi", 1083 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 1084 1085//////////////////////////////////////////////////////////////////////////////// 1086// Set all lanes to same value 1087def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", "hdQhQdPlQPl", OP_DUP_LN>; 1088def VDUP_LANE2: WOpInst<"vdup_laneq", "dji", 1089 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 1090 OP_DUP_LN>; 1091def DUP_N : WOpInst<"vdup_n", "ds", "dQdPlQPl", OP_DUP>; 1092def MOV_N : WOpInst<"vmov_n", "ds", "dQd", OP_DUP>; 1093 1094//////////////////////////////////////////////////////////////////////////////// 1095def COMBINE : NoTestOpInst<"vcombine", "kdd", "dPl", OP_CONC>; 1096 1097//////////////////////////////////////////////////////////////////////////////// 1098//Initialize a vector from bit pattern 1099def CREATE : NoTestOpInst<"vcreate", "dl", "dPl", OP_CAST> { 1100 let BigEndianSafe = 1; 1101} 1102 1103//////////////////////////////////////////////////////////////////////////////// 1104 1105def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji", 1106 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 1107def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji", 1108 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 1109 1110def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">; 1111def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd"> { 1112 let isLaneQ = 1; 1113} 1114def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>; 1115def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>; 1116 1117def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>; 1118def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi", 1119 OP_MLALHi_LN>; 1120def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi", 1121 OP_MLALHi_LN>; 1122def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>; 1123def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi", 1124 OP_MLSLHi_LN>; 1125def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi", 1126 OP_MLSLHi_LN>; 1127 1128def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>; 1129def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si", 1130 OP_QDMLALHi_LN>; 1131def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si", 1132 OP_QDMLALHi_LN>; 1133def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>; 1134def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si", 1135 OP_QDMLSLHi_LN>; 1136def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si", 1137 OP_QDMLSLHi_LN>; 1138 1139// Newly add double parameter for vmul_lane in aarch64 1140// Note: d type is handled by SCALAR_VMUL_LANE 1141def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>; 1142 1143// Note: d type is handled by SCALAR_VMUL_LANEQ 1144def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji", 1145 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>; 1146def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>; 1147def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi", 1148 OP_MULLHi_LN>; 1149def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi", 1150 OP_MULLHi_LN>; 1151 1152def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>; 1153def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si", 1154 OP_QDMULLHi_LN>; 1155def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si", 1156 OP_QDMULLHi_LN>; 1157 1158def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>; 1159def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>; 1160 1161// Note: d type implemented by SCALAR_VMULX_LANE 1162def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>; 1163// Note: d type is implemented by SCALAR_VMULX_LANEQ 1164def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>; 1165 1166//////////////////////////////////////////////////////////////////////////////// 1167// Across vectors class 1168def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">; 1169def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 1170def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 1171def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">; 1172def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">; 1173def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">; 1174 1175//////////////////////////////////////////////////////////////////////////////// 1176// Newly added Vector Extract for f64 1177def VEXT_A64 : WInst<"vext", "dddi", "dQdPlQPl">; 1178 1179//////////////////////////////////////////////////////////////////////////////// 1180// Crypto 1181let ArchGuard = "__ARM_FEATURE_CRYPTO" in { 1182def AESE : SInst<"vaese", "ddd", "QUc">; 1183def AESD : SInst<"vaesd", "ddd", "QUc">; 1184def AESMC : SInst<"vaesmc", "dd", "QUc">; 1185def AESIMC : SInst<"vaesimc", "dd", "QUc">; 1186 1187def SHA1H : SInst<"vsha1h", "ss", "Ui">; 1188def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">; 1189def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">; 1190 1191def SHA1C : SInst<"vsha1c", "ddsd", "QUi">; 1192def SHA1P : SInst<"vsha1p", "ddsd", "QUi">; 1193def SHA1M : SInst<"vsha1m", "ddsd", "QUi">; 1194def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">; 1195def SHA256H : SInst<"vsha256h", "dddd", "QUi">; 1196def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">; 1197def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">; 1198} 1199 1200//////////////////////////////////////////////////////////////////////////////// 1201// Float -> Int conversions with explicit rounding mode 1202 1203let ArchGuard = "__ARM_ARCH >= 8" in { 1204def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">; 1205def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">; 1206def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">; 1207def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">; 1208def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">; 1209def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">; 1210def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">; 1211def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">; 1212} 1213 1214let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in { 1215def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">; 1216def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">; 1217def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">; 1218def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">; 1219def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">; 1220def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">; 1221def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">; 1222def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">; 1223} 1224 1225//////////////////////////////////////////////////////////////////////////////// 1226// Permutation 1227def VTRN1 : SOpInst<"vtrn1", "ddd", 1228 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>; 1229def VZIP1 : SOpInst<"vzip1", "ddd", 1230 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>; 1231def VUZP1 : SOpInst<"vuzp1", "ddd", 1232 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>; 1233def VTRN2 : SOpInst<"vtrn2", "ddd", 1234 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>; 1235def VZIP2 : SOpInst<"vzip2", "ddd", 1236 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>; 1237def VUZP2 : SOpInst<"vuzp2", "ddd", 1238 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>; 1239 1240//////////////////////////////////////////////////////////////////////////////// 1241// Table lookup 1242let InstName = "vtbl" in { 1243def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">; 1244def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">; 1245def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">; 1246def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">; 1247} 1248let InstName = "vtbx" in { 1249def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">; 1250def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">; 1251def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">; 1252def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">; 1253} 1254 1255//////////////////////////////////////////////////////////////////////////////// 1256// Vector reinterpret cast operations 1257 1258// NeonEmitter implicitly takes the cartesian product of the type string with 1259// itself during generation so, unlike all other intrinsics, this one should 1260// include *all* types, not just additional ones. 1261def VVREINTERPRET 1262 : NoTestOpInst<"vreinterpret", "dd", 1263 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", OP_REINT> { 1264 let CartesianProductOfTypes = 1; 1265 let BigEndianSafe = 1; 1266 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)"; 1267} 1268 1269//////////////////////////////////////////////////////////////////////////////// 1270// Scalar Intrinsics 1271// Scalar Arithmetic 1272 1273// Scalar Addition 1274def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">; 1275// Scalar Saturating Add 1276def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1277 1278// Scalar Subtraction 1279def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">; 1280// Scalar Saturating Sub 1281def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1282 1283let InstName = "vmov" in { 1284def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "dPl", OP_HI>; 1285def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "dPl", OP_LO>; 1286} 1287 1288//////////////////////////////////////////////////////////////////////////////// 1289// Scalar Shift 1290// Scalar Shift Left 1291def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">; 1292// Scalar Saturating Shift Left 1293def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1294// Scalar Saturating Rounding Shift Left 1295def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1296// Scalar Shift Rouding Left 1297def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">; 1298 1299//////////////////////////////////////////////////////////////////////////////// 1300// Scalar Shift (Immediate) 1301let isScalarShift = 1 in { 1302// Signed/Unsigned Shift Right (Immediate) 1303def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">; 1304// Signed/Unsigned Rounding Shift Right (Immediate) 1305def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">; 1306 1307// Signed/Unsigned Shift Right and Accumulate (Immediate) 1308def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">; 1309// Signed/Unsigned Rounding Shift Right and Accumulate (Immediate) 1310def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">; 1311 1312// Shift Left (Immediate) 1313def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">; 1314// Signed/Unsigned Saturating Shift Left (Immediate) 1315def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">; 1316// Signed Saturating Shift Left Unsigned (Immediate) 1317def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">; 1318 1319// Shift Right And Insert (Immediate) 1320def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">; 1321// Shift Left And Insert (Immediate) 1322def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">; 1323 1324let isScalarNarrowShift = 1 in { 1325 // Signed/Unsigned Saturating Shift Right Narrow (Immediate) 1326 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1327 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) 1328 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1329 // Signed Saturating Shift Right Unsigned Narrow (Immediate) 1330 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">; 1331 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) 1332 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">; 1333} 1334 1335//////////////////////////////////////////////////////////////////////////////// 1336// Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) 1337def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">; 1338def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">; 1339 1340//////////////////////////////////////////////////////////////////////////////// 1341// Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) 1342def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">; 1343def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">; 1344def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">; 1345def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">; 1346} 1347 1348//////////////////////////////////////////////////////////////////////////////// 1349// Scalar Reduce Pairwise Addition (Scalar and Floating Point) 1350def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">; 1351 1352//////////////////////////////////////////////////////////////////////////////// 1353// Scalar Reduce Floating Point Pairwise Max/Min 1354def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">; 1355 1356def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">; 1357 1358//////////////////////////////////////////////////////////////////////////////// 1359// Scalar Reduce Floating Point Pairwise maxNum/minNum 1360def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">; 1361def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">; 1362 1363//////////////////////////////////////////////////////////////////////////////// 1364// Scalar Integer Saturating Doubling Multiply Half High 1365def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">; 1366 1367//////////////////////////////////////////////////////////////////////////////// 1368// Scalar Integer Saturating Rounding Doubling Multiply Half High 1369def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">; 1370 1371//////////////////////////////////////////////////////////////////////////////// 1372// Scalar Floating-point Multiply Extended 1373def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">; 1374 1375//////////////////////////////////////////////////////////////////////////////// 1376// Scalar Floating-point Reciprocal Step 1377def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">; 1378 1379//////////////////////////////////////////////////////////////////////////////// 1380// Scalar Floating-point Reciprocal Square Root Step 1381def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">; 1382 1383//////////////////////////////////////////////////////////////////////////////// 1384// Scalar Signed Integer Convert To Floating-point 1385def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">; 1386def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">; 1387 1388//////////////////////////////////////////////////////////////////////////////// 1389// Scalar Unsigned Integer Convert To Floating-point 1390def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">; 1391def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">; 1392 1393//////////////////////////////////////////////////////////////////////////////// 1394// Scalar Floating-point Converts 1395def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">; 1396def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">; 1397def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">; 1398def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">; 1399def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">; 1400def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">; 1401def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">; 1402def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">; 1403def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">; 1404def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">; 1405def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">; 1406def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">; 1407def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">; 1408def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">; 1409def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">; 1410def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">; 1411def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">; 1412def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">; 1413def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">; 1414def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">; 1415def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">; 1416 1417//////////////////////////////////////////////////////////////////////////////// 1418// Scalar Floating-point Reciprocal Estimate 1419def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">; 1420 1421//////////////////////////////////////////////////////////////////////////////// 1422// Scalar Floating-point Reciprocal Exponent 1423def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">; 1424 1425//////////////////////////////////////////////////////////////////////////////// 1426// Scalar Floating-point Reciprocal Square Root Estimate 1427def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">; 1428 1429//////////////////////////////////////////////////////////////////////////////// 1430// Scalar Integer Comparison 1431def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">; 1432def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">; 1433def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">; 1434def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">; 1435def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">; 1436def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">; 1437def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">; 1438def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">; 1439def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">; 1440def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">; 1441def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">; 1442def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">; 1443def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">; 1444 1445//////////////////////////////////////////////////////////////////////////////// 1446// Scalar Floating-point Comparison 1447def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">; 1448def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">; 1449def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">; 1450def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">; 1451def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">; 1452def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">; 1453def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">; 1454def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">; 1455def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">; 1456def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">; 1457 1458//////////////////////////////////////////////////////////////////////////////// 1459// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal 1460def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">; 1461def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">; 1462 1463//////////////////////////////////////////////////////////////////////////////// 1464// Scalar Floating-point Absolute Compare Mask Greater Than 1465def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">; 1466def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">; 1467 1468//////////////////////////////////////////////////////////////////////////////// 1469// Scalar Absolute Value 1470def SCALAR_ABS : SInst<"vabs", "ss", "Sl">; 1471 1472//////////////////////////////////////////////////////////////////////////////// 1473// Scalar Absolute Difference 1474def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">; 1475 1476//////////////////////////////////////////////////////////////////////////////// 1477// Scalar Signed Saturating Absolute Value 1478def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">; 1479 1480//////////////////////////////////////////////////////////////////////////////// 1481// Scalar Negate 1482def SCALAR_NEG : SInst<"vneg", "ss", "Sl">; 1483 1484//////////////////////////////////////////////////////////////////////////////// 1485// Scalar Signed Saturating Negate 1486def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">; 1487 1488//////////////////////////////////////////////////////////////////////////////// 1489// Scalar Signed Saturating Accumulated of Unsigned Value 1490def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">; 1491 1492//////////////////////////////////////////////////////////////////////////////// 1493// Scalar Unsigned Saturating Accumulated of Signed Value 1494def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">; 1495 1496//////////////////////////////////////////////////////////////////////////////// 1497// Signed Saturating Doubling Multiply-Add Long 1498def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">; 1499 1500//////////////////////////////////////////////////////////////////////////////// 1501// Signed Saturating Doubling Multiply-Subtract Long 1502def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">; 1503 1504//////////////////////////////////////////////////////////////////////////////// 1505// Signed Saturating Doubling Multiply Long 1506def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">; 1507 1508//////////////////////////////////////////////////////////////////////////////// 1509// Scalar Signed Saturating Extract Unsigned Narrow 1510def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">; 1511 1512//////////////////////////////////////////////////////////////////////////////// 1513// Scalar Signed Saturating Extract Narrow 1514def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">; 1515 1516//////////////////////////////////////////////////////////////////////////////// 1517// Scalar Unsigned Saturating Extract Narrow 1518def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">; 1519 1520// Scalar Floating Point multiply (scalar, by element) 1521def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>; 1522def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LN>; 1523 1524// Scalar Floating Point multiply extended (scalar, by element) 1525def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>; 1526def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LN>; 1527 1528def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">; 1529 1530// VMUL_LANE_A64 d type implemented using scalar mul lane 1531def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">; 1532 1533// VMUL_LANEQ d type implemented using scalar mul lane 1534def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d"> { 1535 let isLaneQ = 1; 1536} 1537 1538// VMULX_LANE d type implemented using scalar vmulx_lane 1539def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>; 1540 1541// VMULX_LANEQ d type implemented using scalar vmulx_laneq 1542def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>; 1543 1544// Scalar Floating Point fused multiply-add (scalar, by element) 1545def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">; 1546def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">; 1547 1548// Scalar Floating Point fused multiply-subtract (scalar, by element) 1549def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>; 1550def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>; 1551 1552// Signed Saturating Doubling Multiply Long (scalar by element) 1553def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>; 1554def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LN>; 1555 1556// Signed Saturating Doubling Multiply-Add Long (scalar by element) 1557def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">; 1558def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">; 1559 1560// Signed Saturating Doubling Multiply-Subtract Long (scalar by element) 1561def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">; 1562def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">; 1563 1564// Scalar Integer Saturating Doubling Multiply Half High (scalar by element) 1565def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>; 1566def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LN>; 1567 1568// Scalar Integer Saturating Rounding Doubling Multiply Half High 1569def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>; 1570def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LN>; 1571 1572def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1573def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1574 1575// FIXME: Rename so it is obvious this only applies to halfs. 1576def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "sdi", "h", OP_SCALAR_HALF_GET_LN>; 1577def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", "dsdi", "h", OP_SCALAR_HALF_SET_LN>; 1578def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "sdi", "Qh", OP_SCALAR_HALF_GET_LNQ>; 1579def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", "dsdi", "Qh", OP_SCALAR_HALF_SET_LNQ>; 1580} 1581