Targets.cpp revision 5ccd3d0214b9d765a1bb41872da27d3c5530ab2b 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387        case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393        case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus11) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593template <typename Target>
594class NaClTargetInfo : public OSTargetInfo<Target> {
595 protected:
596  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                            MacroBuilder &Builder) const {
598    if (Opts.POSIXThreads)
599      Builder.defineMacro("_REENTRANT");
600    if (Opts.CPlusPlus)
601      Builder.defineMacro("_GNU_SOURCE");
602
603    DefineStd(Builder, "unix", Opts);
604    Builder.defineMacro("__ELF__");
605    Builder.defineMacro("__native_client__");
606  }
607 public:
608  NaClTargetInfo(const std::string &triple)
609    : OSTargetInfo<Target>(triple) {
610    this->UserLabelPrefix = "";
611    this->LongAlign = 32;
612    this->LongWidth = 32;
613    this->PointerAlign = 32;
614    this->PointerWidth = 32;
615    this->IntMaxType = TargetInfo::SignedLongLong;
616    this->UIntMaxType = TargetInfo::UnsignedLongLong;
617    this->Int64Type = TargetInfo::SignedLongLong;
618    this->DoubleAlign = 64;
619    this->LongDoubleWidth = 64;
620    this->LongDoubleAlign = 64;
621    this->SizeType = TargetInfo::UnsignedInt;
622    this->PtrDiffType = TargetInfo::SignedInt;
623    this->IntPtrType = TargetInfo::SignedInt;
624    this->RegParmMax = 2;
625    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628  }
629  virtual typename Target::CallingConvCheckResult checkCallingConvention(
630      CallingConv CC) const {
631    return CC == CC_PnaclCall ? Target::CCCR_OK :
632        Target::checkCallingConvention(CC);
633  }
634};
635} // end anonymous namespace.
636
637//===----------------------------------------------------------------------===//
638// Specific target implementations.
639//===----------------------------------------------------------------------===//
640
641namespace {
642// PPC abstract base class
643class PPCTargetInfo : public TargetInfo {
644  static const Builtin::Info BuiltinInfo[];
645  static const char * const GCCRegNames[];
646  static const TargetInfo::GCCRegAlias GCCRegAliases[];
647  std::string CPU;
648public:
649  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650    LongDoubleWidth = LongDoubleAlign = 128;
651    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652  }
653
654  /// \brief Flags for architecture specific defines.
655  typedef enum {
656    ArchDefineNone  = 0,
657    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658    ArchDefinePpcgr = 1 << 1,
659    ArchDefinePpcsq = 1 << 2,
660    ArchDefine440   = 1 << 3,
661    ArchDefine603   = 1 << 4,
662    ArchDefine604   = 1 << 5,
663    ArchDefinePwr4  = 1 << 6,
664    ArchDefinePwr6  = 1 << 7,
665    ArchDefineA2    = 1 << 8,
666    ArchDefineA2q   = 1 << 9
667  } ArchDefineTypes;
668
669  virtual bool setCPU(const std::string &Name) {
670    bool CPUKnown = llvm::StringSwitch<bool>(Name)
671      .Case("generic", true)
672      .Case("440", true)
673      .Case("450", true)
674      .Case("601", true)
675      .Case("602", true)
676      .Case("603", true)
677      .Case("603e", true)
678      .Case("603ev", true)
679      .Case("604", true)
680      .Case("604e", true)
681      .Case("620", true)
682      .Case("g3", true)
683      .Case("7400", true)
684      .Case("g4", true)
685      .Case("7450", true)
686      .Case("g4+", true)
687      .Case("750", true)
688      .Case("970", true)
689      .Case("g5", true)
690      .Case("a2", true)
691      .Case("a2q", true)
692      .Case("e500mc", true)
693      .Case("e5500", true)
694      .Case("pwr6", true)
695      .Case("pwr7", true)
696      .Case("ppc", true)
697      .Case("ppc64", true)
698      .Default(false);
699
700    if (CPUKnown)
701      CPU = Name;
702
703    return CPUKnown;
704  }
705
706  virtual void getTargetBuiltins(const Builtin::Info *&Records,
707                                 unsigned &NumRecords) const {
708    Records = BuiltinInfo;
709    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
710  }
711
712  virtual bool isCLZForZeroUndef() const { return false; }
713
714  virtual void getTargetDefines(const LangOptions &Opts,
715                                MacroBuilder &Builder) const;
716
717  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
718
719  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
720                                 StringRef Name,
721                                 bool Enabled) const;
722
723  virtual bool hasFeature(StringRef Feature) const;
724
725  virtual void getGCCRegNames(const char * const *&Names,
726                              unsigned &NumNames) const;
727  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
728                                unsigned &NumAliases) const;
729  virtual bool validateAsmConstraint(const char *&Name,
730                                     TargetInfo::ConstraintInfo &Info) const {
731    switch (*Name) {
732    default: return false;
733    case 'O': // Zero
734      break;
735    case 'b': // Base register
736    case 'f': // Floating point register
737      Info.setAllowsRegister();
738      break;
739    // FIXME: The following are added to allow parsing.
740    // I just took a guess at what the actions should be.
741    // Also, is more specific checking needed?  I.e. specific registers?
742    case 'd': // Floating point register (containing 64-bit value)
743    case 'v': // Altivec vector register
744      Info.setAllowsRegister();
745      break;
746    case 'w':
747      switch (Name[1]) {
748        case 'd':// VSX vector register to hold vector double data
749        case 'f':// VSX vector register to hold vector float data
750        case 's':// VSX vector register to hold scalar float data
751        case 'a':// Any VSX register
752          break;
753        default:
754          return false;
755      }
756      Info.setAllowsRegister();
757      Name++; // Skip over 'w'.
758      break;
759    case 'h': // `MQ', `CTR', or `LINK' register
760    case 'q': // `MQ' register
761    case 'c': // `CTR' register
762    case 'l': // `LINK' register
763    case 'x': // `CR' register (condition register) number 0
764    case 'y': // `CR' register (condition register)
765    case 'z': // `XER[CA]' carry bit (part of the XER register)
766      Info.setAllowsRegister();
767      break;
768    case 'I': // Signed 16-bit constant
769    case 'J': // Unsigned 16-bit constant shifted left 16 bits
770              //  (use `L' instead for SImode constants)
771    case 'K': // Unsigned 16-bit constant
772    case 'L': // Signed 16-bit constant shifted left 16 bits
773    case 'M': // Constant larger than 31
774    case 'N': // Exact power of 2
775    case 'P': // Constant whose negation is a signed 16-bit constant
776    case 'G': // Floating point constant that can be loaded into a
777              // register with one instruction per word
778    case 'H': // Integer/Floating point constant that can be loaded
779              // into a register using three instructions
780      break;
781    case 'm': // Memory operand. Note that on PowerPC targets, m can
782              // include addresses that update the base register. It
783              // is therefore only safe to use `m' in an asm statement
784              // if that asm statement accesses the operand exactly once.
785              // The asm statement must also use `%U<opno>' as a
786              // placeholder for the "update" flag in the corresponding
787              // load or store instruction. For example:
788              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
789              // is correct but:
790              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
791              // is not. Use es rather than m if you don't want the base
792              // register to be updated.
793    case 'e':
794      if (Name[1] != 's')
795          return false;
796              // es: A "stable" memory operand; that is, one which does not
797              // include any automodification of the base register. Unlike
798              // `m', this constraint can be used in asm statements that
799              // might access the operand several times, or that might not
800              // access it at all.
801      Info.setAllowsMemory();
802      Name++; // Skip over 'e'.
803      break;
804    case 'Q': // Memory operand that is an offset from a register (it is
805              // usually better to use `m' or `es' in asm statements)
806    case 'Z': // Memory operand that is an indexed or indirect from a
807              // register (it is usually better to use `m' or `es' in
808              // asm statements)
809      Info.setAllowsMemory();
810      Info.setAllowsRegister();
811      break;
812    case 'R': // AIX TOC entry
813    case 'a': // Address operand that is an indexed or indirect from a
814              // register (`p' is preferable for asm statements)
815    case 'S': // Constant suitable as a 64-bit mask operand
816    case 'T': // Constant suitable as a 32-bit mask operand
817    case 'U': // System V Release 4 small data area reference
818    case 't': // AND masks that can be performed by two rldic{l, r}
819              // instructions
820    case 'W': // Vector constant that does not require memory
821    case 'j': // Vector constant that is all zeros.
822      break;
823    // End FIXME.
824    }
825    return true;
826  }
827  virtual const char *getClobbers() const {
828    return "";
829  }
830  int getEHDataRegisterNumber(unsigned RegNo) const {
831    if (RegNo == 0) return 3;
832    if (RegNo == 1) return 4;
833    return -1;
834  }
835};
836
837const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
838#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
839#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
840                                              ALL_LANGUAGES },
841#include "clang/Basic/BuiltinsPPC.def"
842};
843
844
845/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
846/// #defines that are not tied to a specific subtarget.
847void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
848                                     MacroBuilder &Builder) const {
849  // Target identification.
850  Builder.defineMacro("__ppc__");
851  Builder.defineMacro("_ARCH_PPC");
852  Builder.defineMacro("__powerpc__");
853  Builder.defineMacro("__POWERPC__");
854  if (PointerWidth == 64) {
855    Builder.defineMacro("_ARCH_PPC64");
856    Builder.defineMacro("__powerpc64__");
857    Builder.defineMacro("__ppc64__");
858  } else {
859    Builder.defineMacro("__ppc__");
860  }
861
862  // Target properties.
863  if (getTriple().getOS() != llvm::Triple::NetBSD &&
864      getTriple().getOS() != llvm::Triple::OpenBSD)
865    Builder.defineMacro("_BIG_ENDIAN");
866  Builder.defineMacro("__BIG_ENDIAN__");
867
868  // Subtarget options.
869  Builder.defineMacro("__NATURAL_ALIGNMENT__");
870  Builder.defineMacro("__REGISTER_PREFIX__", "");
871
872  // FIXME: Should be controlled by command line option.
873  Builder.defineMacro("__LONG_DOUBLE_128__");
874
875  if (Opts.AltiVec) {
876    Builder.defineMacro("__VEC__", "10206");
877    Builder.defineMacro("__ALTIVEC__");
878  }
879
880  // CPU identification.
881  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
882    .Case("440",   ArchDefineName)
883    .Case("450",   ArchDefineName | ArchDefine440)
884    .Case("601",   ArchDefineName)
885    .Case("602",   ArchDefineName | ArchDefinePpcgr)
886    .Case("603",   ArchDefineName | ArchDefinePpcgr)
887    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
888    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
889    .Case("604",   ArchDefineName | ArchDefinePpcgr)
890    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
891    .Case("620",   ArchDefineName | ArchDefinePpcgr)
892    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
893    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
894    .Case("750",   ArchDefineName | ArchDefinePpcgr)
895    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
896                     | ArchDefinePpcsq)
897    .Case("pwr6",  ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
898    .Case("pwr7",  ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr
899                     | ArchDefinePpcsq)
900    .Case("a2",    ArchDefineA2)
901    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
902    .Default(ArchDefineNone);
903
904  if (defs & ArchDefineName)
905    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
906  if (defs & ArchDefinePpcgr)
907    Builder.defineMacro("_ARCH_PPCGR");
908  if (defs & ArchDefinePpcsq)
909    Builder.defineMacro("_ARCH_PPCSQ");
910  if (defs & ArchDefine440)
911    Builder.defineMacro("_ARCH_440");
912  if (defs & ArchDefine603)
913    Builder.defineMacro("_ARCH_603");
914  if (defs & ArchDefine604)
915    Builder.defineMacro("_ARCH_604");
916  if (defs & (ArchDefinePwr4 | ArchDefinePwr6))
917    Builder.defineMacro("_ARCH_PWR4");
918  if (defs & ArchDefinePwr6) {
919    Builder.defineMacro("_ARCH_PWR5");
920    Builder.defineMacro("_ARCH_PWR6");
921  }
922  if (defs & ArchDefineA2)
923    Builder.defineMacro("_ARCH_A2");
924  if (defs & ArchDefineA2q) {
925    Builder.defineMacro("_ARCH_A2Q");
926    Builder.defineMacro("_ARCH_QP");
927  }
928
929  if (getTriple().getVendor() == llvm::Triple::BGQ) {
930    Builder.defineMacro("__bg__");
931    Builder.defineMacro("__THW_BLUEGENE__");
932    Builder.defineMacro("__bgq__");
933    Builder.defineMacro("__TOS_BGQ__");
934  }
935}
936
937void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
938  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
939    .Case("7400", true)
940    .Case("g4", true)
941    .Case("7450", true)
942    .Case("g4+", true)
943    .Case("970", true)
944    .Case("g5", true)
945    .Case("pwr6", true)
946    .Case("pwr7", true)
947    .Case("ppc64", true)
948    .Default(false);
949}
950
951bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
952                                         StringRef Name,
953                                         bool Enabled) const {
954  if (Name == "altivec") {
955    Features[Name] = Enabled;
956    return true;
957  }
958
959  return false;
960}
961
962bool PPCTargetInfo::hasFeature(StringRef Feature) const {
963  return Feature == "powerpc";
964}
965
966
967const char * const PPCTargetInfo::GCCRegNames[] = {
968  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
969  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
970  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
971  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
972  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
973  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
974  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
975  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
976  "mq", "lr", "ctr", "ap",
977  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
978  "xer",
979  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
980  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
981  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
982  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
983  "vrsave", "vscr",
984  "spe_acc", "spefscr",
985  "sfp"
986};
987
988void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
989                                   unsigned &NumNames) const {
990  Names = GCCRegNames;
991  NumNames = llvm::array_lengthof(GCCRegNames);
992}
993
994const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
995  // While some of these aliases do map to different registers
996  // they still share the same register name.
997  { { "0" }, "r0" },
998  { { "1"}, "r1" },
999  { { "2" }, "r2" },
1000  { { "3" }, "r3" },
1001  { { "4" }, "r4" },
1002  { { "5" }, "r5" },
1003  { { "6" }, "r6" },
1004  { { "7" }, "r7" },
1005  { { "8" }, "r8" },
1006  { { "9" }, "r9" },
1007  { { "10" }, "r10" },
1008  { { "11" }, "r11" },
1009  { { "12" }, "r12" },
1010  { { "13" }, "r13" },
1011  { { "14" }, "r14" },
1012  { { "15" }, "r15" },
1013  { { "16" }, "r16" },
1014  { { "17" }, "r17" },
1015  { { "18" }, "r18" },
1016  { { "19" }, "r19" },
1017  { { "20" }, "r20" },
1018  { { "21" }, "r21" },
1019  { { "22" }, "r22" },
1020  { { "23" }, "r23" },
1021  { { "24" }, "r24" },
1022  { { "25" }, "r25" },
1023  { { "26" }, "r26" },
1024  { { "27" }, "r27" },
1025  { { "28" }, "r28" },
1026  { { "29" }, "r29" },
1027  { { "30" }, "r30" },
1028  { { "31" }, "r31" },
1029  { { "fr0" }, "f0" },
1030  { { "fr1" }, "f1" },
1031  { { "fr2" }, "f2" },
1032  { { "fr3" }, "f3" },
1033  { { "fr4" }, "f4" },
1034  { { "fr5" }, "f5" },
1035  { { "fr6" }, "f6" },
1036  { { "fr7" }, "f7" },
1037  { { "fr8" }, "f8" },
1038  { { "fr9" }, "f9" },
1039  { { "fr10" }, "f10" },
1040  { { "fr11" }, "f11" },
1041  { { "fr12" }, "f12" },
1042  { { "fr13" }, "f13" },
1043  { { "fr14" }, "f14" },
1044  { { "fr15" }, "f15" },
1045  { { "fr16" }, "f16" },
1046  { { "fr17" }, "f17" },
1047  { { "fr18" }, "f18" },
1048  { { "fr19" }, "f19" },
1049  { { "fr20" }, "f20" },
1050  { { "fr21" }, "f21" },
1051  { { "fr22" }, "f22" },
1052  { { "fr23" }, "f23" },
1053  { { "fr24" }, "f24" },
1054  { { "fr25" }, "f25" },
1055  { { "fr26" }, "f26" },
1056  { { "fr27" }, "f27" },
1057  { { "fr28" }, "f28" },
1058  { { "fr29" }, "f29" },
1059  { { "fr30" }, "f30" },
1060  { { "fr31" }, "f31" },
1061  { { "cc" }, "cr0" },
1062};
1063
1064void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1065                                     unsigned &NumAliases) const {
1066  Aliases = GCCRegAliases;
1067  NumAliases = llvm::array_lengthof(GCCRegAliases);
1068}
1069} // end anonymous namespace.
1070
1071namespace {
1072class PPC32TargetInfo : public PPCTargetInfo {
1073public:
1074  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1075    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1076                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1077
1078    switch (getTriple().getOS()) {
1079    case llvm::Triple::Linux:
1080    case llvm::Triple::FreeBSD:
1081    case llvm::Triple::NetBSD:
1082      SizeType = UnsignedInt;
1083      PtrDiffType = SignedInt;
1084      IntPtrType = SignedInt;
1085      break;
1086    default:
1087      break;
1088    }
1089
1090    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1091      LongDoubleWidth = LongDoubleAlign = 64;
1092      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1093    }
1094
1095    // PPC32 supports atomics up to 4 bytes.
1096    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1097  }
1098
1099  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1100    // This is the ELF definition, and is overridden by the Darwin sub-target
1101    return TargetInfo::PowerABIBuiltinVaList;
1102  }
1103};
1104} // end anonymous namespace.
1105
1106namespace {
1107class PPC64TargetInfo : public PPCTargetInfo {
1108public:
1109  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1110    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1111    IntMaxType = SignedLong;
1112    UIntMaxType = UnsignedLong;
1113    Int64Type = SignedLong;
1114
1115    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1116      LongDoubleWidth = LongDoubleAlign = 64;
1117      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1118      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1119                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1120                          "v128:128:128-n32:64";
1121    } else
1122      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1123                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1124                          "v128:128:128-n32:64";
1125
1126    // PPC64 supports atomics up to 8 bytes.
1127    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1128  }
1129  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1130    return TargetInfo::CharPtrBuiltinVaList;
1131  }
1132};
1133} // end anonymous namespace.
1134
1135
1136namespace {
1137class DarwinPPC32TargetInfo :
1138  public DarwinTargetInfo<PPC32TargetInfo> {
1139public:
1140  DarwinPPC32TargetInfo(const std::string& triple)
1141    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1142    HasAlignMac68kSupport = true;
1143    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1144    LongLongAlign = 32;
1145    SuitableAlign = 128;
1146    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1147                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1148  }
1149  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1150    return TargetInfo::CharPtrBuiltinVaList;
1151  }
1152};
1153
1154class DarwinPPC64TargetInfo :
1155  public DarwinTargetInfo<PPC64TargetInfo> {
1156public:
1157  DarwinPPC64TargetInfo(const std::string& triple)
1158    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1159    HasAlignMac68kSupport = true;
1160    SuitableAlign = 128;
1161    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1162                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1163  }
1164};
1165} // end anonymous namespace.
1166
1167namespace {
1168  static const unsigned NVPTXAddrSpaceMap[] = {
1169    1,    // opencl_global
1170    3,    // opencl_local
1171    4,    // opencl_constant
1172    1,    // cuda_device
1173    4,    // cuda_constant
1174    3,    // cuda_shared
1175  };
1176  class NVPTXTargetInfo : public TargetInfo {
1177    static const char * const GCCRegNames[];
1178    static const Builtin::Info BuiltinInfo[];
1179    std::vector<StringRef> AvailableFeatures;
1180  public:
1181    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1182      BigEndian = false;
1183      TLSSupported = false;
1184      LongWidth = LongAlign = 64;
1185      AddrSpaceMap = &NVPTXAddrSpaceMap;
1186      // Define available target features
1187      // These must be defined in sorted order!
1188      NoAsmVariants = true;
1189    }
1190    virtual void getTargetDefines(const LangOptions &Opts,
1191                                  MacroBuilder &Builder) const {
1192      Builder.defineMacro("__PTX__");
1193      Builder.defineMacro("__NVPTX__");
1194    }
1195    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1196                                   unsigned &NumRecords) const {
1197      Records = BuiltinInfo;
1198      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1199    }
1200    virtual bool hasFeature(StringRef Feature) const {
1201      return Feature == "ptx" || Feature == "nvptx";
1202    }
1203
1204    virtual void getGCCRegNames(const char * const *&Names,
1205                                unsigned &NumNames) const;
1206    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1207                                  unsigned &NumAliases) const {
1208      // No aliases.
1209      Aliases = 0;
1210      NumAliases = 0;
1211    }
1212    virtual bool validateAsmConstraint(const char *&Name,
1213                                       TargetInfo::ConstraintInfo &info) const {
1214      // FIXME: implement
1215      return true;
1216    }
1217    virtual const char *getClobbers() const {
1218      // FIXME: Is this really right?
1219      return "";
1220    }
1221    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1222      // FIXME: implement
1223      return TargetInfo::CharPtrBuiltinVaList;
1224    }
1225    virtual bool setCPU(const std::string &Name) {
1226      return Name == "sm_10" || Name == "sm_13" || Name == "sm_20";
1227    }
1228    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1229                                   StringRef Name,
1230                                   bool Enabled) const;
1231  };
1232
1233  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1234#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1235#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1236                                              ALL_LANGUAGES },
1237#include "clang/Basic/BuiltinsNVPTX.def"
1238  };
1239
1240  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1241    "r0"
1242  };
1243
1244  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1245                                     unsigned &NumNames) const {
1246    Names = GCCRegNames;
1247    NumNames = llvm::array_lengthof(GCCRegNames);
1248  }
1249
1250  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1251                                          StringRef Name,
1252                                          bool Enabled) const {
1253    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1254                          Name)) {
1255      Features[Name] = Enabled;
1256      return true;
1257    } else {
1258      return false;
1259    }
1260  }
1261
1262  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1263  public:
1264    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1265      PointerWidth = PointerAlign = 32;
1266      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1267      DescriptionString
1268        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1269          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1270          "n16:32:64";
1271  }
1272  };
1273
1274  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1275  public:
1276    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1277      PointerWidth = PointerAlign = 64;
1278      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1279      DescriptionString
1280        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1281          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1282          "n16:32:64";
1283  }
1284  };
1285}
1286
1287namespace {
1288
1289static const unsigned R600AddrSpaceMap[] = {
1290  1,    // opencl_global
1291  3,    // opencl_local
1292  2,    // opencl_constant
1293  1,    // cuda_device
1294  2,    // cuda_constant
1295  3     // cuda_shared
1296};
1297
1298class R600TargetInfo : public TargetInfo {
1299public:
1300  R600TargetInfo(const std::string& triple) : TargetInfo(triple) {
1301    DescriptionString =
1302          "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16"
1303          "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32"
1304          "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64"
1305          "-v96:128:128-v128:128:128-v192:256:256-v256:256:256"
1306          "-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1307          "-n8:16:32:64";
1308    AddrSpaceMap = &R600AddrSpaceMap;
1309  }
1310
1311  virtual const char * getClobbers() const {
1312    return "";
1313  }
1314
1315  virtual void getGCCRegNames(const char * const *&Names,
1316                              unsigned &numNames) const  {
1317    Names = NULL;
1318    numNames = 0;
1319  }
1320
1321  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1322                                unsigned &NumAliases) const {
1323    Aliases = NULL;
1324    NumAliases = 0;
1325  }
1326
1327  virtual bool validateAsmConstraint(const char *&Name,
1328                                     TargetInfo::ConstraintInfo &info) const {
1329    return true;
1330  }
1331
1332  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1333                                 unsigned &NumRecords) const {
1334    Records = NULL;
1335    NumRecords = 0;
1336  }
1337
1338
1339  virtual void getTargetDefines(const LangOptions &Opts,
1340                                MacroBuilder &Builder) const {
1341    Builder.defineMacro("__R600__");
1342  }
1343
1344  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1345    return TargetInfo::CharPtrBuiltinVaList;
1346  }
1347
1348};
1349
1350} // end anonymous namespace
1351
1352namespace {
1353// MBlaze abstract base class
1354class MBlazeTargetInfo : public TargetInfo {
1355  static const char * const GCCRegNames[];
1356  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1357
1358public:
1359  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1360    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1361  }
1362
1363  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1364                                 unsigned &NumRecords) const {
1365    // FIXME: Implement.
1366    Records = 0;
1367    NumRecords = 0;
1368  }
1369
1370  virtual void getTargetDefines(const LangOptions &Opts,
1371                                MacroBuilder &Builder) const;
1372
1373  virtual bool hasFeature(StringRef Feature) const {
1374    return Feature == "mblaze";
1375  }
1376
1377  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1378    return TargetInfo::CharPtrBuiltinVaList;
1379  }
1380  virtual const char *getTargetPrefix() const {
1381    return "mblaze";
1382  }
1383  virtual void getGCCRegNames(const char * const *&Names,
1384                              unsigned &NumNames) const;
1385  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1386                                unsigned &NumAliases) const;
1387  virtual bool validateAsmConstraint(const char *&Name,
1388                                     TargetInfo::ConstraintInfo &Info) const {
1389    switch (*Name) {
1390    default: return false;
1391    case 'O': // Zero
1392      return true;
1393    case 'b': // Base register
1394    case 'f': // Floating point register
1395      Info.setAllowsRegister();
1396      return true;
1397    }
1398  }
1399  virtual const char *getClobbers() const {
1400    return "";
1401  }
1402};
1403
1404/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1405/// #defines that are not tied to a specific subtarget.
1406void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1407                                     MacroBuilder &Builder) const {
1408  // Target identification.
1409  Builder.defineMacro("__microblaze__");
1410  Builder.defineMacro("_ARCH_MICROBLAZE");
1411  Builder.defineMacro("__MICROBLAZE__");
1412
1413  // Target properties.
1414  Builder.defineMacro("_BIG_ENDIAN");
1415  Builder.defineMacro("__BIG_ENDIAN__");
1416
1417  // Subtarget options.
1418  Builder.defineMacro("__REGISTER_PREFIX__", "");
1419}
1420
1421
1422const char * const MBlazeTargetInfo::GCCRegNames[] = {
1423  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1424  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1425  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1426  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1427  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1428  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1429  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1430  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1431  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1432  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1433};
1434
1435void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1436                                   unsigned &NumNames) const {
1437  Names = GCCRegNames;
1438  NumNames = llvm::array_lengthof(GCCRegNames);
1439}
1440
1441const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1442  { {"f0"},  "r0" },
1443  { {"f1"},  "r1" },
1444  { {"f2"},  "r2" },
1445  { {"f3"},  "r3" },
1446  { {"f4"},  "r4" },
1447  { {"f5"},  "r5" },
1448  { {"f6"},  "r6" },
1449  { {"f7"},  "r7" },
1450  { {"f8"},  "r8" },
1451  { {"f9"},  "r9" },
1452  { {"f10"}, "r10" },
1453  { {"f11"}, "r11" },
1454  { {"f12"}, "r12" },
1455  { {"f13"}, "r13" },
1456  { {"f14"}, "r14" },
1457  { {"f15"}, "r15" },
1458  { {"f16"}, "r16" },
1459  { {"f17"}, "r17" },
1460  { {"f18"}, "r18" },
1461  { {"f19"}, "r19" },
1462  { {"f20"}, "r20" },
1463  { {"f21"}, "r21" },
1464  { {"f22"}, "r22" },
1465  { {"f23"}, "r23" },
1466  { {"f24"}, "r24" },
1467  { {"f25"}, "r25" },
1468  { {"f26"}, "r26" },
1469  { {"f27"}, "r27" },
1470  { {"f28"}, "r28" },
1471  { {"f29"}, "r29" },
1472  { {"f30"}, "r30" },
1473  { {"f31"}, "r31" },
1474};
1475
1476void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1477                                     unsigned &NumAliases) const {
1478  Aliases = GCCRegAliases;
1479  NumAliases = llvm::array_lengthof(GCCRegAliases);
1480}
1481} // end anonymous namespace.
1482
1483namespace {
1484// Namespace for x86 abstract base class
1485const Builtin::Info BuiltinInfo[] = {
1486#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1487#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1488                                              ALL_LANGUAGES },
1489#include "clang/Basic/BuiltinsX86.def"
1490};
1491
1492static const char* const GCCRegNames[] = {
1493  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1494  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1495  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1496  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1497  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1498  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1499  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1500  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1501  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1502};
1503
1504const TargetInfo::AddlRegName AddlRegNames[] = {
1505  { { "al", "ah", "eax", "rax" }, 0 },
1506  { { "bl", "bh", "ebx", "rbx" }, 3 },
1507  { { "cl", "ch", "ecx", "rcx" }, 2 },
1508  { { "dl", "dh", "edx", "rdx" }, 1 },
1509  { { "esi", "rsi" }, 4 },
1510  { { "edi", "rdi" }, 5 },
1511  { { "esp", "rsp" }, 7 },
1512  { { "ebp", "rbp" }, 6 },
1513};
1514
1515// X86 target abstract base class; x86-32 and x86-64 are very close, so
1516// most of the implementation can be shared.
1517class X86TargetInfo : public TargetInfo {
1518  enum X86SSEEnum {
1519    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1520  } SSELevel;
1521  enum MMX3DNowEnum {
1522    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1523  } MMX3DNowLevel;
1524
1525  bool HasAES;
1526  bool HasPCLMUL;
1527  bool HasLZCNT;
1528  bool HasRDRND;
1529  bool HasBMI;
1530  bool HasBMI2;
1531  bool HasPOPCNT;
1532  bool HasRTM;
1533  bool HasSSE4a;
1534  bool HasFMA4;
1535  bool HasFMA;
1536  bool HasXOP;
1537  bool HasF16C;
1538
1539  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1540  ///
1541  /// Each enumeration represents a particular CPU supported by Clang. These
1542  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1543  enum CPUKind {
1544    CK_Generic,
1545
1546    /// \name i386
1547    /// i386-generation processors.
1548    //@{
1549    CK_i386,
1550    //@}
1551
1552    /// \name i486
1553    /// i486-generation processors.
1554    //@{
1555    CK_i486,
1556    CK_WinChipC6,
1557    CK_WinChip2,
1558    CK_C3,
1559    //@}
1560
1561    /// \name i586
1562    /// i586-generation processors, P5 microarchitecture based.
1563    //@{
1564    CK_i586,
1565    CK_Pentium,
1566    CK_PentiumMMX,
1567    //@}
1568
1569    /// \name i686
1570    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1571    //@{
1572    CK_i686,
1573    CK_PentiumPro,
1574    CK_Pentium2,
1575    CK_Pentium3,
1576    CK_Pentium3M,
1577    CK_PentiumM,
1578    CK_C3_2,
1579
1580    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1581    /// Clang however has some logic to suport this.
1582    // FIXME: Warn, deprecate, and potentially remove this.
1583    CK_Yonah,
1584    //@}
1585
1586    /// \name Netburst
1587    /// Netburst microarchitecture based processors.
1588    //@{
1589    CK_Pentium4,
1590    CK_Pentium4M,
1591    CK_Prescott,
1592    CK_Nocona,
1593    //@}
1594
1595    /// \name Core
1596    /// Core microarchitecture based processors.
1597    //@{
1598    CK_Core2,
1599
1600    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1601    /// codename which GCC no longer accepts as an option to -march, but Clang
1602    /// has some logic for recognizing it.
1603    // FIXME: Warn, deprecate, and potentially remove this.
1604    CK_Penryn,
1605    //@}
1606
1607    /// \name Atom
1608    /// Atom processors
1609    //@{
1610    CK_Atom,
1611    //@}
1612
1613    /// \name Nehalem
1614    /// Nehalem microarchitecture based processors.
1615    //@{
1616    CK_Corei7,
1617    CK_Corei7AVX,
1618    CK_CoreAVXi,
1619    CK_CoreAVX2,
1620    //@}
1621
1622    /// \name K6
1623    /// K6 architecture processors.
1624    //@{
1625    CK_K6,
1626    CK_K6_2,
1627    CK_K6_3,
1628    //@}
1629
1630    /// \name K7
1631    /// K7 architecture processors.
1632    //@{
1633    CK_Athlon,
1634    CK_AthlonThunderbird,
1635    CK_Athlon4,
1636    CK_AthlonXP,
1637    CK_AthlonMP,
1638    //@}
1639
1640    /// \name K8
1641    /// K8 architecture processors.
1642    //@{
1643    CK_Athlon64,
1644    CK_Athlon64SSE3,
1645    CK_AthlonFX,
1646    CK_K8,
1647    CK_K8SSE3,
1648    CK_Opteron,
1649    CK_OpteronSSE3,
1650    CK_AMDFAM10,
1651    //@}
1652
1653    /// \name Bobcat
1654    /// Bobcat architecture processors.
1655    //@{
1656    CK_BTVER1,
1657    //@}
1658
1659    /// \name Bulldozer
1660    /// Bulldozer architecture processors.
1661    //@{
1662    CK_BDVER1,
1663    CK_BDVER2,
1664    //@}
1665
1666    /// This specification is deprecated and will be removed in the future.
1667    /// Users should prefer \see CK_K8.
1668    // FIXME: Warn on this when the CPU is set to it.
1669    CK_x86_64,
1670    //@}
1671
1672    /// \name Geode
1673    /// Geode processors.
1674    //@{
1675    CK_Geode
1676    //@}
1677  } CPU;
1678
1679public:
1680  X86TargetInfo(const std::string& triple)
1681    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1682      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1683      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1684      HasSSE4a(false), HasFMA4(false), HasFMA(false), HasXOP(false),
1685      HasF16C(false), CPU(CK_Generic) {
1686    BigEndian = false;
1687    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1688  }
1689  virtual unsigned getFloatEvalMethod() const {
1690    // X87 evaluates with 80 bits "long double" precision.
1691    return SSELevel == NoSSE ? 2 : 0;
1692  }
1693  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1694                                 unsigned &NumRecords) const {
1695    Records = BuiltinInfo;
1696    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1697  }
1698  virtual void getGCCRegNames(const char * const *&Names,
1699                              unsigned &NumNames) const {
1700    Names = GCCRegNames;
1701    NumNames = llvm::array_lengthof(GCCRegNames);
1702  }
1703  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1704                                unsigned &NumAliases) const {
1705    Aliases = 0;
1706    NumAliases = 0;
1707  }
1708  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1709                                  unsigned &NumNames) const {
1710    Names = AddlRegNames;
1711    NumNames = llvm::array_lengthof(AddlRegNames);
1712  }
1713  virtual bool validateAsmConstraint(const char *&Name,
1714                                     TargetInfo::ConstraintInfo &info) const;
1715  virtual std::string convertConstraint(const char *&Constraint) const;
1716  virtual const char *getClobbers() const {
1717    return "~{dirflag},~{fpsr},~{flags}";
1718  }
1719  virtual void getTargetDefines(const LangOptions &Opts,
1720                                MacroBuilder &Builder) const;
1721  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1722                                 StringRef Name,
1723                                 bool Enabled) const;
1724  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1725  virtual bool hasFeature(StringRef Feature) const;
1726  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1727  virtual const char* getABI() const {
1728    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1729      return "avx";
1730    else if (getTriple().getArch() == llvm::Triple::x86 &&
1731             MMX3DNowLevel == NoMMX3DNow)
1732      return "no-mmx";
1733    return "";
1734  }
1735  virtual bool setCPU(const std::string &Name) {
1736    CPU = llvm::StringSwitch<CPUKind>(Name)
1737      .Case("i386", CK_i386)
1738      .Case("i486", CK_i486)
1739      .Case("winchip-c6", CK_WinChipC6)
1740      .Case("winchip2", CK_WinChip2)
1741      .Case("c3", CK_C3)
1742      .Case("i586", CK_i586)
1743      .Case("pentium", CK_Pentium)
1744      .Case("pentium-mmx", CK_PentiumMMX)
1745      .Case("i686", CK_i686)
1746      .Case("pentiumpro", CK_PentiumPro)
1747      .Case("pentium2", CK_Pentium2)
1748      .Case("pentium3", CK_Pentium3)
1749      .Case("pentium3m", CK_Pentium3M)
1750      .Case("pentium-m", CK_PentiumM)
1751      .Case("c3-2", CK_C3_2)
1752      .Case("yonah", CK_Yonah)
1753      .Case("pentium4", CK_Pentium4)
1754      .Case("pentium4m", CK_Pentium4M)
1755      .Case("prescott", CK_Prescott)
1756      .Case("nocona", CK_Nocona)
1757      .Case("core2", CK_Core2)
1758      .Case("penryn", CK_Penryn)
1759      .Case("atom", CK_Atom)
1760      .Case("corei7", CK_Corei7)
1761      .Case("corei7-avx", CK_Corei7AVX)
1762      .Case("core-avx-i", CK_CoreAVXi)
1763      .Case("core-avx2", CK_CoreAVX2)
1764      .Case("k6", CK_K6)
1765      .Case("k6-2", CK_K6_2)
1766      .Case("k6-3", CK_K6_3)
1767      .Case("athlon", CK_Athlon)
1768      .Case("athlon-tbird", CK_AthlonThunderbird)
1769      .Case("athlon-4", CK_Athlon4)
1770      .Case("athlon-xp", CK_AthlonXP)
1771      .Case("athlon-mp", CK_AthlonMP)
1772      .Case("athlon64", CK_Athlon64)
1773      .Case("athlon64-sse3", CK_Athlon64SSE3)
1774      .Case("athlon-fx", CK_AthlonFX)
1775      .Case("k8", CK_K8)
1776      .Case("k8-sse3", CK_K8SSE3)
1777      .Case("opteron", CK_Opteron)
1778      .Case("opteron-sse3", CK_OpteronSSE3)
1779      .Case("amdfam10", CK_AMDFAM10)
1780      .Case("btver1", CK_BTVER1)
1781      .Case("bdver1", CK_BDVER1)
1782      .Case("bdver2", CK_BDVER2)
1783      .Case("x86-64", CK_x86_64)
1784      .Case("geode", CK_Geode)
1785      .Default(CK_Generic);
1786
1787    // Perform any per-CPU checks necessary to determine if this CPU is
1788    // acceptable.
1789    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1790    // invalid without explaining *why*.
1791    switch (CPU) {
1792    case CK_Generic:
1793      // No processor selected!
1794      return false;
1795
1796    case CK_i386:
1797    case CK_i486:
1798    case CK_WinChipC6:
1799    case CK_WinChip2:
1800    case CK_C3:
1801    case CK_i586:
1802    case CK_Pentium:
1803    case CK_PentiumMMX:
1804    case CK_i686:
1805    case CK_PentiumPro:
1806    case CK_Pentium2:
1807    case CK_Pentium3:
1808    case CK_Pentium3M:
1809    case CK_PentiumM:
1810    case CK_Yonah:
1811    case CK_C3_2:
1812    case CK_Pentium4:
1813    case CK_Pentium4M:
1814    case CK_Prescott:
1815    case CK_K6:
1816    case CK_K6_2:
1817    case CK_K6_3:
1818    case CK_Athlon:
1819    case CK_AthlonThunderbird:
1820    case CK_Athlon4:
1821    case CK_AthlonXP:
1822    case CK_AthlonMP:
1823    case CK_Geode:
1824      // Only accept certain architectures when compiling in 32-bit mode.
1825      if (getTriple().getArch() != llvm::Triple::x86)
1826        return false;
1827
1828      // Fallthrough
1829    case CK_Nocona:
1830    case CK_Core2:
1831    case CK_Penryn:
1832    case CK_Atom:
1833    case CK_Corei7:
1834    case CK_Corei7AVX:
1835    case CK_CoreAVXi:
1836    case CK_CoreAVX2:
1837    case CK_Athlon64:
1838    case CK_Athlon64SSE3:
1839    case CK_AthlonFX:
1840    case CK_K8:
1841    case CK_K8SSE3:
1842    case CK_Opteron:
1843    case CK_OpteronSSE3:
1844    case CK_AMDFAM10:
1845    case CK_BTVER1:
1846    case CK_BDVER1:
1847    case CK_BDVER2:
1848    case CK_x86_64:
1849      return true;
1850    }
1851    llvm_unreachable("Unhandled CPU kind");
1852  }
1853
1854  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1855    // We accept all non-ARM calling conventions
1856    return (CC == CC_X86ThisCall ||
1857            CC == CC_X86FastCall ||
1858            CC == CC_X86StdCall ||
1859            CC == CC_C ||
1860            CC == CC_X86Pascal ||
1861            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
1862  }
1863
1864  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
1865    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
1866  }
1867};
1868
1869void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1870  // FIXME: This should not be here.
1871  Features["3dnow"] = false;
1872  Features["3dnowa"] = false;
1873  Features["mmx"] = false;
1874  Features["sse"] = false;
1875  Features["sse2"] = false;
1876  Features["sse3"] = false;
1877  Features["ssse3"] = false;
1878  Features["sse41"] = false;
1879  Features["sse42"] = false;
1880  Features["sse4a"] = false;
1881  Features["aes"] = false;
1882  Features["pclmul"] = false;
1883  Features["avx"] = false;
1884  Features["avx2"] = false;
1885  Features["lzcnt"] = false;
1886  Features["rdrand"] = false;
1887  Features["bmi"] = false;
1888  Features["bmi2"] = false;
1889  Features["popcnt"] = false;
1890  Features["rtm"] = false;
1891  Features["fma4"] = false;
1892  Features["fma"] = false;
1893  Features["xop"] = false;
1894  Features["f16c"] = false;
1895
1896  // FIXME: This *really* should not be here.
1897
1898  // X86_64 always has SSE2.
1899  if (getTriple().getArch() == llvm::Triple::x86_64)
1900    setFeatureEnabled(Features, "sse2", true);
1901
1902  switch (CPU) {
1903  case CK_Generic:
1904  case CK_i386:
1905  case CK_i486:
1906  case CK_i586:
1907  case CK_Pentium:
1908  case CK_i686:
1909  case CK_PentiumPro:
1910    break;
1911  case CK_PentiumMMX:
1912  case CK_Pentium2:
1913    setFeatureEnabled(Features, "mmx", true);
1914    break;
1915  case CK_Pentium3:
1916  case CK_Pentium3M:
1917    setFeatureEnabled(Features, "sse", true);
1918    break;
1919  case CK_PentiumM:
1920  case CK_Pentium4:
1921  case CK_Pentium4M:
1922  case CK_x86_64:
1923    setFeatureEnabled(Features, "sse2", true);
1924    break;
1925  case CK_Yonah:
1926  case CK_Prescott:
1927  case CK_Nocona:
1928    setFeatureEnabled(Features, "sse3", true);
1929    break;
1930  case CK_Core2:
1931    setFeatureEnabled(Features, "ssse3", true);
1932    break;
1933  case CK_Penryn:
1934    setFeatureEnabled(Features, "sse4.1", true);
1935    break;
1936  case CK_Atom:
1937    setFeatureEnabled(Features, "ssse3", true);
1938    break;
1939  case CK_Corei7:
1940    setFeatureEnabled(Features, "sse4", true);
1941    break;
1942  case CK_Corei7AVX:
1943    setFeatureEnabled(Features, "avx", true);
1944    setFeatureEnabled(Features, "aes", true);
1945    setFeatureEnabled(Features, "pclmul", true);
1946    break;
1947  case CK_CoreAVXi:
1948    setFeatureEnabled(Features, "avx", true);
1949    setFeatureEnabled(Features, "aes", true);
1950    setFeatureEnabled(Features, "pclmul", true);
1951    setFeatureEnabled(Features, "rdrnd", true);
1952    setFeatureEnabled(Features, "f16c", true);
1953    break;
1954  case CK_CoreAVX2:
1955    setFeatureEnabled(Features, "avx2", true);
1956    setFeatureEnabled(Features, "aes", true);
1957    setFeatureEnabled(Features, "pclmul", true);
1958    setFeatureEnabled(Features, "lzcnt", true);
1959    setFeatureEnabled(Features, "rdrnd", true);
1960    setFeatureEnabled(Features, "f16c", true);
1961    setFeatureEnabled(Features, "bmi", true);
1962    setFeatureEnabled(Features, "bmi2", true);
1963    setFeatureEnabled(Features, "rtm", true);
1964    setFeatureEnabled(Features, "fma", true);
1965    break;
1966  case CK_K6:
1967  case CK_WinChipC6:
1968    setFeatureEnabled(Features, "mmx", true);
1969    break;
1970  case CK_K6_2:
1971  case CK_K6_3:
1972  case CK_WinChip2:
1973  case CK_C3:
1974    setFeatureEnabled(Features, "3dnow", true);
1975    break;
1976  case CK_Athlon:
1977  case CK_AthlonThunderbird:
1978  case CK_Geode:
1979    setFeatureEnabled(Features, "3dnowa", true);
1980    break;
1981  case CK_Athlon4:
1982  case CK_AthlonXP:
1983  case CK_AthlonMP:
1984    setFeatureEnabled(Features, "sse", true);
1985    setFeatureEnabled(Features, "3dnowa", true);
1986    break;
1987  case CK_K8:
1988  case CK_Opteron:
1989  case CK_Athlon64:
1990  case CK_AthlonFX:
1991    setFeatureEnabled(Features, "sse2", true);
1992    setFeatureEnabled(Features, "3dnowa", true);
1993    break;
1994  case CK_K8SSE3:
1995  case CK_OpteronSSE3:
1996  case CK_Athlon64SSE3:
1997    setFeatureEnabled(Features, "sse3", true);
1998    setFeatureEnabled(Features, "3dnowa", true);
1999    break;
2000  case CK_AMDFAM10:
2001    setFeatureEnabled(Features, "sse3", true);
2002    setFeatureEnabled(Features, "sse4a", true);
2003    setFeatureEnabled(Features, "3dnowa", true);
2004    setFeatureEnabled(Features, "lzcnt", true);
2005    setFeatureEnabled(Features, "popcnt", true);
2006    break;
2007  case CK_BTVER1:
2008    setFeatureEnabled(Features, "ssse3", true);
2009    setFeatureEnabled(Features, "sse4a", true);
2010    setFeatureEnabled(Features, "lzcnt", true);
2011    setFeatureEnabled(Features, "popcnt", true);
2012    break;
2013  case CK_BDVER1:
2014    setFeatureEnabled(Features, "xop", true);
2015    setFeatureEnabled(Features, "lzcnt", true);
2016    setFeatureEnabled(Features, "aes", true);
2017    setFeatureEnabled(Features, "pclmul", true);
2018    break;
2019  case CK_BDVER2:
2020    setFeatureEnabled(Features, "xop", true);
2021    setFeatureEnabled(Features, "lzcnt", true);
2022    setFeatureEnabled(Features, "aes", true);
2023    setFeatureEnabled(Features, "pclmul", true);
2024    setFeatureEnabled(Features, "bmi", true);
2025    setFeatureEnabled(Features, "fma", true);
2026    setFeatureEnabled(Features, "f16c", true);
2027    break;
2028  case CK_C3_2:
2029    setFeatureEnabled(Features, "sse", true);
2030    break;
2031  }
2032}
2033
2034bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2035                                      StringRef Name,
2036                                      bool Enabled) const {
2037  // FIXME: This *really* should not be here.  We need some way of translating
2038  // options into llvm subtarget features.
2039  if (!Features.count(Name) &&
2040      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2041       Name != "rdrnd"))
2042    return false;
2043
2044  // FIXME: this should probably use a switch with fall through.
2045
2046  if (Enabled) {
2047    if (Name == "mmx")
2048      Features["mmx"] = true;
2049    else if (Name == "sse")
2050      Features["mmx"] = Features["sse"] = true;
2051    else if (Name == "sse2")
2052      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2053    else if (Name == "sse3")
2054      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2055        true;
2056    else if (Name == "ssse3")
2057      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2058        Features["ssse3"] = true;
2059    else if (Name == "sse4" || Name == "sse4.2")
2060      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2061        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2062        Features["popcnt"] = true;
2063    else if (Name == "sse4.1")
2064      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2065        Features["ssse3"] = Features["sse41"] = true;
2066    else if (Name == "3dnow")
2067      Features["mmx"] = Features["3dnow"] = true;
2068    else if (Name == "3dnowa")
2069      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2070    else if (Name == "aes")
2071      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2072    else if (Name == "pclmul")
2073      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2074    else if (Name == "avx")
2075      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2076        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2077        Features["popcnt"] = Features["avx"] = true;
2078    else if (Name == "avx2")
2079      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2080        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2081        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2082    else if (Name == "fma")
2083      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2084        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2085        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2086    else if (Name == "fma4")
2087      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2088        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2089        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2090        Features["fma4"] = true;
2091    else if (Name == "xop")
2092      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2093        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2094        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2095        Features["fma4"] = Features["xop"] = true;
2096    else if (Name == "sse4a")
2097      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2098        Features["sse4a"] = true;
2099    else if (Name == "lzcnt")
2100      Features["lzcnt"] = true;
2101    else if (Name == "rdrnd")
2102      Features["rdrand"] = true;
2103    else if (Name == "bmi")
2104      Features["bmi"] = true;
2105    else if (Name == "bmi2")
2106      Features["bmi2"] = true;
2107    else if (Name == "popcnt")
2108      Features["popcnt"] = true;
2109    else if (Name == "f16c")
2110      Features["f16c"] = true;
2111    else if (Name == "rtm")
2112      Features["rtm"] = true;
2113  } else {
2114    if (Name == "mmx")
2115      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2116    else if (Name == "sse")
2117      Features["sse"] = Features["sse2"] = Features["sse3"] =
2118        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2119        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2120        Features["fma"] = Features["fma4"] = Features["aes"] =
2121        Features["pclmul"] = Features["xop"] = false;
2122    else if (Name == "sse2")
2123      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2124        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2125        Features["avx"] = Features["avx2"] = Features["fma"] =
2126        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2127        Features["xop"] = false;
2128    else if (Name == "sse3")
2129      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2130        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2131        Features["avx2"] = Features["fma"] = Features["fma4"] =
2132        Features["xop"] = false;
2133    else if (Name == "ssse3")
2134      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2135        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2136    else if (Name == "sse4" || Name == "sse4.1")
2137      Features["sse41"] = Features["sse42"] = Features["avx"] =
2138        Features["avx2"] = Features["fma"] = false;
2139    else if (Name == "sse4.2")
2140      Features["sse42"] = Features["avx"] = Features["avx2"] =
2141        Features["fma"] = false;
2142    else if (Name == "3dnow")
2143      Features["3dnow"] = Features["3dnowa"] = false;
2144    else if (Name == "3dnowa")
2145      Features["3dnowa"] = false;
2146    else if (Name == "aes")
2147      Features["aes"] = false;
2148    else if (Name == "pclmul")
2149      Features["pclmul"] = false;
2150    else if (Name == "avx")
2151      Features["avx"] = Features["avx2"] = Features["fma"] =
2152        Features["fma4"] = Features["xop"] = false;
2153    else if (Name == "avx2")
2154      Features["avx2"] = false;
2155    else if (Name == "fma")
2156      Features["fma"] = false;
2157    else if (Name == "sse4a")
2158      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2159    else if (Name == "lzcnt")
2160      Features["lzcnt"] = false;
2161    else if (Name == "rdrnd")
2162      Features["rdrand"] = false;
2163    else if (Name == "bmi")
2164      Features["bmi"] = false;
2165    else if (Name == "bmi2")
2166      Features["bmi2"] = false;
2167    else if (Name == "popcnt")
2168      Features["popcnt"] = false;
2169    else if (Name == "fma4")
2170      Features["fma4"] = Features["xop"] = false;
2171    else if (Name == "xop")
2172      Features["xop"] = false;
2173    else if (Name == "f16c")
2174      Features["f16c"] = false;
2175    else if (Name == "rtm")
2176      Features["rtm"] = false;
2177  }
2178
2179  return true;
2180}
2181
2182/// HandleTargetOptions - Perform initialization based on the user
2183/// configured set of features.
2184void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2185  // Remember the maximum enabled sselevel.
2186  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2187    // Ignore disabled features.
2188    if (Features[i][0] == '-')
2189      continue;
2190
2191    StringRef Feature = StringRef(Features[i]).substr(1);
2192
2193    if (Feature == "aes") {
2194      HasAES = true;
2195      continue;
2196    }
2197
2198    if (Feature == "pclmul") {
2199      HasPCLMUL = true;
2200      continue;
2201    }
2202
2203    if (Feature == "lzcnt") {
2204      HasLZCNT = true;
2205      continue;
2206    }
2207
2208    if (Feature == "rdrand") {
2209      HasRDRND = true;
2210      continue;
2211    }
2212
2213    if (Feature == "bmi") {
2214      HasBMI = true;
2215      continue;
2216    }
2217
2218    if (Feature == "bmi2") {
2219      HasBMI2 = true;
2220      continue;
2221    }
2222
2223    if (Feature == "popcnt") {
2224      HasPOPCNT = true;
2225      continue;
2226    }
2227
2228    if (Feature == "rtm") {
2229      HasRTM = true;
2230      continue;
2231    }
2232
2233    if (Feature == "sse4a") {
2234      HasSSE4a = true;
2235      continue;
2236    }
2237
2238    if (Feature == "fma4") {
2239      HasFMA4 = true;
2240      continue;
2241    }
2242
2243    if (Feature == "fma") {
2244      HasFMA = true;
2245      continue;
2246    }
2247
2248    if (Feature == "xop") {
2249      HasXOP = true;
2250      continue;
2251    }
2252
2253    if (Feature == "f16c") {
2254      HasF16C = true;
2255      continue;
2256    }
2257
2258    assert(Features[i][0] == '+' && "Invalid target feature!");
2259    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2260      .Case("avx2", AVX2)
2261      .Case("avx", AVX)
2262      .Case("sse42", SSE42)
2263      .Case("sse41", SSE41)
2264      .Case("ssse3", SSSE3)
2265      .Case("sse3", SSE3)
2266      .Case("sse2", SSE2)
2267      .Case("sse", SSE1)
2268      .Default(NoSSE);
2269    SSELevel = std::max(SSELevel, Level);
2270
2271    MMX3DNowEnum ThreeDNowLevel =
2272      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2273        .Case("3dnowa", AMD3DNowAthlon)
2274        .Case("3dnow", AMD3DNow)
2275        .Case("mmx", MMX)
2276        .Default(NoMMX3DNow);
2277
2278    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2279  }
2280
2281  // Don't tell the backend if we're turning off mmx; it will end up disabling
2282  // SSE, which we don't want.
2283  std::vector<std::string>::iterator it;
2284  it = std::find(Features.begin(), Features.end(), "-mmx");
2285  if (it != Features.end())
2286    Features.erase(it);
2287}
2288
2289/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2290/// definitions for this particular subtarget.
2291void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2292                                     MacroBuilder &Builder) const {
2293  // Target identification.
2294  if (getTriple().getArch() == llvm::Triple::x86_64) {
2295    Builder.defineMacro("__amd64__");
2296    Builder.defineMacro("__amd64");
2297    Builder.defineMacro("__x86_64");
2298    Builder.defineMacro("__x86_64__");
2299  } else {
2300    DefineStd(Builder, "i386", Opts);
2301  }
2302
2303  // Subtarget options.
2304  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2305  // truly should be based on -mtune options.
2306  switch (CPU) {
2307  case CK_Generic:
2308    break;
2309  case CK_i386:
2310    // The rest are coming from the i386 define above.
2311    Builder.defineMacro("__tune_i386__");
2312    break;
2313  case CK_i486:
2314  case CK_WinChipC6:
2315  case CK_WinChip2:
2316  case CK_C3:
2317    defineCPUMacros(Builder, "i486");
2318    break;
2319  case CK_PentiumMMX:
2320    Builder.defineMacro("__pentium_mmx__");
2321    Builder.defineMacro("__tune_pentium_mmx__");
2322    // Fallthrough
2323  case CK_i586:
2324  case CK_Pentium:
2325    defineCPUMacros(Builder, "i586");
2326    defineCPUMacros(Builder, "pentium");
2327    break;
2328  case CK_Pentium3:
2329  case CK_Pentium3M:
2330  case CK_PentiumM:
2331    Builder.defineMacro("__tune_pentium3__");
2332    // Fallthrough
2333  case CK_Pentium2:
2334  case CK_C3_2:
2335    Builder.defineMacro("__tune_pentium2__");
2336    // Fallthrough
2337  case CK_PentiumPro:
2338    Builder.defineMacro("__tune_i686__");
2339    Builder.defineMacro("__tune_pentiumpro__");
2340    // Fallthrough
2341  case CK_i686:
2342    Builder.defineMacro("__i686");
2343    Builder.defineMacro("__i686__");
2344    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2345    Builder.defineMacro("__pentiumpro");
2346    Builder.defineMacro("__pentiumpro__");
2347    break;
2348  case CK_Pentium4:
2349  case CK_Pentium4M:
2350    defineCPUMacros(Builder, "pentium4");
2351    break;
2352  case CK_Yonah:
2353  case CK_Prescott:
2354  case CK_Nocona:
2355    defineCPUMacros(Builder, "nocona");
2356    break;
2357  case CK_Core2:
2358  case CK_Penryn:
2359    defineCPUMacros(Builder, "core2");
2360    break;
2361  case CK_Atom:
2362    defineCPUMacros(Builder, "atom");
2363    break;
2364  case CK_Corei7:
2365  case CK_Corei7AVX:
2366  case CK_CoreAVXi:
2367  case CK_CoreAVX2:
2368    defineCPUMacros(Builder, "corei7");
2369    break;
2370  case CK_K6_2:
2371    Builder.defineMacro("__k6_2__");
2372    Builder.defineMacro("__tune_k6_2__");
2373    // Fallthrough
2374  case CK_K6_3:
2375    if (CPU != CK_K6_2) {  // In case of fallthrough
2376      // FIXME: GCC may be enabling these in cases where some other k6
2377      // architecture is specified but -m3dnow is explicitly provided. The
2378      // exact semantics need to be determined and emulated here.
2379      Builder.defineMacro("__k6_3__");
2380      Builder.defineMacro("__tune_k6_3__");
2381    }
2382    // Fallthrough
2383  case CK_K6:
2384    defineCPUMacros(Builder, "k6");
2385    break;
2386  case CK_Athlon:
2387  case CK_AthlonThunderbird:
2388  case CK_Athlon4:
2389  case CK_AthlonXP:
2390  case CK_AthlonMP:
2391    defineCPUMacros(Builder, "athlon");
2392    if (SSELevel != NoSSE) {
2393      Builder.defineMacro("__athlon_sse__");
2394      Builder.defineMacro("__tune_athlon_sse__");
2395    }
2396    break;
2397  case CK_K8:
2398  case CK_K8SSE3:
2399  case CK_x86_64:
2400  case CK_Opteron:
2401  case CK_OpteronSSE3:
2402  case CK_Athlon64:
2403  case CK_Athlon64SSE3:
2404  case CK_AthlonFX:
2405    defineCPUMacros(Builder, "k8");
2406    break;
2407  case CK_AMDFAM10:
2408    defineCPUMacros(Builder, "amdfam10");
2409    break;
2410  case CK_BTVER1:
2411    defineCPUMacros(Builder, "btver1");
2412    break;
2413  case CK_BDVER1:
2414    defineCPUMacros(Builder, "bdver1");
2415    break;
2416  case CK_BDVER2:
2417    defineCPUMacros(Builder, "bdver2");
2418    break;
2419  case CK_Geode:
2420    defineCPUMacros(Builder, "geode");
2421    break;
2422  }
2423
2424  // Target properties.
2425  Builder.defineMacro("__LITTLE_ENDIAN__");
2426  Builder.defineMacro("__REGISTER_PREFIX__", "");
2427
2428  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2429  // functions in glibc header files that use FP Stack inline asm which the
2430  // backend can't deal with (PR879).
2431  Builder.defineMacro("__NO_MATH_INLINES");
2432
2433  if (HasAES)
2434    Builder.defineMacro("__AES__");
2435
2436  if (HasPCLMUL)
2437    Builder.defineMacro("__PCLMUL__");
2438
2439  if (HasLZCNT)
2440    Builder.defineMacro("__LZCNT__");
2441
2442  if (HasRDRND)
2443    Builder.defineMacro("__RDRND__");
2444
2445  if (HasBMI)
2446    Builder.defineMacro("__BMI__");
2447
2448  if (HasBMI2)
2449    Builder.defineMacro("__BMI2__");
2450
2451  if (HasPOPCNT)
2452    Builder.defineMacro("__POPCNT__");
2453
2454  if (HasRTM)
2455    Builder.defineMacro("__RTM__");
2456
2457  if (HasSSE4a)
2458    Builder.defineMacro("__SSE4A__");
2459
2460  if (HasFMA4)
2461    Builder.defineMacro("__FMA4__");
2462
2463  if (HasFMA)
2464    Builder.defineMacro("__FMA__");
2465
2466  if (HasXOP)
2467    Builder.defineMacro("__XOP__");
2468
2469  if (HasF16C)
2470    Builder.defineMacro("__F16C__");
2471
2472  // Each case falls through to the previous one here.
2473  switch (SSELevel) {
2474  case AVX2:
2475    Builder.defineMacro("__AVX2__");
2476  case AVX:
2477    Builder.defineMacro("__AVX__");
2478  case SSE42:
2479    Builder.defineMacro("__SSE4_2__");
2480  case SSE41:
2481    Builder.defineMacro("__SSE4_1__");
2482  case SSSE3:
2483    Builder.defineMacro("__SSSE3__");
2484  case SSE3:
2485    Builder.defineMacro("__SSE3__");
2486  case SSE2:
2487    Builder.defineMacro("__SSE2__");
2488    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2489  case SSE1:
2490    Builder.defineMacro("__SSE__");
2491    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2492  case NoSSE:
2493    break;
2494  }
2495
2496  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2497    switch (SSELevel) {
2498    case AVX2:
2499    case AVX:
2500    case SSE42:
2501    case SSE41:
2502    case SSSE3:
2503    case SSE3:
2504    case SSE2:
2505      Builder.defineMacro("_M_IX86_FP", Twine(2));
2506      break;
2507    case SSE1:
2508      Builder.defineMacro("_M_IX86_FP", Twine(1));
2509      break;
2510    default:
2511      Builder.defineMacro("_M_IX86_FP", Twine(0));
2512    }
2513  }
2514
2515  // Each case falls through to the previous one here.
2516  switch (MMX3DNowLevel) {
2517  case AMD3DNowAthlon:
2518    Builder.defineMacro("__3dNOW_A__");
2519  case AMD3DNow:
2520    Builder.defineMacro("__3dNOW__");
2521  case MMX:
2522    Builder.defineMacro("__MMX__");
2523  case NoMMX3DNow:
2524    break;
2525  }
2526}
2527
2528bool X86TargetInfo::hasFeature(StringRef Feature) const {
2529  return llvm::StringSwitch<bool>(Feature)
2530      .Case("aes", HasAES)
2531      .Case("avx", SSELevel >= AVX)
2532      .Case("avx2", SSELevel >= AVX2)
2533      .Case("bmi", HasBMI)
2534      .Case("bmi2", HasBMI2)
2535      .Case("fma", HasFMA)
2536      .Case("fma4", HasFMA4)
2537      .Case("lzcnt", HasLZCNT)
2538      .Case("rdrnd", HasRDRND)
2539      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2540      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2541      .Case("mmx", MMX3DNowLevel >= MMX)
2542      .Case("pclmul", HasPCLMUL)
2543      .Case("popcnt", HasPOPCNT)
2544      .Case("rtm", HasRTM)
2545      .Case("sse", SSELevel >= SSE1)
2546      .Case("sse2", SSELevel >= SSE2)
2547      .Case("sse3", SSELevel >= SSE3)
2548      .Case("ssse3", SSELevel >= SSSE3)
2549      .Case("sse41", SSELevel >= SSE41)
2550      .Case("sse42", SSELevel >= SSE42)
2551      .Case("sse4a", HasSSE4a)
2552      .Case("x86", true)
2553      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2554      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2555      .Case("xop", HasXOP)
2556      .Case("f16c", HasF16C)
2557      .Default(false);
2558}
2559
2560bool
2561X86TargetInfo::validateAsmConstraint(const char *&Name,
2562                                     TargetInfo::ConstraintInfo &Info) const {
2563  switch (*Name) {
2564  default: return false;
2565  case 'Y': // first letter of a pair:
2566    switch (*(Name+1)) {
2567    default: return false;
2568    case '0':  // First SSE register.
2569    case 't':  // Any SSE register, when SSE2 is enabled.
2570    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2571    case 'm':  // any MMX register, when inter-unit moves enabled.
2572      break;   // falls through to setAllowsRegister.
2573  }
2574  case 'a': // eax.
2575  case 'b': // ebx.
2576  case 'c': // ecx.
2577  case 'd': // edx.
2578  case 'S': // esi.
2579  case 'D': // edi.
2580  case 'A': // edx:eax.
2581  case 'f': // any x87 floating point stack register.
2582  case 't': // top of floating point stack.
2583  case 'u': // second from top of floating point stack.
2584  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2585  case 'y': // Any MMX register.
2586  case 'x': // Any SSE register.
2587  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2588  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2589  case 'l': // "Index" registers: any general register that can be used as an
2590            // index in a base+index memory access.
2591    Info.setAllowsRegister();
2592    return true;
2593  case 'C': // SSE floating point constant.
2594  case 'G': // x87 floating point constant.
2595  case 'e': // 32-bit signed integer constant for use with zero-extending
2596            // x86_64 instructions.
2597  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2598            // x86_64 instructions.
2599    return true;
2600  }
2601}
2602
2603
2604std::string
2605X86TargetInfo::convertConstraint(const char *&Constraint) const {
2606  switch (*Constraint) {
2607  case 'a': return std::string("{ax}");
2608  case 'b': return std::string("{bx}");
2609  case 'c': return std::string("{cx}");
2610  case 'd': return std::string("{dx}");
2611  case 'S': return std::string("{si}");
2612  case 'D': return std::string("{di}");
2613  case 'p': // address
2614    return std::string("im");
2615  case 't': // top of floating point stack.
2616    return std::string("{st}");
2617  case 'u': // second from top of floating point stack.
2618    return std::string("{st(1)}"); // second from top of floating point stack.
2619  default:
2620    return std::string(1, *Constraint);
2621  }
2622}
2623} // end anonymous namespace
2624
2625namespace {
2626// X86-32 generic target
2627class X86_32TargetInfo : public X86TargetInfo {
2628public:
2629  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2630    DoubleAlign = LongLongAlign = 32;
2631    LongDoubleWidth = 96;
2632    LongDoubleAlign = 32;
2633    SuitableAlign = 128;
2634    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2635                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2636                        "a0:0:64-f80:32:32-n8:16:32-S128";
2637    SizeType = UnsignedInt;
2638    PtrDiffType = SignedInt;
2639    IntPtrType = SignedInt;
2640    RegParmMax = 3;
2641
2642    // Use fpret for all types.
2643    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2644                             (1 << TargetInfo::Double) |
2645                             (1 << TargetInfo::LongDouble));
2646
2647    // x86-32 has atomics up to 8 bytes
2648    // FIXME: Check that we actually have cmpxchg8b before setting
2649    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2650    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2651  }
2652  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2653    return TargetInfo::CharPtrBuiltinVaList;
2654  }
2655
2656  int getEHDataRegisterNumber(unsigned RegNo) const {
2657    if (RegNo == 0) return 0;
2658    if (RegNo == 1) return 2;
2659    return -1;
2660  }
2661  virtual bool validateInputSize(StringRef Constraint,
2662                                 unsigned Size) const {
2663    switch (Constraint[0]) {
2664    default: break;
2665    case 'a':
2666    case 'b':
2667    case 'c':
2668    case 'd':
2669      return Size <= 32;
2670    }
2671
2672    return true;
2673  }
2674};
2675} // end anonymous namespace
2676
2677namespace {
2678class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2679public:
2680  NetBSDI386TargetInfo(const std::string &triple) :
2681    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2682  }
2683
2684  virtual unsigned getFloatEvalMethod() const {
2685    // NetBSD defaults to "double" rounding
2686    return 1;
2687  }
2688};
2689} // end anonymous namespace
2690
2691namespace {
2692class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2693public:
2694  OpenBSDI386TargetInfo(const std::string& triple) :
2695    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2696    SizeType = UnsignedLong;
2697    IntPtrType = SignedLong;
2698    PtrDiffType = SignedLong;
2699  }
2700};
2701} // end anonymous namespace
2702
2703namespace {
2704class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2705public:
2706  BitrigI386TargetInfo(const std::string& triple) :
2707    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2708    SizeType = UnsignedLong;
2709    IntPtrType = SignedLong;
2710    PtrDiffType = SignedLong;
2711  }
2712};
2713} // end anonymous namespace
2714
2715namespace {
2716class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2717public:
2718  DarwinI386TargetInfo(const std::string& triple) :
2719    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2720    LongDoubleWidth = 128;
2721    LongDoubleAlign = 128;
2722    SuitableAlign = 128;
2723    MaxVectorAlign = 256;
2724    SizeType = UnsignedLong;
2725    IntPtrType = SignedLong;
2726    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2727                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2728                        "a0:0:64-f80:128:128-n8:16:32-S128";
2729    HasAlignMac68kSupport = true;
2730  }
2731
2732};
2733} // end anonymous namespace
2734
2735namespace {
2736// x86-32 Windows target
2737class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2738public:
2739  WindowsX86_32TargetInfo(const std::string& triple)
2740    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2741    TLSSupported = false;
2742    WCharType = UnsignedShort;
2743    DoubleAlign = LongLongAlign = 64;
2744    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2745                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2746                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2747  }
2748  virtual void getTargetDefines(const LangOptions &Opts,
2749                                MacroBuilder &Builder) const {
2750    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2751  }
2752};
2753} // end anonymous namespace
2754
2755namespace {
2756
2757// x86-32 Windows Visual Studio target
2758class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2759public:
2760  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2761    : WindowsX86_32TargetInfo(triple) {
2762    LongDoubleWidth = LongDoubleAlign = 64;
2763    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2764  }
2765  virtual void getTargetDefines(const LangOptions &Opts,
2766                                MacroBuilder &Builder) const {
2767    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2768    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2769    // The value of the following reflects processor type.
2770    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2771    // We lost the original triple, so we use the default.
2772    Builder.defineMacro("_M_IX86", "600");
2773  }
2774};
2775} // end anonymous namespace
2776
2777namespace {
2778// x86-32 MinGW target
2779class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2780public:
2781  MinGWX86_32TargetInfo(const std::string& triple)
2782    : WindowsX86_32TargetInfo(triple) {
2783  }
2784  virtual void getTargetDefines(const LangOptions &Opts,
2785                                MacroBuilder &Builder) const {
2786    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2787    DefineStd(Builder, "WIN32", Opts);
2788    DefineStd(Builder, "WINNT", Opts);
2789    Builder.defineMacro("_X86_");
2790    Builder.defineMacro("__MSVCRT__");
2791    Builder.defineMacro("__MINGW32__");
2792
2793    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2794    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2795    if (Opts.MicrosoftExt)
2796      // Provide "as-is" __declspec.
2797      Builder.defineMacro("__declspec", "__declspec");
2798    else
2799      // Provide alias of __attribute__ like mingw32-gcc.
2800      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2801  }
2802};
2803} // end anonymous namespace
2804
2805namespace {
2806// x86-32 Cygwin target
2807class CygwinX86_32TargetInfo : public X86_32TargetInfo {
2808public:
2809  CygwinX86_32TargetInfo(const std::string& triple)
2810    : X86_32TargetInfo(triple) {
2811    TLSSupported = false;
2812    WCharType = UnsignedShort;
2813    DoubleAlign = LongLongAlign = 64;
2814    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2815                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2816                        "a0:0:64-f80:32:32-n8:16:32-S32";
2817  }
2818  virtual void getTargetDefines(const LangOptions &Opts,
2819                                MacroBuilder &Builder) const {
2820    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2821    Builder.defineMacro("_X86_");
2822    Builder.defineMacro("__CYGWIN__");
2823    Builder.defineMacro("__CYGWIN32__");
2824    DefineStd(Builder, "unix", Opts);
2825    if (Opts.CPlusPlus)
2826      Builder.defineMacro("_GNU_SOURCE");
2827  }
2828};
2829} // end anonymous namespace
2830
2831namespace {
2832// x86-32 Haiku target
2833class HaikuX86_32TargetInfo : public X86_32TargetInfo {
2834public:
2835  HaikuX86_32TargetInfo(const std::string& triple)
2836    : X86_32TargetInfo(triple) {
2837    SizeType = UnsignedLong;
2838    IntPtrType = SignedLong;
2839    PtrDiffType = SignedLong;
2840    ProcessIDType = SignedLong;
2841    this->UserLabelPrefix = "";
2842    this->TLSSupported = false;
2843  }
2844  virtual void getTargetDefines(const LangOptions &Opts,
2845                                MacroBuilder &Builder) const {
2846    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2847    Builder.defineMacro("__INTEL__");
2848    Builder.defineMacro("__HAIKU__");
2849  }
2850};
2851} // end anonymous namespace
2852
2853// RTEMS Target
2854template<typename Target>
2855class RTEMSTargetInfo : public OSTargetInfo<Target> {
2856protected:
2857  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
2858                            MacroBuilder &Builder) const {
2859    // RTEMS defines; list based off of gcc output
2860
2861    Builder.defineMacro("__rtems__");
2862    Builder.defineMacro("__ELF__");
2863  }
2864public:
2865  RTEMSTargetInfo(const std::string &triple)
2866    : OSTargetInfo<Target>(triple) {
2867      this->UserLabelPrefix = "";
2868
2869      llvm::Triple Triple(triple);
2870      switch (Triple.getArch()) {
2871        default:
2872        case llvm::Triple::x86:
2873          // this->MCountName = ".mcount";
2874          break;
2875        case llvm::Triple::mips:
2876        case llvm::Triple::mipsel:
2877        case llvm::Triple::ppc:
2878        case llvm::Triple::ppc64:
2879          // this->MCountName = "_mcount";
2880          break;
2881        case llvm::Triple::arm:
2882          // this->MCountName = "__mcount";
2883          break;
2884      }
2885
2886    }
2887};
2888
2889namespace {
2890// x86-32 RTEMS target
2891class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
2892public:
2893  RTEMSX86_32TargetInfo(const std::string& triple)
2894    : X86_32TargetInfo(triple) {
2895    SizeType = UnsignedLong;
2896    IntPtrType = SignedLong;
2897    PtrDiffType = SignedLong;
2898    this->UserLabelPrefix = "";
2899  }
2900  virtual void getTargetDefines(const LangOptions &Opts,
2901                                MacroBuilder &Builder) const {
2902    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2903    Builder.defineMacro("__INTEL__");
2904    Builder.defineMacro("__rtems__");
2905  }
2906};
2907} // end anonymous namespace
2908
2909namespace {
2910// x86-64 generic target
2911class X86_64TargetInfo : public X86TargetInfo {
2912public:
2913  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
2914    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
2915    LongDoubleWidth = 128;
2916    LongDoubleAlign = 128;
2917    LargeArrayMinWidth = 128;
2918    LargeArrayAlign = 128;
2919    SuitableAlign = 128;
2920    IntMaxType = SignedLong;
2921    UIntMaxType = UnsignedLong;
2922    Int64Type = SignedLong;
2923    RegParmMax = 6;
2924
2925    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2926                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2927                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
2928
2929    // Use fpret only for long double.
2930    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
2931
2932    // Use fp2ret for _Complex long double.
2933    ComplexLongDoubleUsesFP2Ret = true;
2934
2935    // x86-64 has atomics up to 16 bytes.
2936    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
2937    // on CPUs with cmpxchg16b
2938    MaxAtomicPromoteWidth = 128;
2939    MaxAtomicInlineWidth = 64;
2940  }
2941  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2942    return TargetInfo::X86_64ABIBuiltinVaList;
2943  }
2944
2945  int getEHDataRegisterNumber(unsigned RegNo) const {
2946    if (RegNo == 0) return 0;
2947    if (RegNo == 1) return 1;
2948    return -1;
2949  }
2950
2951  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2952    return (CC == CC_Default ||
2953            CC == CC_C ||
2954            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2955  }
2956
2957  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2958    return CC_C;
2959  }
2960
2961};
2962} // end anonymous namespace
2963
2964namespace {
2965// x86-64 Windows target
2966class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
2967public:
2968  WindowsX86_64TargetInfo(const std::string& triple)
2969    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
2970    TLSSupported = false;
2971    WCharType = UnsignedShort;
2972    LongWidth = LongAlign = 32;
2973    DoubleAlign = LongLongAlign = 64;
2974    IntMaxType = SignedLongLong;
2975    UIntMaxType = UnsignedLongLong;
2976    Int64Type = SignedLongLong;
2977    SizeType = UnsignedLongLong;
2978    PtrDiffType = SignedLongLong;
2979    IntPtrType = SignedLongLong;
2980    this->UserLabelPrefix = "";
2981  }
2982  virtual void getTargetDefines(const LangOptions &Opts,
2983                                MacroBuilder &Builder) const {
2984    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
2985    Builder.defineMacro("_WIN64");
2986  }
2987  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2988    return TargetInfo::CharPtrBuiltinVaList;
2989  }
2990};
2991} // end anonymous namespace
2992
2993namespace {
2994// x86-64 Windows Visual Studio target
2995class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
2996public:
2997  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
2998    : WindowsX86_64TargetInfo(triple) {
2999    LongDoubleWidth = LongDoubleAlign = 64;
3000    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3001  }
3002  virtual void getTargetDefines(const LangOptions &Opts,
3003                                MacroBuilder &Builder) const {
3004    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3005    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3006    Builder.defineMacro("_M_X64");
3007    Builder.defineMacro("_M_AMD64");
3008  }
3009};
3010} // end anonymous namespace
3011
3012namespace {
3013// x86-64 MinGW target
3014class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3015public:
3016  MinGWX86_64TargetInfo(const std::string& triple)
3017    : WindowsX86_64TargetInfo(triple) {
3018  }
3019  virtual void getTargetDefines(const LangOptions &Opts,
3020                                MacroBuilder &Builder) const {
3021    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3022    DefineStd(Builder, "WIN64", Opts);
3023    Builder.defineMacro("__MSVCRT__");
3024    Builder.defineMacro("__MINGW32__");
3025    Builder.defineMacro("__MINGW64__");
3026
3027    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3028    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3029    if (Opts.MicrosoftExt)
3030      // Provide "as-is" __declspec.
3031      Builder.defineMacro("__declspec", "__declspec");
3032    else
3033      // Provide alias of __attribute__ like mingw32-gcc.
3034      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3035  }
3036};
3037} // end anonymous namespace
3038
3039namespace {
3040class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3041public:
3042  DarwinX86_64TargetInfo(const std::string& triple)
3043      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3044    Int64Type = SignedLongLong;
3045    MaxVectorAlign = 256;
3046  }
3047};
3048} // end anonymous namespace
3049
3050namespace {
3051class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3052public:
3053  OpenBSDX86_64TargetInfo(const std::string& triple)
3054      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3055    IntMaxType = SignedLongLong;
3056    UIntMaxType = UnsignedLongLong;
3057    Int64Type = SignedLongLong;
3058  }
3059};
3060} // end anonymous namespace
3061
3062namespace {
3063class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3064public:
3065  BitrigX86_64TargetInfo(const std::string& triple)
3066      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3067     IntMaxType = SignedLongLong;
3068     UIntMaxType = UnsignedLongLong;
3069     Int64Type = SignedLongLong;
3070  }
3071};
3072}
3073
3074namespace {
3075class AArch64TargetInfo : public TargetInfo {
3076  static const char * const GCCRegNames[];
3077  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3078public:
3079  AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3080    BigEndian = false;
3081    LongWidth = LongAlign = 64;
3082    LongDoubleWidth = LongDoubleAlign = 128;
3083    PointerWidth = PointerAlign = 64;
3084    SuitableAlign = 128;
3085    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3086                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3087                        "f128:128:128-n32:64-S128";
3088
3089    WCharType = UnsignedInt;
3090    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3091
3092    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3093  }
3094  virtual void getTargetDefines(const LangOptions &Opts,
3095                                MacroBuilder &Builder) const {
3096    // GCC defines theses currently
3097    Builder.defineMacro("__aarch64__");
3098    Builder.defineMacro("__AARCH64EL__");
3099
3100    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3101
3102    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3103    // which was intended to be compatible with a 64-bit implementation. They
3104    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3105    // instances are: __AARCH_ISA_A32, __AARCH_ISA_T32, __ARCH_PCS.
3106    Builder.defineMacro("__AARCH_ACLE",    "101");
3107    Builder.defineMacro("__AARCH",         "8");
3108    Builder.defineMacro("__AARCH_PROFILE", "'A'");
3109
3110    Builder.defineMacro("__AARCH_FEATURE_UNALIGNED");
3111    Builder.defineMacro("__AARCH_FEATURE_CLZ");
3112    Builder.defineMacro("__AARCH_FEATURE_FMA");
3113
3114    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3115    // 128-bit LDXP present, at which point this becomes 0x1f.
3116    Builder.defineMacro("__AARCH_FEATURE_LDREX", "0xf");
3117
3118    // 0xe implies support for half, single and double precision operations.
3119    Builder.defineMacro("__AARCH_FP", "0xe");
3120
3121    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3122    // may choose __AARCH_FP16_FORMAT_ALTERNATIVE.
3123    Builder.defineMacro("__AARCH_FP16_FORMAT_IEEE");
3124
3125    if (Opts.FastMath || Opts.FiniteMathOnly)
3126      Builder.defineMacro("__AARCH_FP_FAST");
3127
3128    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3129      Builder.defineMacro("__AARCH_FP_FENV_ROUNDING");
3130
3131    Builder.defineMacro("__AARCH_SIZEOF_WCHAR_T",
3132                        Opts.ShortWChar ? "2" : "4");
3133
3134    Builder.defineMacro("__AARCH_SIZEOF_MINIMAL_ENUM",
3135                        Opts.ShortEnums ? "1" : "4");
3136
3137    if (BigEndian)
3138      Builder.defineMacro("__AARCH_BIG_ENDIAN");
3139  }
3140  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3141                                 unsigned &NumRecords) const {
3142    Records = 0;
3143    NumRecords = 0;
3144  }
3145  virtual bool hasFeature(StringRef Feature) const {
3146    return Feature == "aarch64";
3147  }
3148  virtual void getGCCRegNames(const char * const *&Names,
3149                              unsigned &NumNames) const;
3150  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3151                                unsigned &NumAliases) const;
3152
3153  virtual bool isCLZForZeroUndef() const { return false; }
3154
3155  virtual bool validateAsmConstraint(const char *&Name,
3156                                     TargetInfo::ConstraintInfo &Info) const {
3157    switch (*Name) {
3158    default: return false;
3159    case 'w': // An FP/SIMD vector register
3160      Info.setAllowsRegister();
3161      return true;
3162    case 'I': // Constant that can be used with an ADD instruction
3163    case 'J': // Constant that can be used with a SUB instruction
3164    case 'K': // Constant that can be used with a 32-bit logical instruction
3165    case 'L': // Constant that can be used with a 64-bit logical instruction
3166    case 'M': // Constant that can be used as a 32-bit MOV immediate
3167    case 'N': // Constant that can be used as a 64-bit MOV immediate
3168    case 'Y': // Floating point constant zero
3169    case 'Z': // Integer constant zero
3170      return true;
3171    case 'Q': // A memory reference with base register and no offset
3172      Info.setAllowsMemory();
3173      return true;
3174    case 'S': // A symbolic address
3175      Info.setAllowsRegister();
3176      return true;
3177    case 'U':
3178      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3179      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3180      // Usa: An absolute symbolic address
3181      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3182      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3183    }
3184  }
3185
3186  virtual const char *getClobbers() const {
3187    // There are no AArch64 clobbers shared by all asm statements.
3188    return "";
3189  }
3190
3191  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3192    return TargetInfo::AArch64ABIBuiltinVaList;
3193  }
3194};
3195
3196const char * const AArch64TargetInfo::GCCRegNames[] = {
3197  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3198  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3199  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3200  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3201
3202  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3203  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3204  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3205  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3206
3207  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3208  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3209  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3210  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3211
3212  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3213  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3214  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3215  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3216
3217  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3218  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3219  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3220  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3221
3222  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3223  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3224  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3225  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3226
3227  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3228  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3229  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3230  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3231};
3232
3233void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3234                                       unsigned &NumNames) const {
3235  Names = GCCRegNames;
3236  NumNames = llvm::array_lengthof(GCCRegNames);
3237}
3238
3239const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3240  { { "x16" }, "ip0"},
3241  { { "x17" }, "ip1"},
3242  { { "x29" }, "fp" },
3243  { { "x30" }, "lr" }
3244};
3245
3246void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3247                                         unsigned &NumAliases) const {
3248  Aliases = GCCRegAliases;
3249  NumAliases = llvm::array_lengthof(GCCRegAliases);
3250
3251}
3252} // end anonymous namespace
3253
3254namespace {
3255class ARMTargetInfo : public TargetInfo {
3256  // Possible FPU choices.
3257  enum FPUMode {
3258    VFP2FPU = (1 << 0),
3259    VFP3FPU = (1 << 1),
3260    VFP4FPU = (1 << 2),
3261    NeonFPU = (1 << 3)
3262  };
3263
3264  static bool FPUModeIsVFP(FPUMode Mode) {
3265    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3266  }
3267
3268  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3269  static const char * const GCCRegNames[];
3270
3271  std::string ABI, CPU;
3272
3273  unsigned FPU : 4;
3274
3275  unsigned IsAAPCS : 1;
3276  unsigned IsThumb : 1;
3277
3278  // Initialized via features.
3279  unsigned SoftFloat : 1;
3280  unsigned SoftFloatABI : 1;
3281
3282  static const Builtin::Info BuiltinInfo[];
3283
3284public:
3285  ARMTargetInfo(const std::string &TripleStr)
3286    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3287  {
3288    BigEndian = false;
3289    SizeType = UnsignedInt;
3290    PtrDiffType = SignedInt;
3291    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3292    WCharType = UnsignedInt;
3293
3294    // {} in inline assembly are neon specifiers, not assembly variant
3295    // specifiers.
3296    NoAsmVariants = true;
3297
3298    // FIXME: Should we just treat this as a feature?
3299    IsThumb = getTriple().getArchName().startswith("thumb");
3300    if (IsThumb) {
3301      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3302      // so set preferred for small types to 32.
3303      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3304                           "i64:64:64-f32:32:32-f64:64:64-"
3305                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3306    } else {
3307      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3308                           "i64:64:64-f32:32:32-f64:64:64-"
3309                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3310    }
3311
3312    // ARM targets default to using the ARM C++ ABI.
3313    TheCXXABI.set(TargetCXXABI::GenericARM);
3314
3315    // ARM has atomics up to 8 bytes
3316    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
3317    MaxAtomicPromoteWidth = 64;
3318
3319    // Do force alignment of members that follow zero length bitfields.  If
3320    // the alignment of the zero-length bitfield is greater than the member
3321    // that follows it, `bar', `bar' will be aligned as the  type of the
3322    // zero length bitfield.
3323    UseZeroLengthBitfieldAlignment = true;
3324  }
3325  virtual const char *getABI() const { return ABI.c_str(); }
3326  virtual bool setABI(const std::string &Name) {
3327    ABI = Name;
3328
3329    // The defaults (above) are for AAPCS, check if we need to change them.
3330    //
3331    // FIXME: We need support for -meabi... we could just mangle it into the
3332    // name.
3333    if (Name == "apcs-gnu") {
3334      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3335      // size_t is unsigned int on FreeBSD.
3336      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3337        SizeType = UnsignedLong;
3338
3339      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3340      WCharType = SignedInt;
3341
3342      // Do not respect the alignment of bit-field types when laying out
3343      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3344      UseBitFieldTypeAlignment = false;
3345
3346      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3347      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3348      /// gcc.
3349      ZeroLengthBitfieldBoundary = 32;
3350
3351      IsAAPCS = false;
3352
3353      if (IsThumb) {
3354        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3355        // so set preferred for small types to 32.
3356        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3357                             "i64:32:64-f32:32:32-f64:32:64-"
3358                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3359      } else {
3360        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3361                             "i64:32:64-f32:32:32-f64:32:64-"
3362                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3363      }
3364
3365      // FIXME: Override "preferred align" for double and long long.
3366    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3367      IsAAPCS = true;
3368      // FIXME: Enumerated types are variable width in straight AAPCS.
3369    } else if (Name == "aapcs-linux") {
3370      IsAAPCS = true;
3371    } else
3372      return false;
3373
3374    return true;
3375  }
3376
3377  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3378    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3379      Features["vfp2"] = true;
3380    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3381             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3382      Features["neon"] = true;
3383    else if (CPU == "swift") {
3384      Features["vfp4"] = true;
3385      Features["neon"] = true;
3386    }
3387  }
3388
3389  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3390                                 StringRef Name,
3391                                 bool Enabled) const {
3392    if (Name == "soft-float" || Name == "soft-float-abi" ||
3393        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3394        Name == "d16" || Name == "neonfp") {
3395      Features[Name] = Enabled;
3396    } else
3397      return false;
3398
3399    return true;
3400  }
3401
3402  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3403    FPU = 0;
3404    SoftFloat = SoftFloatABI = false;
3405    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3406      if (Features[i] == "+soft-float")
3407        SoftFloat = true;
3408      else if (Features[i] == "+soft-float-abi")
3409        SoftFloatABI = true;
3410      else if (Features[i] == "+vfp2")
3411        FPU |= VFP2FPU;
3412      else if (Features[i] == "+vfp3")
3413        FPU |= VFP3FPU;
3414      else if (Features[i] == "+vfp4")
3415        FPU |= VFP4FPU;
3416      else if (Features[i] == "+neon")
3417        FPU |= NeonFPU;
3418    }
3419
3420    // Remove front-end specific options which the backend handles differently.
3421    std::vector<std::string>::iterator it;
3422    it = std::find(Features.begin(), Features.end(), "+soft-float");
3423    if (it != Features.end())
3424      Features.erase(it);
3425    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3426    if (it != Features.end())
3427      Features.erase(it);
3428  }
3429
3430  virtual bool hasFeature(StringRef Feature) const {
3431    return llvm::StringSwitch<bool>(Feature)
3432        .Case("arm", true)
3433        .Case("softfloat", SoftFloat)
3434        .Case("thumb", IsThumb)
3435        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3436              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3437        .Default(false);
3438  }
3439  // FIXME: Should we actually have some table instead of these switches?
3440  static const char *getCPUDefineSuffix(StringRef Name) {
3441    return llvm::StringSwitch<const char*>(Name)
3442      .Cases("arm8", "arm810", "4")
3443      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3444      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3445      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3446      .Case("ep9312", "4T")
3447      .Cases("arm10tdmi", "arm1020t", "5T")
3448      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3449      .Case("arm926ej-s", "5TEJ")
3450      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3451      .Cases("xscale", "iwmmxt", "5TE")
3452      .Case("arm1136j-s", "6J")
3453      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3454      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3455      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3456      .Cases("cortex-a5", "cortex-a8", "cortex-a9", "cortex-a15", "7A")
3457      .Case("cortex-r5", "7R")
3458      .Case("cortex-a9-mp", "7F")
3459      .Case("swift", "7S")
3460      .Cases("cortex-m3", "cortex-m4", "7M")
3461      .Case("cortex-m0", "6M")
3462      .Default(0);
3463  }
3464  static const char *getCPUProfile(StringRef Name) {
3465    return llvm::StringSwitch<const char*>(Name)
3466      .Cases("cortex-a8", "cortex-a9", "A")
3467      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3468      .Case("cortex-r5", "R")
3469      .Default("");
3470  }
3471  virtual bool setCPU(const std::string &Name) {
3472    if (!getCPUDefineSuffix(Name))
3473      return false;
3474
3475    CPU = Name;
3476    return true;
3477  }
3478  virtual void getTargetDefines(const LangOptions &Opts,
3479                                MacroBuilder &Builder) const {
3480    // Target identification.
3481    Builder.defineMacro("__arm");
3482    Builder.defineMacro("__arm__");
3483
3484    // Target properties.
3485    Builder.defineMacro("__ARMEL__");
3486    Builder.defineMacro("__LITTLE_ENDIAN__");
3487    Builder.defineMacro("__REGISTER_PREFIX__", "");
3488
3489    StringRef CPUArch = getCPUDefineSuffix(CPU);
3490    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3491    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3492    StringRef CPUProfile = getCPUProfile(CPU);
3493    if (!CPUProfile.empty())
3494      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3495
3496    // Subtarget options.
3497
3498    // FIXME: It's more complicated than this and we don't really support
3499    // interworking.
3500    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3501      Builder.defineMacro("__THUMB_INTERWORK__");
3502
3503    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3504      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3505      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3506        Builder.defineMacro("__ARM_EABI__");
3507      Builder.defineMacro("__ARM_PCS", "1");
3508
3509      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3510        Builder.defineMacro("__ARM_PCS_VFP", "1");
3511    }
3512
3513    if (SoftFloat)
3514      Builder.defineMacro("__SOFTFP__");
3515
3516    if (CPU == "xscale")
3517      Builder.defineMacro("__XSCALE__");
3518
3519    bool IsARMv7 = CPUArch.startswith("7");
3520    if (IsThumb) {
3521      Builder.defineMacro("__THUMBEL__");
3522      Builder.defineMacro("__thumb__");
3523      if (CPUArch == "6T2" || IsARMv7)
3524        Builder.defineMacro("__thumb2__");
3525    }
3526
3527    // Note, this is always on in gcc, even though it doesn't make sense.
3528    Builder.defineMacro("__APCS_32__");
3529
3530    if (FPUModeIsVFP((FPUMode) FPU)) {
3531      Builder.defineMacro("__VFP_FP__");
3532      if (FPU & VFP2FPU)
3533        Builder.defineMacro("__ARM_VFPV2__");
3534      if (FPU & VFP3FPU)
3535        Builder.defineMacro("__ARM_VFPV3__");
3536      if (FPU & VFP4FPU)
3537        Builder.defineMacro("__ARM_VFPV4__");
3538    }
3539
3540    // This only gets set when Neon instructions are actually available, unlike
3541    // the VFP define, hence the soft float and arch check. This is subtly
3542    // different from gcc, we follow the intent which was that it should be set
3543    // when Neon instructions are actually available.
3544    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3545      Builder.defineMacro("__ARM_NEON__");
3546  }
3547  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3548                                 unsigned &NumRecords) const {
3549    Records = BuiltinInfo;
3550    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3551  }
3552  virtual bool isCLZForZeroUndef() const { return false; }
3553  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3554    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3555  }
3556  virtual void getGCCRegNames(const char * const *&Names,
3557                              unsigned &NumNames) const;
3558  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3559                                unsigned &NumAliases) const;
3560  virtual bool validateAsmConstraint(const char *&Name,
3561                                     TargetInfo::ConstraintInfo &Info) const {
3562    switch (*Name) {
3563    default: break;
3564    case 'l': // r0-r7
3565    case 'h': // r8-r15
3566    case 'w': // VFP Floating point register single precision
3567    case 'P': // VFP Floating point register double precision
3568      Info.setAllowsRegister();
3569      return true;
3570    case 'Q': // A memory address that is a single base register.
3571      Info.setAllowsMemory();
3572      return true;
3573    case 'U': // a memory reference...
3574      switch (Name[1]) {
3575      case 'q': // ...ARMV4 ldrsb
3576      case 'v': // ...VFP load/store (reg+constant offset)
3577      case 'y': // ...iWMMXt load/store
3578      case 't': // address valid for load/store opaque types wider
3579                // than 128-bits
3580      case 'n': // valid address for Neon doubleword vector load/store
3581      case 'm': // valid address for Neon element and structure load/store
3582      case 's': // valid address for non-offset loads/stores of quad-word
3583                // values in four ARM registers
3584        Info.setAllowsMemory();
3585        Name++;
3586        return true;
3587      }
3588    }
3589    return false;
3590  }
3591  virtual std::string convertConstraint(const char *&Constraint) const {
3592    std::string R;
3593    switch (*Constraint) {
3594    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3595      R = std::string("^") + std::string(Constraint, 2);
3596      Constraint++;
3597      break;
3598    case 'p': // 'p' should be translated to 'r' by default.
3599      R = std::string("r");
3600      break;
3601    default:
3602      return std::string(1, *Constraint);
3603    }
3604    return R;
3605  }
3606  virtual bool validateConstraintModifier(StringRef Constraint,
3607                                          const char Modifier,
3608                                          unsigned Size) const {
3609    bool isOutput = (Constraint[0] == '=');
3610    bool isInOut = (Constraint[0] == '+');
3611
3612    // Strip off constraint modifiers.
3613    while (Constraint[0] == '=' ||
3614           Constraint[0] == '+' ||
3615           Constraint[0] == '&')
3616      Constraint = Constraint.substr(1);
3617
3618    switch (Constraint[0]) {
3619    default: break;
3620    case 'r': {
3621      switch (Modifier) {
3622      default:
3623        return isInOut || (isOutput && Size >= 32) ||
3624          (!isOutput && !isInOut && Size <= 32);
3625      case 'q':
3626        // A register of size 32 cannot fit a vector type.
3627        return false;
3628      }
3629    }
3630    }
3631
3632    return true;
3633  }
3634  virtual const char *getClobbers() const {
3635    // FIXME: Is this really right?
3636    return "";
3637  }
3638
3639  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3640    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3641  }
3642};
3643
3644const char * const ARMTargetInfo::GCCRegNames[] = {
3645  // Integer registers
3646  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3647  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3648
3649  // Float registers
3650  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3651  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3652  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3653  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3654
3655  // Double registers
3656  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3657  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3658  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3659  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3660
3661  // Quad registers
3662  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3663  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3664};
3665
3666void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3667                                   unsigned &NumNames) const {
3668  Names = GCCRegNames;
3669  NumNames = llvm::array_lengthof(GCCRegNames);
3670}
3671
3672const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3673  { { "a1" }, "r0" },
3674  { { "a2" }, "r1" },
3675  { { "a3" }, "r2" },
3676  { { "a4" }, "r3" },
3677  { { "v1" }, "r4" },
3678  { { "v2" }, "r5" },
3679  { { "v3" }, "r6" },
3680  { { "v4" }, "r7" },
3681  { { "v5" }, "r8" },
3682  { { "v6", "rfp" }, "r9" },
3683  { { "sl" }, "r10" },
3684  { { "fp" }, "r11" },
3685  { { "ip" }, "r12" },
3686  { { "r13" }, "sp" },
3687  { { "r14" }, "lr" },
3688  { { "r15" }, "pc" },
3689  // The S, D and Q registers overlap, but aren't really aliases; we
3690  // don't want to substitute one of these for a different-sized one.
3691};
3692
3693void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3694                                       unsigned &NumAliases) const {
3695  Aliases = GCCRegAliases;
3696  NumAliases = llvm::array_lengthof(GCCRegAliases);
3697}
3698
3699const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3700#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3701#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3702                                              ALL_LANGUAGES },
3703#include "clang/Basic/BuiltinsARM.def"
3704};
3705} // end anonymous namespace.
3706
3707namespace {
3708class DarwinARMTargetInfo :
3709  public DarwinTargetInfo<ARMTargetInfo> {
3710protected:
3711  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3712                            MacroBuilder &Builder) const {
3713    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3714  }
3715
3716public:
3717  DarwinARMTargetInfo(const std::string& triple)
3718    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3719    HasAlignMac68kSupport = true;
3720    // iOS always has 64-bit atomic instructions.
3721    // FIXME: This should be based off of the target features in ARMTargetInfo.
3722    MaxAtomicInlineWidth = 64;
3723
3724    // Darwin on iOS uses a variant of the ARM C++ ABI.
3725    TheCXXABI.set(TargetCXXABI::iOS);
3726  }
3727};
3728} // end anonymous namespace.
3729
3730
3731namespace {
3732// Hexagon abstract base class
3733class HexagonTargetInfo : public TargetInfo {
3734  static const Builtin::Info BuiltinInfo[];
3735  static const char * const GCCRegNames[];
3736  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3737  std::string CPU;
3738public:
3739  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3740    BigEndian = false;
3741    DescriptionString = ("e-p:32:32:32-"
3742                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
3743                         "f64:64:64-f32:32:32-a0:0-n32");
3744
3745    // {} in inline assembly are packet specifiers, not assembly variant
3746    // specifiers.
3747    NoAsmVariants = true;
3748  }
3749
3750  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3751                                 unsigned &NumRecords) const {
3752    Records = BuiltinInfo;
3753    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3754  }
3755
3756  virtual bool validateAsmConstraint(const char *&Name,
3757                                     TargetInfo::ConstraintInfo &Info) const {
3758    return true;
3759  }
3760
3761  virtual void getTargetDefines(const LangOptions &Opts,
3762                                MacroBuilder &Builder) const;
3763
3764  virtual bool hasFeature(StringRef Feature) const {
3765    return Feature == "hexagon";
3766  }
3767
3768  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3769    return TargetInfo::CharPtrBuiltinVaList;
3770  }
3771  virtual void getGCCRegNames(const char * const *&Names,
3772                              unsigned &NumNames) const;
3773  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3774                                unsigned &NumAliases) const;
3775  virtual const char *getClobbers() const {
3776    return "";
3777  }
3778
3779  static const char *getHexagonCPUSuffix(StringRef Name) {
3780    return llvm::StringSwitch<const char*>(Name)
3781      .Case("hexagonv2", "2")
3782      .Case("hexagonv3", "3")
3783      .Case("hexagonv4", "4")
3784      .Case("hexagonv5", "5")
3785      .Default(0);
3786  }
3787
3788  virtual bool setCPU(const std::string &Name) {
3789    if (!getHexagonCPUSuffix(Name))
3790      return false;
3791
3792    CPU = Name;
3793    return true;
3794  }
3795};
3796
3797void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
3798                                MacroBuilder &Builder) const {
3799  Builder.defineMacro("qdsp6");
3800  Builder.defineMacro("__qdsp6", "1");
3801  Builder.defineMacro("__qdsp6__", "1");
3802
3803  Builder.defineMacro("hexagon");
3804  Builder.defineMacro("__hexagon", "1");
3805  Builder.defineMacro("__hexagon__", "1");
3806
3807  if(CPU == "hexagonv1") {
3808    Builder.defineMacro("__HEXAGON_V1__");
3809    Builder.defineMacro("__HEXAGON_ARCH__", "1");
3810    if(Opts.HexagonQdsp6Compat) {
3811      Builder.defineMacro("__QDSP6_V1__");
3812      Builder.defineMacro("__QDSP6_ARCH__", "1");
3813    }
3814  }
3815  else if(CPU == "hexagonv2") {
3816    Builder.defineMacro("__HEXAGON_V2__");
3817    Builder.defineMacro("__HEXAGON_ARCH__", "2");
3818    if(Opts.HexagonQdsp6Compat) {
3819      Builder.defineMacro("__QDSP6_V2__");
3820      Builder.defineMacro("__QDSP6_ARCH__", "2");
3821    }
3822  }
3823  else if(CPU == "hexagonv3") {
3824    Builder.defineMacro("__HEXAGON_V3__");
3825    Builder.defineMacro("__HEXAGON_ARCH__", "3");
3826    if(Opts.HexagonQdsp6Compat) {
3827      Builder.defineMacro("__QDSP6_V3__");
3828      Builder.defineMacro("__QDSP6_ARCH__", "3");
3829    }
3830  }
3831  else if(CPU == "hexagonv4") {
3832    Builder.defineMacro("__HEXAGON_V4__");
3833    Builder.defineMacro("__HEXAGON_ARCH__", "4");
3834    if(Opts.HexagonQdsp6Compat) {
3835      Builder.defineMacro("__QDSP6_V4__");
3836      Builder.defineMacro("__QDSP6_ARCH__", "4");
3837    }
3838  }
3839  else if(CPU == "hexagonv5") {
3840    Builder.defineMacro("__HEXAGON_V5__");
3841    Builder.defineMacro("__HEXAGON_ARCH__", "5");
3842    if(Opts.HexagonQdsp6Compat) {
3843      Builder.defineMacro("__QDSP6_V5__");
3844      Builder.defineMacro("__QDSP6_ARCH__", "5");
3845    }
3846  }
3847}
3848
3849const char * const HexagonTargetInfo::GCCRegNames[] = {
3850  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3851  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3852  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3853  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
3854  "p0", "p1", "p2", "p3",
3855  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
3856};
3857
3858void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
3859                                   unsigned &NumNames) const {
3860  Names = GCCRegNames;
3861  NumNames = llvm::array_lengthof(GCCRegNames);
3862}
3863
3864
3865const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
3866  { { "sp" }, "r29" },
3867  { { "fp" }, "r30" },
3868  { { "lr" }, "r31" },
3869 };
3870
3871void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3872                                     unsigned &NumAliases) const {
3873  Aliases = GCCRegAliases;
3874  NumAliases = llvm::array_lengthof(GCCRegAliases);
3875}
3876
3877
3878const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
3879#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3880#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3881                                              ALL_LANGUAGES },
3882#include "clang/Basic/BuiltinsHexagon.def"
3883};
3884}
3885
3886
3887namespace {
3888class SparcV8TargetInfo : public TargetInfo {
3889  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3890  static const char * const GCCRegNames[];
3891  bool SoftFloat;
3892public:
3893  SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
3894    // FIXME: Support Sparc quad-precision long double?
3895    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3896                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
3897  }
3898  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3899                                 StringRef Name,
3900                                 bool Enabled) const {
3901    if (Name == "soft-float")
3902      Features[Name] = Enabled;
3903    else
3904      return false;
3905
3906    return true;
3907  }
3908  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3909    SoftFloat = false;
3910    for (unsigned i = 0, e = Features.size(); i != e; ++i)
3911      if (Features[i] == "+soft-float")
3912        SoftFloat = true;
3913  }
3914  virtual void getTargetDefines(const LangOptions &Opts,
3915                                MacroBuilder &Builder) const {
3916    DefineStd(Builder, "sparc", Opts);
3917    Builder.defineMacro("__sparcv8");
3918    Builder.defineMacro("__REGISTER_PREFIX__", "");
3919
3920    if (SoftFloat)
3921      Builder.defineMacro("SOFT_FLOAT", "1");
3922  }
3923
3924  virtual bool hasFeature(StringRef Feature) const {
3925    return llvm::StringSwitch<bool>(Feature)
3926             .Case("softfloat", SoftFloat)
3927             .Case("sparc", true)
3928             .Default(false);
3929  }
3930
3931  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3932                                 unsigned &NumRecords) const {
3933    // FIXME: Implement!
3934  }
3935  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3936    return TargetInfo::VoidPtrBuiltinVaList;
3937  }
3938  virtual void getGCCRegNames(const char * const *&Names,
3939                              unsigned &NumNames) const;
3940  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3941                                unsigned &NumAliases) const;
3942  virtual bool validateAsmConstraint(const char *&Name,
3943                                     TargetInfo::ConstraintInfo &info) const {
3944    // FIXME: Implement!
3945    return false;
3946  }
3947  virtual const char *getClobbers() const {
3948    // FIXME: Implement!
3949    return "";
3950  }
3951};
3952
3953const char * const SparcV8TargetInfo::GCCRegNames[] = {
3954  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3955  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3956  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3957  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3958};
3959
3960void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
3961                                       unsigned &NumNames) const {
3962  Names = GCCRegNames;
3963  NumNames = llvm::array_lengthof(GCCRegNames);
3964}
3965
3966const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
3967  { { "g0" }, "r0" },
3968  { { "g1" }, "r1" },
3969  { { "g2" }, "r2" },
3970  { { "g3" }, "r3" },
3971  { { "g4" }, "r4" },
3972  { { "g5" }, "r5" },
3973  { { "g6" }, "r6" },
3974  { { "g7" }, "r7" },
3975  { { "o0" }, "r8" },
3976  { { "o1" }, "r9" },
3977  { { "o2" }, "r10" },
3978  { { "o3" }, "r11" },
3979  { { "o4" }, "r12" },
3980  { { "o5" }, "r13" },
3981  { { "o6", "sp" }, "r14" },
3982  { { "o7" }, "r15" },
3983  { { "l0" }, "r16" },
3984  { { "l1" }, "r17" },
3985  { { "l2" }, "r18" },
3986  { { "l3" }, "r19" },
3987  { { "l4" }, "r20" },
3988  { { "l5" }, "r21" },
3989  { { "l6" }, "r22" },
3990  { { "l7" }, "r23" },
3991  { { "i0" }, "r24" },
3992  { { "i1" }, "r25" },
3993  { { "i2" }, "r26" },
3994  { { "i3" }, "r27" },
3995  { { "i4" }, "r28" },
3996  { { "i5" }, "r29" },
3997  { { "i6", "fp" }, "r30" },
3998  { { "i7" }, "r31" },
3999};
4000
4001void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4002                                         unsigned &NumAliases) const {
4003  Aliases = GCCRegAliases;
4004  NumAliases = llvm::array_lengthof(GCCRegAliases);
4005}
4006} // end anonymous namespace.
4007
4008namespace {
4009class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4010public:
4011  AuroraUXSparcV8TargetInfo(const std::string& triple) :
4012      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4013    SizeType = UnsignedInt;
4014    PtrDiffType = SignedInt;
4015  }
4016};
4017class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4018public:
4019  SolarisSparcV8TargetInfo(const std::string& triple) :
4020      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4021    SizeType = UnsignedInt;
4022    PtrDiffType = SignedInt;
4023  }
4024};
4025} // end anonymous namespace.
4026
4027namespace {
4028  class MSP430TargetInfo : public TargetInfo {
4029    static const char * const GCCRegNames[];
4030  public:
4031    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4032      BigEndian = false;
4033      TLSSupported = false;
4034      IntWidth = 16; IntAlign = 16;
4035      LongWidth = 32; LongLongWidth = 64;
4036      LongAlign = LongLongAlign = 16;
4037      PointerWidth = 16; PointerAlign = 16;
4038      SuitableAlign = 16;
4039      SizeType = UnsignedInt;
4040      IntMaxType = SignedLong;
4041      UIntMaxType = UnsignedLong;
4042      IntPtrType = SignedShort;
4043      PtrDiffType = SignedInt;
4044      SigAtomicType = SignedLong;
4045      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4046   }
4047    virtual void getTargetDefines(const LangOptions &Opts,
4048                                  MacroBuilder &Builder) const {
4049      Builder.defineMacro("MSP430");
4050      Builder.defineMacro("__MSP430__");
4051      // FIXME: defines for different 'flavours' of MCU
4052    }
4053    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4054                                   unsigned &NumRecords) const {
4055     // FIXME: Implement.
4056      Records = 0;
4057      NumRecords = 0;
4058    }
4059    virtual bool hasFeature(StringRef Feature) const {
4060      return Feature == "msp430";
4061    }
4062    virtual void getGCCRegNames(const char * const *&Names,
4063                                unsigned &NumNames) const;
4064    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4065                                  unsigned &NumAliases) const {
4066      // No aliases.
4067      Aliases = 0;
4068      NumAliases = 0;
4069    }
4070    virtual bool validateAsmConstraint(const char *&Name,
4071                                       TargetInfo::ConstraintInfo &info) const {
4072      // No target constraints for now.
4073      return false;
4074    }
4075    virtual const char *getClobbers() const {
4076      // FIXME: Is this really right?
4077      return "";
4078    }
4079    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4080      // FIXME: implement
4081      return TargetInfo::CharPtrBuiltinVaList;
4082   }
4083  };
4084
4085  const char * const MSP430TargetInfo::GCCRegNames[] = {
4086    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4087    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4088  };
4089
4090  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4091                                        unsigned &NumNames) const {
4092    Names = GCCRegNames;
4093    NumNames = llvm::array_lengthof(GCCRegNames);
4094  }
4095}
4096
4097namespace {
4098
4099  // LLVM and Clang cannot be used directly to output native binaries for
4100  // target, but is used to compile C code to llvm bitcode with correct
4101  // type and alignment information.
4102  //
4103  // TCE uses the llvm bitcode as input and uses it for generating customized
4104  // target processor and program binary. TCE co-design environment is
4105  // publicly available in http://tce.cs.tut.fi
4106
4107  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4108      3, // opencl_global
4109      4, // opencl_local
4110      5, // opencl_constant
4111      0, // cuda_device
4112      0, // cuda_constant
4113      0  // cuda_shared
4114  };
4115
4116  class TCETargetInfo : public TargetInfo{
4117  public:
4118    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4119      TLSSupported = false;
4120      IntWidth = 32;
4121      LongWidth = LongLongWidth = 32;
4122      PointerWidth = 32;
4123      IntAlign = 32;
4124      LongAlign = LongLongAlign = 32;
4125      PointerAlign = 32;
4126      SuitableAlign = 32;
4127      SizeType = UnsignedInt;
4128      IntMaxType = SignedLong;
4129      UIntMaxType = UnsignedLong;
4130      IntPtrType = SignedInt;
4131      PtrDiffType = SignedInt;
4132      FloatWidth = 32;
4133      FloatAlign = 32;
4134      DoubleWidth = 32;
4135      DoubleAlign = 32;
4136      LongDoubleWidth = 32;
4137      LongDoubleAlign = 32;
4138      FloatFormat = &llvm::APFloat::IEEEsingle;
4139      DoubleFormat = &llvm::APFloat::IEEEsingle;
4140      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4141      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4142                          "i16:16:32-i32:32:32-i64:32:32-"
4143                          "f32:32:32-f64:32:32-v64:32:32-"
4144                          "v128:32:32-a0:0:32-n32";
4145      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4146    }
4147
4148    virtual void getTargetDefines(const LangOptions &Opts,
4149                                  MacroBuilder &Builder) const {
4150      DefineStd(Builder, "tce", Opts);
4151      Builder.defineMacro("__TCE__");
4152      Builder.defineMacro("__TCE_V1__");
4153    }
4154    virtual bool hasFeature(StringRef Feature) const {
4155      return Feature == "tce";
4156    }
4157
4158    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4159                                   unsigned &NumRecords) const {}
4160    virtual const char *getClobbers() const {
4161      return "";
4162    }
4163    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4164      return TargetInfo::VoidPtrBuiltinVaList;
4165    }
4166    virtual void getGCCRegNames(const char * const *&Names,
4167                                unsigned &NumNames) const {}
4168    virtual bool validateAsmConstraint(const char *&Name,
4169                                       TargetInfo::ConstraintInfo &info) const {
4170      return true;
4171    }
4172    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4173                                  unsigned &NumAliases) const {}
4174  };
4175}
4176
4177namespace {
4178class MipsTargetInfoBase : public TargetInfo {
4179  static const Builtin::Info BuiltinInfo[];
4180  std::string CPU;
4181  bool IsMips16;
4182  enum MipsFloatABI {
4183    HardFloat, SingleFloat, SoftFloat
4184  } FloatABI;
4185  enum DspRevEnum {
4186    NoDSP, DSP1, DSP2
4187  } DspRev;
4188
4189protected:
4190  std::string ABI;
4191
4192public:
4193  MipsTargetInfoBase(const std::string& triple,
4194                     const std::string& ABIStr,
4195                     const std::string& CPUStr)
4196    : TargetInfo(triple),
4197      CPU(CPUStr),
4198      IsMips16(false),
4199      FloatABI(HardFloat),
4200      DspRev(NoDSP),
4201      ABI(ABIStr)
4202  {}
4203
4204  virtual const char *getABI() const { return ABI.c_str(); }
4205  virtual bool setABI(const std::string &Name) = 0;
4206  virtual bool setCPU(const std::string &Name) {
4207    CPU = Name;
4208    return true;
4209  }
4210  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4211    Features[ABI] = true;
4212    Features[CPU] = true;
4213  }
4214
4215  virtual void getTargetDefines(const LangOptions &Opts,
4216                                MacroBuilder &Builder) const {
4217    DefineStd(Builder, "mips", Opts);
4218    Builder.defineMacro("_mips");
4219    Builder.defineMacro("__REGISTER_PREFIX__", "");
4220
4221    switch (FloatABI) {
4222    case HardFloat:
4223      Builder.defineMacro("__mips_hard_float", Twine(1));
4224      break;
4225    case SingleFloat:
4226      Builder.defineMacro("__mips_hard_float", Twine(1));
4227      Builder.defineMacro("__mips_single_float", Twine(1));
4228      break;
4229    case SoftFloat:
4230      Builder.defineMacro("__mips_soft_float", Twine(1));
4231      break;
4232    }
4233
4234    if (IsMips16)
4235      Builder.defineMacro("__mips16", Twine(1));
4236
4237    switch (DspRev) {
4238    default:
4239      break;
4240    case DSP1:
4241      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4242      Builder.defineMacro("__mips_dsp", Twine(1));
4243      break;
4244    case DSP2:
4245      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4246      Builder.defineMacro("__mips_dspr2", Twine(1));
4247      Builder.defineMacro("__mips_dsp", Twine(1));
4248      break;
4249    }
4250
4251    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4252    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4253    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4254
4255    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4256    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4257  }
4258
4259  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4260                                 unsigned &NumRecords) const {
4261    Records = BuiltinInfo;
4262    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4263  }
4264  virtual bool hasFeature(StringRef Feature) const {
4265    return Feature == "mips";
4266  }
4267  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4268    return TargetInfo::VoidPtrBuiltinVaList;
4269  }
4270  virtual void getGCCRegNames(const char * const *&Names,
4271                              unsigned &NumNames) const {
4272    static const char * const GCCRegNames[] = {
4273      // CPU register names
4274      // Must match second column of GCCRegAliases
4275      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4276      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4277      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4278      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4279      // Floating point register names
4280      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4281      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4282      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4283      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4284      // Hi/lo and condition register names
4285      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4286      "$fcc5","$fcc6","$fcc7"
4287    };
4288    Names = GCCRegNames;
4289    NumNames = llvm::array_lengthof(GCCRegNames);
4290  }
4291  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4292                                unsigned &NumAliases) const = 0;
4293  virtual bool validateAsmConstraint(const char *&Name,
4294                                     TargetInfo::ConstraintInfo &Info) const {
4295    switch (*Name) {
4296    default:
4297      return false;
4298
4299    case 'r': // CPU registers.
4300    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4301    case 'y': // Equivalent to "r", backwards compatibility only.
4302    case 'f': // floating-point registers.
4303    case 'c': // $25 for indirect jumps
4304    case 'l': // lo register
4305    case 'x': // hilo register pair
4306      Info.setAllowsRegister();
4307      return true;
4308    }
4309  }
4310
4311  virtual const char *getClobbers() const {
4312    // FIXME: Implement!
4313    return "";
4314  }
4315
4316  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4317                                 StringRef Name,
4318                                 bool Enabled) const {
4319    if (Name == "soft-float" || Name == "single-float" ||
4320        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4321        Name == "mips32" || Name == "mips32r2" ||
4322        Name == "mips64" || Name == "mips64r2" ||
4323        Name == "mips16" || Name == "dsp" || Name == "dspr2") {
4324      Features[Name] = Enabled;
4325      return true;
4326    }
4327    return false;
4328  }
4329
4330  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4331    IsMips16 = false;
4332    FloatABI = HardFloat;
4333    DspRev = NoDSP;
4334
4335    for (std::vector<std::string>::iterator it = Features.begin(),
4336         ie = Features.end(); it != ie; ++it) {
4337      if (*it == "+single-float")
4338        FloatABI = SingleFloat;
4339      else if (*it == "+soft-float")
4340        FloatABI = SoftFloat;
4341      else if (*it == "+mips16")
4342        IsMips16 = true;
4343      else if (*it == "+dsp")
4344        DspRev = std::max(DspRev, DSP1);
4345      else if (*it == "+dspr2")
4346        DspRev = std::max(DspRev, DSP2);
4347    }
4348
4349    // Remove front-end specific option.
4350    std::vector<std::string>::iterator it =
4351      std::find(Features.begin(), Features.end(), "+soft-float");
4352    if (it != Features.end())
4353      Features.erase(it);
4354  }
4355};
4356
4357const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4358#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4359#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4360                                              ALL_LANGUAGES },
4361#include "clang/Basic/BuiltinsMips.def"
4362};
4363
4364class Mips32TargetInfoBase : public MipsTargetInfoBase {
4365public:
4366  Mips32TargetInfoBase(const std::string& triple) :
4367    MipsTargetInfoBase(triple, "o32", "mips32") {
4368    SizeType = UnsignedInt;
4369    PtrDiffType = SignedInt;
4370    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4371  }
4372  virtual bool setABI(const std::string &Name) {
4373    if ((Name == "o32") || (Name == "eabi")) {
4374      ABI = Name;
4375      return true;
4376    } else
4377      return false;
4378  }
4379  virtual void getTargetDefines(const LangOptions &Opts,
4380                                MacroBuilder &Builder) const {
4381    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4382
4383    if (ABI == "o32") {
4384      Builder.defineMacro("__mips_o32");
4385      Builder.defineMacro("_ABIO32", "1");
4386      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4387    }
4388    else if (ABI == "eabi")
4389      Builder.defineMacro("__mips_eabi");
4390    else
4391      llvm_unreachable("Invalid ABI for Mips32.");
4392  }
4393  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4394                                unsigned &NumAliases) const {
4395    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4396      { { "at" },  "$1" },
4397      { { "v0" },  "$2" },
4398      { { "v1" },  "$3" },
4399      { { "a0" },  "$4" },
4400      { { "a1" },  "$5" },
4401      { { "a2" },  "$6" },
4402      { { "a3" },  "$7" },
4403      { { "t0" },  "$8" },
4404      { { "t1" },  "$9" },
4405      { { "t2" }, "$10" },
4406      { { "t3" }, "$11" },
4407      { { "t4" }, "$12" },
4408      { { "t5" }, "$13" },
4409      { { "t6" }, "$14" },
4410      { { "t7" }, "$15" },
4411      { { "s0" }, "$16" },
4412      { { "s1" }, "$17" },
4413      { { "s2" }, "$18" },
4414      { { "s3" }, "$19" },
4415      { { "s4" }, "$20" },
4416      { { "s5" }, "$21" },
4417      { { "s6" }, "$22" },
4418      { { "s7" }, "$23" },
4419      { { "t8" }, "$24" },
4420      { { "t9" }, "$25" },
4421      { { "k0" }, "$26" },
4422      { { "k1" }, "$27" },
4423      { { "gp" }, "$28" },
4424      { { "sp","$sp" }, "$29" },
4425      { { "fp","$fp" }, "$30" },
4426      { { "ra" }, "$31" }
4427    };
4428    Aliases = GCCRegAliases;
4429    NumAliases = llvm::array_lengthof(GCCRegAliases);
4430  }
4431};
4432
4433class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4434public:
4435  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4436    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4437                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4438  }
4439  virtual void getTargetDefines(const LangOptions &Opts,
4440                                MacroBuilder &Builder) const {
4441    DefineStd(Builder, "MIPSEB", Opts);
4442    Builder.defineMacro("_MIPSEB");
4443    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4444  }
4445};
4446
4447class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4448public:
4449  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4450    BigEndian = false;
4451    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4452                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4453  }
4454  virtual void getTargetDefines(const LangOptions &Opts,
4455                                MacroBuilder &Builder) const {
4456    DefineStd(Builder, "MIPSEL", Opts);
4457    Builder.defineMacro("_MIPSEL");
4458    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4459  }
4460};
4461
4462class Mips64TargetInfoBase : public MipsTargetInfoBase {
4463  virtual void SetDescriptionString(const std::string &Name) = 0;
4464public:
4465  Mips64TargetInfoBase(const std::string& triple) :
4466    MipsTargetInfoBase(triple, "n64", "mips64") {
4467    LongWidth = LongAlign = 64;
4468    PointerWidth = PointerAlign = 64;
4469    LongDoubleWidth = LongDoubleAlign = 128;
4470    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4471    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4472      LongDoubleWidth = LongDoubleAlign = 64;
4473      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4474    }
4475    SuitableAlign = 128;
4476    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4477  }
4478  virtual bool setABI(const std::string &Name) {
4479    SetDescriptionString(Name);
4480
4481    if (Name != "n32" && Name != "n64")
4482      return false;
4483
4484    ABI = Name;
4485
4486    if (Name == "n32") {
4487      LongWidth = LongAlign = 32;
4488      PointerWidth = PointerAlign = 32;
4489    }
4490
4491    return true;
4492  }
4493  virtual void getTargetDefines(const LangOptions &Opts,
4494                                MacroBuilder &Builder) const {
4495    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4496
4497    Builder.defineMacro("__mips64");
4498    Builder.defineMacro("__mips64__");
4499
4500    if (ABI == "n32") {
4501      Builder.defineMacro("__mips_n32");
4502      Builder.defineMacro("_ABIN32", "2");
4503      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4504    }
4505    else if (ABI == "n64") {
4506      Builder.defineMacro("__mips_n64");
4507      Builder.defineMacro("_ABI64", "3");
4508      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4509    }
4510    else
4511      llvm_unreachable("Invalid ABI for Mips64.");
4512  }
4513  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4514                                unsigned &NumAliases) const {
4515    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4516      { { "at" },  "$1" },
4517      { { "v0" },  "$2" },
4518      { { "v1" },  "$3" },
4519      { { "a0" },  "$4" },
4520      { { "a1" },  "$5" },
4521      { { "a2" },  "$6" },
4522      { { "a3" },  "$7" },
4523      { { "a4" },  "$8" },
4524      { { "a5" },  "$9" },
4525      { { "a6" }, "$10" },
4526      { { "a7" }, "$11" },
4527      { { "t0" }, "$12" },
4528      { { "t1" }, "$13" },
4529      { { "t2" }, "$14" },
4530      { { "t3" }, "$15" },
4531      { { "s0" }, "$16" },
4532      { { "s1" }, "$17" },
4533      { { "s2" }, "$18" },
4534      { { "s3" }, "$19" },
4535      { { "s4" }, "$20" },
4536      { { "s5" }, "$21" },
4537      { { "s6" }, "$22" },
4538      { { "s7" }, "$23" },
4539      { { "t8" }, "$24" },
4540      { { "t9" }, "$25" },
4541      { { "k0" }, "$26" },
4542      { { "k1" }, "$27" },
4543      { { "gp" }, "$28" },
4544      { { "sp","$sp" }, "$29" },
4545      { { "fp","$fp" }, "$30" },
4546      { { "ra" }, "$31" }
4547    };
4548    Aliases = GCCRegAliases;
4549    NumAliases = llvm::array_lengthof(GCCRegAliases);
4550  }
4551};
4552
4553class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4554  virtual void SetDescriptionString(const std::string &Name) {
4555    // Change DescriptionString only if ABI is n32.
4556    if (Name == "n32")
4557      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4558                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4559                          "v64:64:64-n32:64-S128";
4560  }
4561public:
4562  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4563    // Default ABI is n64.
4564    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4565                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4566                        "v64:64:64-n32:64-S128";
4567  }
4568  virtual void getTargetDefines(const LangOptions &Opts,
4569                                MacroBuilder &Builder) const {
4570    DefineStd(Builder, "MIPSEB", Opts);
4571    Builder.defineMacro("_MIPSEB");
4572    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4573  }
4574};
4575
4576class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4577  virtual void SetDescriptionString(const std::string &Name) {
4578    // Change DescriptionString only if ABI is n32.
4579    if (Name == "n32")
4580      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4581                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4582                          "-v64:64:64-n32:64-S128";
4583  }
4584public:
4585  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4586    // Default ABI is n64.
4587    BigEndian = false;
4588    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4589                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4590                        "v64:64:64-n32:64-S128";
4591  }
4592  virtual void getTargetDefines(const LangOptions &Opts,
4593                                MacroBuilder &Builder) const {
4594    DefineStd(Builder, "MIPSEL", Opts);
4595    Builder.defineMacro("_MIPSEL");
4596    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4597  }
4598};
4599} // end anonymous namespace.
4600
4601namespace {
4602class PNaClTargetInfo : public TargetInfo {
4603public:
4604  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4605    BigEndian = false;
4606    this->UserLabelPrefix = "";
4607    this->LongAlign = 32;
4608    this->LongWidth = 32;
4609    this->PointerAlign = 32;
4610    this->PointerWidth = 32;
4611    this->IntMaxType = TargetInfo::SignedLongLong;
4612    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4613    this->Int64Type = TargetInfo::SignedLongLong;
4614    this->DoubleAlign = 64;
4615    this->LongDoubleWidth = 64;
4616    this->LongDoubleAlign = 64;
4617    this->SizeType = TargetInfo::UnsignedInt;
4618    this->PtrDiffType = TargetInfo::SignedInt;
4619    this->IntPtrType = TargetInfo::SignedInt;
4620    this->RegParmMax = 2;
4621    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4622                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4623  }
4624
4625  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4626  }
4627  virtual void getArchDefines(const LangOptions &Opts,
4628                              MacroBuilder &Builder) const {
4629    Builder.defineMacro("__le32__");
4630    Builder.defineMacro("__pnacl__");
4631  }
4632  virtual void getTargetDefines(const LangOptions &Opts,
4633                                MacroBuilder &Builder) const {
4634    Builder.defineMacro("__LITTLE_ENDIAN__");
4635    getArchDefines(Opts, Builder);
4636  }
4637  virtual bool hasFeature(StringRef Feature) const {
4638    return Feature == "pnacl";
4639  }
4640  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4641                                 unsigned &NumRecords) const {
4642  }
4643  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4644    return TargetInfo::PNaClABIBuiltinVaList;
4645  }
4646  virtual void getGCCRegNames(const char * const *&Names,
4647                              unsigned &NumNames) const;
4648  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4649                                unsigned &NumAliases) const;
4650  virtual bool validateAsmConstraint(const char *&Name,
4651                                     TargetInfo::ConstraintInfo &Info) const {
4652    return false;
4653  }
4654
4655  virtual const char *getClobbers() const {
4656    return "";
4657  }
4658};
4659
4660void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4661                                     unsigned &NumNames) const {
4662  Names = NULL;
4663  NumNames = 0;
4664}
4665
4666void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4667                                       unsigned &NumAliases) const {
4668  Aliases = NULL;
4669  NumAliases = 0;
4670}
4671} // end anonymous namespace.
4672
4673namespace {
4674  static const unsigned SPIRAddrSpaceMap[] = {
4675    1,    // opencl_global
4676    3,    // opencl_local
4677    2,    // opencl_constant
4678    0,    // cuda_device
4679    0,    // cuda_constant
4680    0     // cuda_shared
4681  };
4682  class SPIRTargetInfo : public TargetInfo {
4683    static const char * const GCCRegNames[];
4684    static const Builtin::Info BuiltinInfo[];
4685    std::vector<StringRef> AvailableFeatures;
4686  public:
4687    SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
4688      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
4689        "SPIR target must use unknown OS");
4690      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
4691        "SPIR target must use unknown environment type");
4692      BigEndian = false;
4693      TLSSupported = false;
4694      LongWidth = LongAlign = 64;
4695      AddrSpaceMap = &SPIRAddrSpaceMap;
4696      // Define available target features
4697      // These must be defined in sorted order!
4698      NoAsmVariants = true;
4699    }
4700    virtual void getTargetDefines(const LangOptions &Opts,
4701                                  MacroBuilder &Builder) const {
4702      DefineStd(Builder, "SPIR", Opts);
4703    }
4704    virtual bool hasFeature(StringRef Feature) const {
4705      return Feature == "spir";
4706    }
4707
4708    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4709                                   unsigned &NumRecords) const {}
4710    virtual const char *getClobbers() const {
4711      return "";
4712    }
4713    virtual void getGCCRegNames(const char * const *&Names,
4714                                unsigned &NumNames) const {}
4715    virtual bool validateAsmConstraint(const char *&Name,
4716                                       TargetInfo::ConstraintInfo &info) const {
4717      return true;
4718    }
4719    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4720                                  unsigned &NumAliases) const {}
4721    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4722      return TargetInfo::VoidPtrBuiltinVaList;
4723    }
4724  };
4725
4726
4727  class SPIR32TargetInfo : public SPIRTargetInfo {
4728  public:
4729    SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4730      PointerWidth = PointerAlign = 32;
4731      SizeType     = TargetInfo::UnsignedInt;
4732      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
4733      DescriptionString
4734        = "p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4735          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4736          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4737          "v512:512:512-v1024:1024:1024";
4738  }
4739  };
4740
4741  class SPIR64TargetInfo : public SPIRTargetInfo {
4742  public:
4743    SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
4744      PointerWidth = PointerAlign = 64;
4745      SizeType     = TargetInfo::UnsignedLong;
4746      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
4747      DescriptionString
4748        = "p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4749          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
4750          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
4751          "v512:512:512-v1024:1024:1024";
4752  }
4753  };
4754}
4755
4756
4757//===----------------------------------------------------------------------===//
4758// Driver code
4759//===----------------------------------------------------------------------===//
4760
4761static TargetInfo *AllocateTarget(const std::string &T) {
4762  llvm::Triple Triple(T);
4763  llvm::Triple::OSType os = Triple.getOS();
4764
4765  switch (Triple.getArch()) {
4766  default:
4767    return NULL;
4768
4769  case llvm::Triple::hexagon:
4770    return new HexagonTargetInfo(T);
4771
4772  case llvm::Triple::aarch64:
4773    switch (os) {
4774    case llvm::Triple::Linux:
4775      return new LinuxTargetInfo<AArch64TargetInfo>(T);
4776    default:
4777      return new AArch64TargetInfo(T);
4778    }
4779
4780  case llvm::Triple::arm:
4781  case llvm::Triple::thumb:
4782    if (Triple.isOSDarwin())
4783      return new DarwinARMTargetInfo(T);
4784
4785    switch (os) {
4786    case llvm::Triple::Linux:
4787      return new LinuxTargetInfo<ARMTargetInfo>(T);
4788    case llvm::Triple::FreeBSD:
4789      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
4790    case llvm::Triple::NetBSD:
4791      return new NetBSDTargetInfo<ARMTargetInfo>(T);
4792    case llvm::Triple::OpenBSD:
4793      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
4794    case llvm::Triple::Bitrig:
4795      return new BitrigTargetInfo<ARMTargetInfo>(T);
4796    case llvm::Triple::RTEMS:
4797      return new RTEMSTargetInfo<ARMTargetInfo>(T);
4798    case llvm::Triple::NaCl:
4799      return new NaClTargetInfo<ARMTargetInfo>(T);
4800    default:
4801      return new ARMTargetInfo(T);
4802    }
4803
4804  case llvm::Triple::msp430:
4805    return new MSP430TargetInfo(T);
4806
4807  case llvm::Triple::mips:
4808    switch (os) {
4809    case llvm::Triple::Linux:
4810      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
4811    case llvm::Triple::RTEMS:
4812      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
4813    case llvm::Triple::FreeBSD:
4814      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
4815    case llvm::Triple::NetBSD:
4816      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
4817    default:
4818      return new Mips32EBTargetInfo(T);
4819    }
4820
4821  case llvm::Triple::mipsel:
4822    switch (os) {
4823    case llvm::Triple::Linux:
4824      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
4825    case llvm::Triple::RTEMS:
4826      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
4827    case llvm::Triple::FreeBSD:
4828      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
4829    case llvm::Triple::NetBSD:
4830      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
4831    default:
4832      return new Mips32ELTargetInfo(T);
4833    }
4834
4835  case llvm::Triple::mips64:
4836    switch (os) {
4837    case llvm::Triple::Linux:
4838      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
4839    case llvm::Triple::RTEMS:
4840      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
4841    case llvm::Triple::FreeBSD:
4842      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
4843    case llvm::Triple::NetBSD:
4844      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
4845    case llvm::Triple::OpenBSD:
4846      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
4847    default:
4848      return new Mips64EBTargetInfo(T);
4849    }
4850
4851  case llvm::Triple::mips64el:
4852    switch (os) {
4853    case llvm::Triple::Linux:
4854      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
4855    case llvm::Triple::RTEMS:
4856      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
4857    case llvm::Triple::FreeBSD:
4858      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
4859    case llvm::Triple::NetBSD:
4860      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
4861    case llvm::Triple::OpenBSD:
4862      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
4863    default:
4864      return new Mips64ELTargetInfo(T);
4865    }
4866
4867  case llvm::Triple::le32:
4868    switch (os) {
4869      case llvm::Triple::NaCl:
4870        return new NaClTargetInfo<PNaClTargetInfo>(T);
4871      default:
4872        return NULL;
4873    }
4874
4875  case llvm::Triple::ppc:
4876    if (Triple.isOSDarwin())
4877      return new DarwinPPC32TargetInfo(T);
4878    switch (os) {
4879    case llvm::Triple::Linux:
4880      return new LinuxTargetInfo<PPC32TargetInfo>(T);
4881    case llvm::Triple::FreeBSD:
4882      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
4883    case llvm::Triple::NetBSD:
4884      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
4885    case llvm::Triple::OpenBSD:
4886      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
4887    case llvm::Triple::RTEMS:
4888      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
4889    default:
4890      return new PPC32TargetInfo(T);
4891    }
4892
4893  case llvm::Triple::ppc64:
4894    if (Triple.isOSDarwin())
4895      return new DarwinPPC64TargetInfo(T);
4896    switch (os) {
4897    case llvm::Triple::Linux:
4898      return new LinuxTargetInfo<PPC64TargetInfo>(T);
4899    case llvm::Triple::Lv2:
4900      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
4901    case llvm::Triple::FreeBSD:
4902      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
4903    case llvm::Triple::NetBSD:
4904      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
4905    default:
4906      return new PPC64TargetInfo(T);
4907    }
4908
4909  case llvm::Triple::nvptx:
4910    return new NVPTX32TargetInfo(T);
4911  case llvm::Triple::nvptx64:
4912    return new NVPTX64TargetInfo(T);
4913
4914  case llvm::Triple::mblaze:
4915    return new MBlazeTargetInfo(T);
4916
4917  case llvm::Triple::r600:
4918    return new R600TargetInfo(T);
4919
4920  case llvm::Triple::sparc:
4921    switch (os) {
4922    case llvm::Triple::Linux:
4923      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
4924    case llvm::Triple::AuroraUX:
4925      return new AuroraUXSparcV8TargetInfo(T);
4926    case llvm::Triple::Solaris:
4927      return new SolarisSparcV8TargetInfo(T);
4928    case llvm::Triple::NetBSD:
4929      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
4930    case llvm::Triple::OpenBSD:
4931      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
4932    case llvm::Triple::RTEMS:
4933      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
4934    default:
4935      return new SparcV8TargetInfo(T);
4936    }
4937
4938  case llvm::Triple::tce:
4939    return new TCETargetInfo(T);
4940
4941  case llvm::Triple::x86:
4942    if (Triple.isOSDarwin())
4943      return new DarwinI386TargetInfo(T);
4944
4945    switch (os) {
4946    case llvm::Triple::AuroraUX:
4947      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
4948    case llvm::Triple::Linux:
4949      return new LinuxTargetInfo<X86_32TargetInfo>(T);
4950    case llvm::Triple::DragonFly:
4951      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
4952    case llvm::Triple::NetBSD:
4953      return new NetBSDI386TargetInfo(T);
4954    case llvm::Triple::OpenBSD:
4955      return new OpenBSDI386TargetInfo(T);
4956    case llvm::Triple::Bitrig:
4957      return new BitrigI386TargetInfo(T);
4958    case llvm::Triple::FreeBSD:
4959      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
4960    case llvm::Triple::Minix:
4961      return new MinixTargetInfo<X86_32TargetInfo>(T);
4962    case llvm::Triple::Solaris:
4963      return new SolarisTargetInfo<X86_32TargetInfo>(T);
4964    case llvm::Triple::Cygwin:
4965      return new CygwinX86_32TargetInfo(T);
4966    case llvm::Triple::MinGW32:
4967      return new MinGWX86_32TargetInfo(T);
4968    case llvm::Triple::Win32:
4969      return new VisualStudioWindowsX86_32TargetInfo(T);
4970    case llvm::Triple::Haiku:
4971      return new HaikuX86_32TargetInfo(T);
4972    case llvm::Triple::RTEMS:
4973      return new RTEMSX86_32TargetInfo(T);
4974    case llvm::Triple::NaCl:
4975      return new NaClTargetInfo<X86_32TargetInfo>(T);
4976    default:
4977      return new X86_32TargetInfo(T);
4978    }
4979
4980  case llvm::Triple::x86_64:
4981    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
4982      return new DarwinX86_64TargetInfo(T);
4983
4984    switch (os) {
4985    case llvm::Triple::AuroraUX:
4986      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
4987    case llvm::Triple::Linux:
4988      return new LinuxTargetInfo<X86_64TargetInfo>(T);
4989    case llvm::Triple::DragonFly:
4990      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
4991    case llvm::Triple::NetBSD:
4992      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
4993    case llvm::Triple::OpenBSD:
4994      return new OpenBSDX86_64TargetInfo(T);
4995    case llvm::Triple::Bitrig:
4996      return new BitrigX86_64TargetInfo(T);
4997    case llvm::Triple::FreeBSD:
4998      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
4999    case llvm::Triple::Solaris:
5000      return new SolarisTargetInfo<X86_64TargetInfo>(T);
5001    case llvm::Triple::MinGW32:
5002      return new MinGWX86_64TargetInfo(T);
5003    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5004      return new VisualStudioWindowsX86_64TargetInfo(T);
5005    case llvm::Triple::NaCl:
5006      return new NaClTargetInfo<X86_64TargetInfo>(T);
5007    default:
5008      return new X86_64TargetInfo(T);
5009    }
5010
5011    case llvm::Triple::spir: {
5012      llvm::Triple Triple(T);
5013      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5014        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5015        return NULL;
5016      return new SPIR32TargetInfo(T);
5017    }
5018    case llvm::Triple::spir64: {
5019      llvm::Triple Triple(T);
5020      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5021        Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5022        return NULL;
5023      return new SPIR64TargetInfo(T);
5024    }
5025  }
5026}
5027
5028/// CreateTargetInfo - Return the target info object for the specified target
5029/// triple.
5030TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5031                                         TargetOptions *Opts) {
5032  llvm::Triple Triple(Opts->Triple);
5033
5034  // Construct the target
5035  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5036  if (!Target) {
5037    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5038    return 0;
5039  }
5040  Target->setTargetOpts(Opts);
5041
5042  // Set the target CPU if specified.
5043  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5044    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5045    return 0;
5046  }
5047
5048  // Set the target ABI if specified.
5049  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5050    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5051    return 0;
5052  }
5053
5054  // Set the target C++ ABI.
5055  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5056    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5057    return 0;
5058  }
5059
5060  // Compute the default target features, we need the target to handle this
5061  // because features may have dependencies on one another.
5062  llvm::StringMap<bool> Features;
5063  Target->getDefaultFeatures(Features);
5064
5065  // Apply the user specified deltas.
5066  // First the enables.
5067  for (std::vector<std::string>::const_iterator
5068         it = Opts->FeaturesAsWritten.begin(),
5069         ie = Opts->FeaturesAsWritten.end();
5070       it != ie; ++it) {
5071    const char *Name = it->c_str();
5072
5073    if (Name[0] != '+')
5074      continue;
5075
5076    // Apply the feature via the target.
5077    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5078      Diags.Report(diag::err_target_invalid_feature) << Name;
5079      return 0;
5080    }
5081  }
5082
5083  // Then the disables.
5084  for (std::vector<std::string>::const_iterator
5085         it = Opts->FeaturesAsWritten.begin(),
5086         ie = Opts->FeaturesAsWritten.end();
5087       it != ie; ++it) {
5088    const char *Name = it->c_str();
5089
5090    if (Name[0] == '+')
5091      continue;
5092
5093    // Apply the feature via the target.
5094    if (Name[0] != '-' ||
5095        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5096      Diags.Report(diag::err_target_invalid_feature) << Name;
5097      return 0;
5098    }
5099  }
5100
5101  // Add the features to the compile options.
5102  //
5103  // FIXME: If we are completely confident that we have the right set, we only
5104  // need to pass the minuses.
5105  Opts->Features.clear();
5106  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5107         ie = Features.end(); it != ie; ++it)
5108    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5109  Target->HandleTargetFeatures(Opts->Features);
5110
5111  return Target.take();
5112}
5113