Targets.cpp revision 9b79630004fe0a748e0328a19de25840b37d4aa1 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "6000");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.isiOS()) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else if (Triple.getArchName() != "thumbv6m" &&
153             Triple.getArchName() != "thumbv7m" &&
154             Triple.getArchName() != "thumbv7em") {
155    // Note that the Driver allows versions which aren't representable in the
156    // define (because we only get a single digit for the minor and micro
157    // revision numbers). So, we limit them to the maximum representable
158    // version.
159    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
160    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161    char Str[5];
162    Str[0] = '0' + (Maj / 10);
163    Str[1] = '0' + (Maj % 10);
164    Str[2] = '0' + std::min(Min, 9U);
165    Str[3] = '0' + std::min(Rev, 9U);
166    Str[4] = '\0';
167    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
168  }
169
170  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
171}
172
173namespace {
174template<typename Target>
175class DarwinTargetInfo : public OSTargetInfo<Target> {
176protected:
177  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
178                            MacroBuilder &Builder) const {
179    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
180                     this->PlatformMinVersion);
181  }
182
183public:
184  DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
185    this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
186    this->MCountName = "\01mcount";
187  }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
228      : OSTargetInfo<Target>(Triple) {
229    this->UserLabelPrefix = "";
230
231    switch (Triple.getArch()) {
232    default:
233    case llvm::Triple::x86:
234    case llvm::Triple::x86_64:
235      this->MCountName = ".mcount";
236      break;
237    }
238  }
239};
240
241// FreeBSD Target
242template<typename Target>
243class FreeBSDTargetInfo : public OSTargetInfo<Target> {
244protected:
245  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
246                            MacroBuilder &Builder) const {
247    // FreeBSD defines; list based off of gcc output
248
249    unsigned Release = Triple.getOSMajorVersion();
250    if (Release == 0U)
251      Release = 8;
252
253    Builder.defineMacro("__FreeBSD__", Twine(Release));
254    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
255    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
256    DefineStd(Builder, "unix", Opts);
257    Builder.defineMacro("__ELF__");
258
259    // On FreeBSD, wchar_t contains the number of the code point as
260    // used by the character set of the locale. These character sets are
261    // not necessarily a superset of ASCII.
262    Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
263  }
264public:
265  FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
266    this->UserLabelPrefix = "";
267
268    switch (Triple.getArch()) {
269    default:
270    case llvm::Triple::x86:
271    case llvm::Triple::x86_64:
272      this->MCountName = ".mcount";
273      break;
274    case llvm::Triple::mips:
275    case llvm::Triple::mipsel:
276    case llvm::Triple::ppc:
277    case llvm::Triple::ppc64:
278    case llvm::Triple::ppc64le:
279      this->MCountName = "_mcount";
280      break;
281    case llvm::Triple::arm:
282      this->MCountName = "__mcount";
283      break;
284    }
285  }
286};
287
288// GNU/kFreeBSD Target
289template<typename Target>
290class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
291protected:
292  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
293                            MacroBuilder &Builder) const {
294    // GNU/kFreeBSD defines; list based off of gcc output
295
296    DefineStd(Builder, "unix", Opts);
297    Builder.defineMacro("__FreeBSD_kernel__");
298    Builder.defineMacro("__GLIBC__");
299    Builder.defineMacro("__ELF__");
300    if (Opts.POSIXThreads)
301      Builder.defineMacro("_REENTRANT");
302    if (Opts.CPlusPlus)
303      Builder.defineMacro("_GNU_SOURCE");
304  }
305public:
306  KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
307    this->UserLabelPrefix = "";
308  }
309};
310
311// Minix Target
312template<typename Target>
313class MinixTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Minix defines
318
319    Builder.defineMacro("__minix", "3");
320    Builder.defineMacro("_EM_WSIZE", "4");
321    Builder.defineMacro("_EM_PSIZE", "4");
322    Builder.defineMacro("_EM_SSIZE", "2");
323    Builder.defineMacro("_EM_LSIZE", "4");
324    Builder.defineMacro("_EM_FSIZE", "4");
325    Builder.defineMacro("_EM_DSIZE", "8");
326    Builder.defineMacro("__ELF__");
327    DefineStd(Builder, "unix", Opts);
328  }
329public:
330  MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
331    this->UserLabelPrefix = "";
332  }
333};
334
335// Linux target
336template<typename Target>
337class LinuxTargetInfo : public OSTargetInfo<Target> {
338protected:
339  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
340                            MacroBuilder &Builder) const {
341    // Linux defines; list based off of gcc output
342    DefineStd(Builder, "unix", Opts);
343    DefineStd(Builder, "linux", Opts);
344    Builder.defineMacro("__gnu_linux__");
345    Builder.defineMacro("__ELF__");
346    if (Triple.getEnvironment() == llvm::Triple::Android)
347      Builder.defineMacro("__ANDROID__", "1");
348    if (Opts.POSIXThreads)
349      Builder.defineMacro("_REENTRANT");
350    if (Opts.CPlusPlus)
351      Builder.defineMacro("_GNU_SOURCE");
352  }
353public:
354  LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
355    this->UserLabelPrefix = "";
356    this->WIntType = TargetInfo::UnsignedInt;
357  }
358
359  virtual const char *getStaticInitSectionSpecifier() const {
360    return ".text.startup";
361  }
362};
363
364// NetBSD Target
365template<typename Target>
366class NetBSDTargetInfo : public OSTargetInfo<Target> {
367protected:
368  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
369                            MacroBuilder &Builder) const {
370    // NetBSD defines; list based off of gcc output
371    Builder.defineMacro("__NetBSD__");
372    Builder.defineMacro("__unix__");
373    Builder.defineMacro("__ELF__");
374    if (Opts.POSIXThreads)
375      Builder.defineMacro("_POSIX_THREADS");
376  }
377public:
378  NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
379    this->UserLabelPrefix = "";
380  }
381};
382
383// OpenBSD Target
384template<typename Target>
385class OpenBSDTargetInfo : public OSTargetInfo<Target> {
386protected:
387  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388                            MacroBuilder &Builder) const {
389    // OpenBSD defines; list based off of gcc output
390
391    Builder.defineMacro("__OpenBSD__");
392    DefineStd(Builder, "unix", Opts);
393    Builder.defineMacro("__ELF__");
394    if (Opts.POSIXThreads)
395      Builder.defineMacro("_REENTRANT");
396  }
397public:
398  OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
399    this->UserLabelPrefix = "";
400    this->TLSSupported = false;
401
402      switch (Triple.getArch()) {
403        default:
404        case llvm::Triple::x86:
405        case llvm::Triple::x86_64:
406        case llvm::Triple::arm:
407        case llvm::Triple::sparc:
408          this->MCountName = "__mcount";
409          break;
410        case llvm::Triple::mips64:
411        case llvm::Triple::mips64el:
412        case llvm::Triple::ppc:
413        case llvm::Triple::sparcv9:
414          this->MCountName = "_mcount";
415          break;
416      }
417  }
418};
419
420// Bitrig Target
421template<typename Target>
422class BitrigTargetInfo : public OSTargetInfo<Target> {
423protected:
424  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
425                            MacroBuilder &Builder) const {
426    // Bitrig defines; list based off of gcc output
427
428    Builder.defineMacro("__Bitrig__");
429    DefineStd(Builder, "unix", Opts);
430    Builder.defineMacro("__ELF__");
431    if (Opts.POSIXThreads)
432      Builder.defineMacro("_REENTRANT");
433  }
434public:
435  BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
436    this->UserLabelPrefix = "";
437    this->TLSSupported = false;
438    this->MCountName = "__mcount";
439  }
440};
441
442// PSP Target
443template<typename Target>
444class PSPTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PSP defines; list based on the output of the pspdev gcc toolchain.
449    Builder.defineMacro("PSP");
450    Builder.defineMacro("_PSP");
451    Builder.defineMacro("__psp__");
452    Builder.defineMacro("__ELF__");
453  }
454public:
455  PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
456    this->UserLabelPrefix = "";
457  }
458};
459
460// PS3 PPU Target
461template<typename Target>
462class PS3PPUTargetInfo : public OSTargetInfo<Target> {
463protected:
464  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
465                            MacroBuilder &Builder) const {
466    // PS3 PPU defines.
467    Builder.defineMacro("__PPC__");
468    Builder.defineMacro("__PPU__");
469    Builder.defineMacro("__CELLOS_LV2__");
470    Builder.defineMacro("__ELF__");
471    Builder.defineMacro("__LP32__");
472    Builder.defineMacro("_ARCH_PPC64");
473    Builder.defineMacro("__powerpc64__");
474  }
475public:
476  PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
477    this->UserLabelPrefix = "";
478    this->LongWidth = this->LongAlign = 32;
479    this->PointerWidth = this->PointerAlign = 32;
480    this->IntMaxType = TargetInfo::SignedLongLong;
481    this->UIntMaxType = TargetInfo::UnsignedLongLong;
482    this->Int64Type = TargetInfo::SignedLongLong;
483    this->SizeType = TargetInfo::UnsignedInt;
484    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
485                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
486  }
487};
488
489// FIXME: Need a real SPU target.
490// PS3 SPU Target
491template<typename Target>
492class PS3SPUTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    // PS3 PPU defines.
497    Builder.defineMacro("__SPU__");
498    Builder.defineMacro("__ELF__");
499  }
500public:
501  PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
502    this->UserLabelPrefix = "";
503  }
504};
505
506// AuroraUX target
507template<typename Target>
508class AuroraUXTargetInfo : public OSTargetInfo<Target> {
509protected:
510  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
511                            MacroBuilder &Builder) const {
512    DefineStd(Builder, "sun", Opts);
513    DefineStd(Builder, "unix", Opts);
514    Builder.defineMacro("__ELF__");
515    Builder.defineMacro("__svr4__");
516    Builder.defineMacro("__SVR4");
517  }
518public:
519  AuroraUXTargetInfo(const llvm::Triple &Triple)
520      : OSTargetInfo<Target>(Triple) {
521    this->UserLabelPrefix = "";
522    this->WCharType = this->SignedLong;
523    // FIXME: WIntType should be SignedLong
524  }
525};
526
527// Solaris target
528template<typename Target>
529class SolarisTargetInfo : public OSTargetInfo<Target> {
530protected:
531  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
532                            MacroBuilder &Builder) const {
533    DefineStd(Builder, "sun", Opts);
534    DefineStd(Builder, "unix", Opts);
535    Builder.defineMacro("__ELF__");
536    Builder.defineMacro("__svr4__");
537    Builder.defineMacro("__SVR4");
538    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
539    // newer, but to 500 for everything else.  feature_test.h has a check to
540    // ensure that you are not using C99 with an old version of X/Open or C89
541    // with a new version.
542    if (Opts.C99 || Opts.C11)
543      Builder.defineMacro("_XOPEN_SOURCE", "600");
544    else
545      Builder.defineMacro("_XOPEN_SOURCE", "500");
546    if (Opts.CPlusPlus)
547      Builder.defineMacro("__C99FEATURES__");
548    Builder.defineMacro("_LARGEFILE_SOURCE");
549    Builder.defineMacro("_LARGEFILE64_SOURCE");
550    Builder.defineMacro("__EXTENSIONS__");
551    Builder.defineMacro("_REENTRANT");
552  }
553public:
554  SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
555    this->UserLabelPrefix = "";
556    this->WCharType = this->SignedInt;
557    // FIXME: WIntType should be SignedLong
558  }
559};
560
561// Windows target
562template<typename Target>
563class WindowsTargetInfo : public OSTargetInfo<Target> {
564protected:
565  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
566                            MacroBuilder &Builder) const {
567    Builder.defineMacro("_WIN32");
568  }
569  void getVisualStudioDefines(const LangOptions &Opts,
570                              MacroBuilder &Builder) const {
571    if (Opts.CPlusPlus) {
572      if (Opts.RTTI)
573        Builder.defineMacro("_CPPRTTI");
574
575      if (Opts.Exceptions)
576        Builder.defineMacro("_CPPUNWIND");
577    }
578
579    if (!Opts.CharIsSigned)
580      Builder.defineMacro("_CHAR_UNSIGNED");
581
582    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
583    //        but it works for now.
584    if (Opts.POSIXThreads)
585      Builder.defineMacro("_MT");
586
587    if (Opts.MSCVersion != 0)
588      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
589
590    if (Opts.MicrosoftExt) {
591      Builder.defineMacro("_MSC_EXTENSIONS");
592
593      if (Opts.CPlusPlus11) {
594        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
595        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
596        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
597      }
598    }
599
600    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
601  }
602
603public:
604  WindowsTargetInfo(const llvm::Triple &Triple)
605      : OSTargetInfo<Target>(Triple) {}
606};
607
608template <typename Target>
609class NaClTargetInfo : public OSTargetInfo<Target> {
610protected:
611  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
612                            MacroBuilder &Builder) const {
613    if (Opts.POSIXThreads)
614      Builder.defineMacro("_REENTRANT");
615    if (Opts.CPlusPlus)
616      Builder.defineMacro("_GNU_SOURCE");
617
618    DefineStd(Builder, "unix", Opts);
619    Builder.defineMacro("__ELF__");
620    Builder.defineMacro("__native_client__");
621  }
622
623public:
624  NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
625    this->UserLabelPrefix = "";
626    this->LongAlign = 32;
627    this->LongWidth = 32;
628    this->PointerAlign = 32;
629    this->PointerWidth = 32;
630    this->IntMaxType = TargetInfo::SignedLongLong;
631    this->UIntMaxType = TargetInfo::UnsignedLongLong;
632    this->Int64Type = TargetInfo::SignedLongLong;
633    this->DoubleAlign = 64;
634    this->LongDoubleWidth = 64;
635    this->LongDoubleAlign = 64;
636    this->SizeType = TargetInfo::UnsignedInt;
637    this->PtrDiffType = TargetInfo::SignedInt;
638    this->IntPtrType = TargetInfo::SignedInt;
639    // RegParmMax is inherited from the underlying architecture
640    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
641    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
642                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
643  }
644  virtual typename Target::CallingConvCheckResult checkCallingConvention(
645      CallingConv CC) const {
646    return CC == CC_PnaclCall ? Target::CCCR_OK :
647        Target::checkCallingConvention(CC);
648  }
649};
650} // end anonymous namespace.
651
652//===----------------------------------------------------------------------===//
653// Specific target implementations.
654//===----------------------------------------------------------------------===//
655
656namespace {
657// PPC abstract base class
658class PPCTargetInfo : public TargetInfo {
659  static const Builtin::Info BuiltinInfo[];
660  static const char * const GCCRegNames[];
661  static const TargetInfo::GCCRegAlias GCCRegAliases[];
662  std::string CPU;
663
664  // Target cpu features.
665  bool HasVSX;
666
667public:
668  PPCTargetInfo(const llvm::Triple &Triple)
669      : TargetInfo(Triple), HasVSX(false) {
670    BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
671    LongDoubleWidth = LongDoubleAlign = 128;
672    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
673  }
674
675  /// \brief Flags for architecture specific defines.
676  typedef enum {
677    ArchDefineNone  = 0,
678    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
679    ArchDefinePpcgr = 1 << 1,
680    ArchDefinePpcsq = 1 << 2,
681    ArchDefine440   = 1 << 3,
682    ArchDefine603   = 1 << 4,
683    ArchDefine604   = 1 << 5,
684    ArchDefinePwr4  = 1 << 6,
685    ArchDefinePwr5  = 1 << 7,
686    ArchDefinePwr5x = 1 << 8,
687    ArchDefinePwr6  = 1 << 9,
688    ArchDefinePwr6x = 1 << 10,
689    ArchDefinePwr7  = 1 << 11,
690    ArchDefineA2    = 1 << 12,
691    ArchDefineA2q   = 1 << 13
692  } ArchDefineTypes;
693
694  // Note: GCC recognizes the following additional cpus:
695  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
696  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
697  //  titan, rs64.
698  virtual bool setCPU(const std::string &Name) {
699    bool CPUKnown = llvm::StringSwitch<bool>(Name)
700      .Case("generic", true)
701      .Case("440", true)
702      .Case("450", true)
703      .Case("601", true)
704      .Case("602", true)
705      .Case("603", true)
706      .Case("603e", true)
707      .Case("603ev", true)
708      .Case("604", true)
709      .Case("604e", true)
710      .Case("620", true)
711      .Case("630", true)
712      .Case("g3", true)
713      .Case("7400", true)
714      .Case("g4", true)
715      .Case("7450", true)
716      .Case("g4+", true)
717      .Case("750", true)
718      .Case("970", true)
719      .Case("g5", true)
720      .Case("a2", true)
721      .Case("a2q", true)
722      .Case("e500mc", true)
723      .Case("e5500", true)
724      .Case("power3", true)
725      .Case("pwr3", true)
726      .Case("power4", true)
727      .Case("pwr4", true)
728      .Case("power5", true)
729      .Case("pwr5", true)
730      .Case("power5x", true)
731      .Case("pwr5x", true)
732      .Case("power6", true)
733      .Case("pwr6", true)
734      .Case("power6x", true)
735      .Case("pwr6x", true)
736      .Case("power7", true)
737      .Case("pwr7", true)
738      .Case("powerpc", true)
739      .Case("ppc", true)
740      .Case("powerpc64", true)
741      .Case("ppc64", true)
742      .Case("powerpc64le", true)
743      .Case("ppc64le", true)
744      .Default(false);
745
746    if (CPUKnown)
747      CPU = Name;
748
749    return CPUKnown;
750  }
751
752  virtual void getTargetBuiltins(const Builtin::Info *&Records,
753                                 unsigned &NumRecords) const {
754    Records = BuiltinInfo;
755    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
756  }
757
758  virtual bool isCLZForZeroUndef() const { return false; }
759
760  virtual void getTargetDefines(const LangOptions &Opts,
761                                MacroBuilder &Builder) const;
762
763  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
764
765  virtual bool handleTargetFeatures(std::vector<std::string> &Features,
766                                    DiagnosticsEngine &Diags);
767  virtual bool hasFeature(StringRef Feature) const;
768
769  virtual void getGCCRegNames(const char * const *&Names,
770                              unsigned &NumNames) const;
771  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
772                                unsigned &NumAliases) const;
773  virtual bool validateAsmConstraint(const char *&Name,
774                                     TargetInfo::ConstraintInfo &Info) const {
775    switch (*Name) {
776    default: return false;
777    case 'O': // Zero
778      break;
779    case 'b': // Base register
780    case 'f': // Floating point register
781      Info.setAllowsRegister();
782      break;
783    // FIXME: The following are added to allow parsing.
784    // I just took a guess at what the actions should be.
785    // Also, is more specific checking needed?  I.e. specific registers?
786    case 'd': // Floating point register (containing 64-bit value)
787    case 'v': // Altivec vector register
788      Info.setAllowsRegister();
789      break;
790    case 'w':
791      switch (Name[1]) {
792        case 'd':// VSX vector register to hold vector double data
793        case 'f':// VSX vector register to hold vector float data
794        case 's':// VSX vector register to hold scalar float data
795        case 'a':// Any VSX register
796          break;
797        default:
798          return false;
799      }
800      Info.setAllowsRegister();
801      Name++; // Skip over 'w'.
802      break;
803    case 'h': // `MQ', `CTR', or `LINK' register
804    case 'q': // `MQ' register
805    case 'c': // `CTR' register
806    case 'l': // `LINK' register
807    case 'x': // `CR' register (condition register) number 0
808    case 'y': // `CR' register (condition register)
809    case 'z': // `XER[CA]' carry bit (part of the XER register)
810      Info.setAllowsRegister();
811      break;
812    case 'I': // Signed 16-bit constant
813    case 'J': // Unsigned 16-bit constant shifted left 16 bits
814              //  (use `L' instead for SImode constants)
815    case 'K': // Unsigned 16-bit constant
816    case 'L': // Signed 16-bit constant shifted left 16 bits
817    case 'M': // Constant larger than 31
818    case 'N': // Exact power of 2
819    case 'P': // Constant whose negation is a signed 16-bit constant
820    case 'G': // Floating point constant that can be loaded into a
821              // register with one instruction per word
822    case 'H': // Integer/Floating point constant that can be loaded
823              // into a register using three instructions
824      break;
825    case 'm': // Memory operand. Note that on PowerPC targets, m can
826              // include addresses that update the base register. It
827              // is therefore only safe to use `m' in an asm statement
828              // if that asm statement accesses the operand exactly once.
829              // The asm statement must also use `%U<opno>' as a
830              // placeholder for the "update" flag in the corresponding
831              // load or store instruction. For example:
832              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
833              // is correct but:
834              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
835              // is not. Use es rather than m if you don't want the base
836              // register to be updated.
837    case 'e':
838      if (Name[1] != 's')
839          return false;
840              // es: A "stable" memory operand; that is, one which does not
841              // include any automodification of the base register. Unlike
842              // `m', this constraint can be used in asm statements that
843              // might access the operand several times, or that might not
844              // access it at all.
845      Info.setAllowsMemory();
846      Name++; // Skip over 'e'.
847      break;
848    case 'Q': // Memory operand that is an offset from a register (it is
849              // usually better to use `m' or `es' in asm statements)
850    case 'Z': // Memory operand that is an indexed or indirect from a
851              // register (it is usually better to use `m' or `es' in
852              // asm statements)
853      Info.setAllowsMemory();
854      Info.setAllowsRegister();
855      break;
856    case 'R': // AIX TOC entry
857    case 'a': // Address operand that is an indexed or indirect from a
858              // register (`p' is preferable for asm statements)
859    case 'S': // Constant suitable as a 64-bit mask operand
860    case 'T': // Constant suitable as a 32-bit mask operand
861    case 'U': // System V Release 4 small data area reference
862    case 't': // AND masks that can be performed by two rldic{l, r}
863              // instructions
864    case 'W': // Vector constant that does not require memory
865    case 'j': // Vector constant that is all zeros.
866      break;
867    // End FIXME.
868    }
869    return true;
870  }
871  virtual const char *getClobbers() const {
872    return "";
873  }
874  int getEHDataRegisterNumber(unsigned RegNo) const {
875    if (RegNo == 0) return 3;
876    if (RegNo == 1) return 4;
877    return -1;
878  }
879};
880
881const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
882#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
883#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
884                                              ALL_LANGUAGES },
885#include "clang/Basic/BuiltinsPPC.def"
886};
887
888  /// handleTargetFeatures - Perform initialization based on the user
889/// configured set of features.
890bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
891                                         DiagnosticsEngine &Diags) {
892  // Remember the maximum enabled sselevel.
893  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
894    // Ignore disabled features.
895    if (Features[i][0] == '-')
896      continue;
897
898    StringRef Feature = StringRef(Features[i]).substr(1);
899
900    if (Feature == "vsx") {
901      HasVSX = true;
902      continue;
903    }
904
905    // TODO: Finish this list and add an assert that we've handled them
906    // all.
907  }
908
909  return true;
910}
911
912/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
913/// #defines that are not tied to a specific subtarget.
914void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
915                                     MacroBuilder &Builder) const {
916  // Target identification.
917  Builder.defineMacro("__ppc__");
918  Builder.defineMacro("__PPC__");
919  Builder.defineMacro("_ARCH_PPC");
920  Builder.defineMacro("__powerpc__");
921  Builder.defineMacro("__POWERPC__");
922  if (PointerWidth == 64) {
923    Builder.defineMacro("_ARCH_PPC64");
924    Builder.defineMacro("__powerpc64__");
925    Builder.defineMacro("__ppc64__");
926    Builder.defineMacro("__PPC64__");
927  }
928
929  // Target properties.
930  if (getTriple().getArch() == llvm::Triple::ppc64le) {
931    Builder.defineMacro("_LITTLE_ENDIAN");
932    Builder.defineMacro("__LITTLE_ENDIAN__");
933  } else {
934    if (getTriple().getOS() != llvm::Triple::NetBSD &&
935        getTriple().getOS() != llvm::Triple::OpenBSD)
936      Builder.defineMacro("_BIG_ENDIAN");
937    Builder.defineMacro("__BIG_ENDIAN__");
938  }
939
940  // Subtarget options.
941  Builder.defineMacro("__NATURAL_ALIGNMENT__");
942  Builder.defineMacro("__REGISTER_PREFIX__", "");
943
944  // FIXME: Should be controlled by command line option.
945  if (LongDoubleWidth == 128)
946    Builder.defineMacro("__LONG_DOUBLE_128__");
947
948  if (Opts.AltiVec) {
949    Builder.defineMacro("__VEC__", "10206");
950    Builder.defineMacro("__ALTIVEC__");
951  }
952
953  // CPU identification.
954  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
955    .Case("440",   ArchDefineName)
956    .Case("450",   ArchDefineName | ArchDefine440)
957    .Case("601",   ArchDefineName)
958    .Case("602",   ArchDefineName | ArchDefinePpcgr)
959    .Case("603",   ArchDefineName | ArchDefinePpcgr)
960    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
961    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
962    .Case("604",   ArchDefineName | ArchDefinePpcgr)
963    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
964    .Case("620",   ArchDefineName | ArchDefinePpcgr)
965    .Case("630",   ArchDefineName | ArchDefinePpcgr)
966    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
967    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
968    .Case("750",   ArchDefineName | ArchDefinePpcgr)
969    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
970                     | ArchDefinePpcsq)
971    .Case("a2",    ArchDefineA2)
972    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
973    .Case("pwr3",  ArchDefinePpcgr)
974    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
975    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
976                     | ArchDefinePpcsq)
977    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
978                     | ArchDefinePpcgr | ArchDefinePpcsq)
979    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
980                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
981    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
982                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
983                     | ArchDefinePpcsq)
984    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
985                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
986                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
987    .Case("power3",  ArchDefinePpcgr)
988    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
989    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
990                       | ArchDefinePpcsq)
991    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
992                       | ArchDefinePpcgr | ArchDefinePpcsq)
993    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
994                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
995    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
996                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
997                       | ArchDefinePpcsq)
998    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
999                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1000                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
1001    .Default(ArchDefineNone);
1002
1003  if (defs & ArchDefineName)
1004    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1005  if (defs & ArchDefinePpcgr)
1006    Builder.defineMacro("_ARCH_PPCGR");
1007  if (defs & ArchDefinePpcsq)
1008    Builder.defineMacro("_ARCH_PPCSQ");
1009  if (defs & ArchDefine440)
1010    Builder.defineMacro("_ARCH_440");
1011  if (defs & ArchDefine603)
1012    Builder.defineMacro("_ARCH_603");
1013  if (defs & ArchDefine604)
1014    Builder.defineMacro("_ARCH_604");
1015  if (defs & ArchDefinePwr4)
1016    Builder.defineMacro("_ARCH_PWR4");
1017  if (defs & ArchDefinePwr5)
1018    Builder.defineMacro("_ARCH_PWR5");
1019  if (defs & ArchDefinePwr5x)
1020    Builder.defineMacro("_ARCH_PWR5X");
1021  if (defs & ArchDefinePwr6)
1022    Builder.defineMacro("_ARCH_PWR6");
1023  if (defs & ArchDefinePwr6x)
1024    Builder.defineMacro("_ARCH_PWR6X");
1025  if (defs & ArchDefinePwr7)
1026    Builder.defineMacro("_ARCH_PWR7");
1027  if (defs & ArchDefineA2)
1028    Builder.defineMacro("_ARCH_A2");
1029  if (defs & ArchDefineA2q) {
1030    Builder.defineMacro("_ARCH_A2Q");
1031    Builder.defineMacro("_ARCH_QP");
1032  }
1033
1034  if (getTriple().getVendor() == llvm::Triple::BGQ) {
1035    Builder.defineMacro("__bg__");
1036    Builder.defineMacro("__THW_BLUEGENE__");
1037    Builder.defineMacro("__bgq__");
1038    Builder.defineMacro("__TOS_BGQ__");
1039  }
1040
1041  if (HasVSX)
1042    Builder.defineMacro("__VSX__");
1043
1044  // FIXME: The following are not yet generated here by Clang, but are
1045  //        generated by GCC:
1046  //
1047  //   _SOFT_FLOAT_
1048  //   __RECIP_PRECISION__
1049  //   __APPLE_ALTIVEC__
1050  //   __RECIP__
1051  //   __RECIPF__
1052  //   __RSQRTE__
1053  //   __RSQRTEF__
1054  //   _SOFT_DOUBLE_
1055  //   __NO_LWSYNC__
1056  //   __HAVE_BSWAP__
1057  //   __LONGDOUBLE128
1058  //   __CMODEL_MEDIUM__
1059  //   __CMODEL_LARGE__
1060  //   _CALL_SYSV
1061  //   _CALL_DARWIN
1062  //   __NO_FPRS__
1063}
1064
1065void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1066  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1067    .Case("7400", true)
1068    .Case("g4", true)
1069    .Case("7450", true)
1070    .Case("g4+", true)
1071    .Case("970", true)
1072    .Case("g5", true)
1073    .Case("pwr6", true)
1074    .Case("pwr7", true)
1075    .Case("ppc64", true)
1076    .Case("ppc64le", true)
1077    .Default(false);
1078
1079  Features["qpx"] = (CPU == "a2q");
1080}
1081
1082bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1083  return Feature == "powerpc";
1084}
1085
1086
1087const char * const PPCTargetInfo::GCCRegNames[] = {
1088  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1089  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1090  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1091  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1092  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1093  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1094  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1095  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1096  "mq", "lr", "ctr", "ap",
1097  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1098  "xer",
1099  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1100  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1101  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1102  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1103  "vrsave", "vscr",
1104  "spe_acc", "spefscr",
1105  "sfp"
1106};
1107
1108void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1109                                   unsigned &NumNames) const {
1110  Names = GCCRegNames;
1111  NumNames = llvm::array_lengthof(GCCRegNames);
1112}
1113
1114const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1115  // While some of these aliases do map to different registers
1116  // they still share the same register name.
1117  { { "0" }, "r0" },
1118  { { "1"}, "r1" },
1119  { { "2" }, "r2" },
1120  { { "3" }, "r3" },
1121  { { "4" }, "r4" },
1122  { { "5" }, "r5" },
1123  { { "6" }, "r6" },
1124  { { "7" }, "r7" },
1125  { { "8" }, "r8" },
1126  { { "9" }, "r9" },
1127  { { "10" }, "r10" },
1128  { { "11" }, "r11" },
1129  { { "12" }, "r12" },
1130  { { "13" }, "r13" },
1131  { { "14" }, "r14" },
1132  { { "15" }, "r15" },
1133  { { "16" }, "r16" },
1134  { { "17" }, "r17" },
1135  { { "18" }, "r18" },
1136  { { "19" }, "r19" },
1137  { { "20" }, "r20" },
1138  { { "21" }, "r21" },
1139  { { "22" }, "r22" },
1140  { { "23" }, "r23" },
1141  { { "24" }, "r24" },
1142  { { "25" }, "r25" },
1143  { { "26" }, "r26" },
1144  { { "27" }, "r27" },
1145  { { "28" }, "r28" },
1146  { { "29" }, "r29" },
1147  { { "30" }, "r30" },
1148  { { "31" }, "r31" },
1149  { { "fr0" }, "f0" },
1150  { { "fr1" }, "f1" },
1151  { { "fr2" }, "f2" },
1152  { { "fr3" }, "f3" },
1153  { { "fr4" }, "f4" },
1154  { { "fr5" }, "f5" },
1155  { { "fr6" }, "f6" },
1156  { { "fr7" }, "f7" },
1157  { { "fr8" }, "f8" },
1158  { { "fr9" }, "f9" },
1159  { { "fr10" }, "f10" },
1160  { { "fr11" }, "f11" },
1161  { { "fr12" }, "f12" },
1162  { { "fr13" }, "f13" },
1163  { { "fr14" }, "f14" },
1164  { { "fr15" }, "f15" },
1165  { { "fr16" }, "f16" },
1166  { { "fr17" }, "f17" },
1167  { { "fr18" }, "f18" },
1168  { { "fr19" }, "f19" },
1169  { { "fr20" }, "f20" },
1170  { { "fr21" }, "f21" },
1171  { { "fr22" }, "f22" },
1172  { { "fr23" }, "f23" },
1173  { { "fr24" }, "f24" },
1174  { { "fr25" }, "f25" },
1175  { { "fr26" }, "f26" },
1176  { { "fr27" }, "f27" },
1177  { { "fr28" }, "f28" },
1178  { { "fr29" }, "f29" },
1179  { { "fr30" }, "f30" },
1180  { { "fr31" }, "f31" },
1181  { { "cc" }, "cr0" },
1182};
1183
1184void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1185                                     unsigned &NumAliases) const {
1186  Aliases = GCCRegAliases;
1187  NumAliases = llvm::array_lengthof(GCCRegAliases);
1188}
1189} // end anonymous namespace.
1190
1191namespace {
1192class PPC32TargetInfo : public PPCTargetInfo {
1193public:
1194  PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1195    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1196                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1197
1198    switch (getTriple().getOS()) {
1199    case llvm::Triple::Linux:
1200    case llvm::Triple::FreeBSD:
1201    case llvm::Triple::NetBSD:
1202      SizeType = UnsignedInt;
1203      PtrDiffType = SignedInt;
1204      IntPtrType = SignedInt;
1205      break;
1206    default:
1207      break;
1208    }
1209
1210    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1211      LongDoubleWidth = LongDoubleAlign = 64;
1212      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1213    }
1214
1215    // PPC32 supports atomics up to 4 bytes.
1216    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1217  }
1218
1219  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1220    // This is the ELF definition, and is overridden by the Darwin sub-target
1221    return TargetInfo::PowerABIBuiltinVaList;
1222  }
1223};
1224} // end anonymous namespace.
1225
1226// Note: ABI differences may eventually require us to have a separate
1227// TargetInfo for little endian.
1228namespace {
1229class PPC64TargetInfo : public PPCTargetInfo {
1230public:
1231  PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1232    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1233    IntMaxType = SignedLong;
1234    UIntMaxType = UnsignedLong;
1235    Int64Type = SignedLong;
1236
1237    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1238      LongDoubleWidth = LongDoubleAlign = 64;
1239      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1240      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241                          "i64:64:64-f32:32:32-f64:64:64-"
1242                          "v128:128:128-n32:64";
1243    } else
1244      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1245                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1246                          "v128:128:128-n32:64";
1247
1248    // PPC64 supports atomics up to 8 bytes.
1249    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1250  }
1251  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1252    return TargetInfo::CharPtrBuiltinVaList;
1253  }
1254};
1255} // end anonymous namespace.
1256
1257
1258namespace {
1259class DarwinPPC32TargetInfo :
1260  public DarwinTargetInfo<PPC32TargetInfo> {
1261public:
1262  DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1263      : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1264    HasAlignMac68kSupport = true;
1265    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1266    PtrDiffType = SignedInt;    // for http://llvm.org/bugs/show_bug.cgi?id=15726
1267    LongLongAlign = 32;
1268    SuitableAlign = 128;
1269    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1270                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1271  }
1272  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1273    return TargetInfo::CharPtrBuiltinVaList;
1274  }
1275};
1276
1277class DarwinPPC64TargetInfo :
1278  public DarwinTargetInfo<PPC64TargetInfo> {
1279public:
1280  DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1281      : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1282    HasAlignMac68kSupport = true;
1283    SuitableAlign = 128;
1284    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1285                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1286  }
1287};
1288} // end anonymous namespace.
1289
1290namespace {
1291  static const unsigned NVPTXAddrSpaceMap[] = {
1292    1,    // opencl_global
1293    3,    // opencl_local
1294    4,    // opencl_constant
1295    1,    // cuda_device
1296    4,    // cuda_constant
1297    3,    // cuda_shared
1298  };
1299  class NVPTXTargetInfo : public TargetInfo {
1300    static const char * const GCCRegNames[];
1301    static const Builtin::Info BuiltinInfo[];
1302  public:
1303    NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1304      BigEndian = false;
1305      TLSSupported = false;
1306      LongWidth = LongAlign = 64;
1307      AddrSpaceMap = &NVPTXAddrSpaceMap;
1308      UseAddrSpaceMapMangling = true;
1309      // Define available target features
1310      // These must be defined in sorted order!
1311      NoAsmVariants = true;
1312    }
1313    virtual void getTargetDefines(const LangOptions &Opts,
1314                                  MacroBuilder &Builder) const {
1315      Builder.defineMacro("__PTX__");
1316      Builder.defineMacro("__NVPTX__");
1317    }
1318    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1319                                   unsigned &NumRecords) const {
1320      Records = BuiltinInfo;
1321      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1322    }
1323    virtual bool hasFeature(StringRef Feature) const {
1324      return Feature == "ptx" || Feature == "nvptx";
1325    }
1326
1327    virtual void getGCCRegNames(const char * const *&Names,
1328                                unsigned &NumNames) const;
1329    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1330                                  unsigned &NumAliases) const {
1331      // No aliases.
1332      Aliases = 0;
1333      NumAliases = 0;
1334    }
1335    virtual bool validateAsmConstraint(const char *&Name,
1336                                       TargetInfo::ConstraintInfo &Info) const {
1337      switch (*Name) {
1338      default: return false;
1339      case 'c':
1340      case 'h':
1341      case 'r':
1342      case 'l':
1343      case 'f':
1344      case 'd':
1345        Info.setAllowsRegister();
1346        return true;
1347      }
1348    }
1349    virtual const char *getClobbers() const {
1350      // FIXME: Is this really right?
1351      return "";
1352    }
1353    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1354      // FIXME: implement
1355      return TargetInfo::CharPtrBuiltinVaList;
1356    }
1357    virtual bool setCPU(const std::string &Name) {
1358      bool Valid = llvm::StringSwitch<bool>(Name)
1359        .Case("sm_20", true)
1360        .Case("sm_21", true)
1361        .Case("sm_30", true)
1362        .Case("sm_35", true)
1363        .Default(false);
1364
1365      return Valid;
1366    }
1367  };
1368
1369  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1370#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1371#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1372                                              ALL_LANGUAGES },
1373#include "clang/Basic/BuiltinsNVPTX.def"
1374  };
1375
1376  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1377    "r0"
1378  };
1379
1380  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1381                                     unsigned &NumNames) const {
1382    Names = GCCRegNames;
1383    NumNames = llvm::array_lengthof(GCCRegNames);
1384  }
1385
1386  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1387  public:
1388    NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1389      PointerWidth = PointerAlign = 32;
1390      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1391      DescriptionString
1392        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1393          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1394          "n16:32:64";
1395  }
1396  };
1397
1398  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1399  public:
1400    NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1401      PointerWidth = PointerAlign = 64;
1402      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1403      DescriptionString
1404        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1405          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1406          "n16:32:64";
1407  }
1408  };
1409}
1410
1411namespace {
1412
1413static const unsigned R600AddrSpaceMap[] = {
1414  1,    // opencl_global
1415  3,    // opencl_local
1416  2,    // opencl_constant
1417  1,    // cuda_device
1418  2,    // cuda_constant
1419  3     // cuda_shared
1420};
1421
1422static const char *DescriptionStringR600 =
1423  "e"
1424  "-p:32:32:32"
1425  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1426  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1427  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1428  "-n32:64";
1429
1430static const char *DescriptionStringR600DoubleOps =
1431  "e"
1432  "-p:32:32:32"
1433  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1434  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1435  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1436  "-n32:64";
1437
1438static const char *DescriptionStringSI =
1439  "e"
1440  "-p:64:64:64"
1441  "-p3:32:32:32"
1442  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1443  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1444  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1445  "-n32:64";
1446
1447class R600TargetInfo : public TargetInfo {
1448  /// \brief The GPU profiles supported by the R600 target.
1449  enum GPUKind {
1450    GK_NONE,
1451    GK_R600,
1452    GK_R600_DOUBLE_OPS,
1453    GK_R700,
1454    GK_R700_DOUBLE_OPS,
1455    GK_EVERGREEN,
1456    GK_EVERGREEN_DOUBLE_OPS,
1457    GK_NORTHERN_ISLANDS,
1458    GK_CAYMAN,
1459    GK_SOUTHERN_ISLANDS,
1460    GK_SEA_ISLANDS
1461  } GPU;
1462
1463public:
1464  R600TargetInfo(const llvm::Triple &Triple)
1465      : TargetInfo(Triple), GPU(GK_R600) {
1466    DescriptionString = DescriptionStringR600;
1467    AddrSpaceMap = &R600AddrSpaceMap;
1468    UseAddrSpaceMapMangling = true;
1469  }
1470
1471  virtual const char * getClobbers() const {
1472    return "";
1473  }
1474
1475  virtual void getGCCRegNames(const char * const *&Names,
1476                              unsigned &numNames) const  {
1477    Names = NULL;
1478    numNames = 0;
1479  }
1480
1481  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1482                                unsigned &NumAliases) const {
1483    Aliases = NULL;
1484    NumAliases = 0;
1485  }
1486
1487  virtual bool validateAsmConstraint(const char *&Name,
1488                                     TargetInfo::ConstraintInfo &info) const {
1489    return true;
1490  }
1491
1492  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1493                                 unsigned &NumRecords) const {
1494    Records = NULL;
1495    NumRecords = 0;
1496  }
1497
1498
1499  virtual void getTargetDefines(const LangOptions &Opts,
1500                                MacroBuilder &Builder) const {
1501    Builder.defineMacro("__R600__");
1502  }
1503
1504  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1505    return TargetInfo::CharPtrBuiltinVaList;
1506  }
1507
1508  virtual bool setCPU(const std::string &Name) {
1509    GPU = llvm::StringSwitch<GPUKind>(Name)
1510      .Case("r600" ,    GK_R600)
1511      .Case("rv610",    GK_R600)
1512      .Case("rv620",    GK_R600)
1513      .Case("rv630",    GK_R600)
1514      .Case("rv635",    GK_R600)
1515      .Case("rs780",    GK_R600)
1516      .Case("rs880",    GK_R600)
1517      .Case("rv670",    GK_R600_DOUBLE_OPS)
1518      .Case("rv710",    GK_R700)
1519      .Case("rv730",    GK_R700)
1520      .Case("rv740",    GK_R700_DOUBLE_OPS)
1521      .Case("rv770",    GK_R700_DOUBLE_OPS)
1522      .Case("palm",     GK_EVERGREEN)
1523      .Case("cedar",    GK_EVERGREEN)
1524      .Case("sumo",     GK_EVERGREEN)
1525      .Case("sumo2",    GK_EVERGREEN)
1526      .Case("redwood",  GK_EVERGREEN)
1527      .Case("juniper",  GK_EVERGREEN)
1528      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1529      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1530      .Case("barts",    GK_NORTHERN_ISLANDS)
1531      .Case("turks",    GK_NORTHERN_ISLANDS)
1532      .Case("caicos",   GK_NORTHERN_ISLANDS)
1533      .Case("cayman",   GK_CAYMAN)
1534      .Case("aruba",    GK_CAYMAN)
1535      .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1536      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1537      .Case("verde",    GK_SOUTHERN_ISLANDS)
1538      .Case("oland",    GK_SOUTHERN_ISLANDS)
1539      .Case("bonaire",  GK_SEA_ISLANDS)
1540      .Case("kabini",   GK_SEA_ISLANDS)
1541      .Case("kaveri",   GK_SEA_ISLANDS)
1542      .Default(GK_NONE);
1543
1544    if (GPU == GK_NONE) {
1545      return false;
1546    }
1547
1548    // Set the correct data layout
1549    switch (GPU) {
1550    case GK_NONE:
1551    case GK_R600:
1552    case GK_R700:
1553    case GK_EVERGREEN:
1554    case GK_NORTHERN_ISLANDS:
1555      DescriptionString = DescriptionStringR600;
1556      break;
1557    case GK_R600_DOUBLE_OPS:
1558    case GK_R700_DOUBLE_OPS:
1559    case GK_EVERGREEN_DOUBLE_OPS:
1560    case GK_CAYMAN:
1561      DescriptionString = DescriptionStringR600DoubleOps;
1562      break;
1563    case GK_SOUTHERN_ISLANDS:
1564    case GK_SEA_ISLANDS:
1565      DescriptionString = DescriptionStringSI;
1566      break;
1567    }
1568
1569    return true;
1570  }
1571};
1572
1573} // end anonymous namespace
1574
1575namespace {
1576// Namespace for x86 abstract base class
1577const Builtin::Info BuiltinInfo[] = {
1578#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1579#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1580                                              ALL_LANGUAGES },
1581#include "clang/Basic/BuiltinsX86.def"
1582};
1583
1584static const char* const GCCRegNames[] = {
1585  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1586  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1587  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1588  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1589  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1590  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1591  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1592  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1593  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1594};
1595
1596const TargetInfo::AddlRegName AddlRegNames[] = {
1597  { { "al", "ah", "eax", "rax" }, 0 },
1598  { { "bl", "bh", "ebx", "rbx" }, 3 },
1599  { { "cl", "ch", "ecx", "rcx" }, 2 },
1600  { { "dl", "dh", "edx", "rdx" }, 1 },
1601  { { "esi", "rsi" }, 4 },
1602  { { "edi", "rdi" }, 5 },
1603  { { "esp", "rsp" }, 7 },
1604  { { "ebp", "rbp" }, 6 },
1605};
1606
1607// X86 target abstract base class; x86-32 and x86-64 are very close, so
1608// most of the implementation can be shared.
1609class X86TargetInfo : public TargetInfo {
1610  enum X86SSEEnum {
1611    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1612  } SSELevel;
1613  enum MMX3DNowEnum {
1614    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1615  } MMX3DNowLevel;
1616  enum XOPEnum {
1617    NoXOP,
1618    SSE4A,
1619    FMA4,
1620    XOP
1621  } XOPLevel;
1622
1623  bool HasAES;
1624  bool HasPCLMUL;
1625  bool HasLZCNT;
1626  bool HasRDRND;
1627  bool HasBMI;
1628  bool HasBMI2;
1629  bool HasPOPCNT;
1630  bool HasRTM;
1631  bool HasPRFCHW;
1632  bool HasRDSEED;
1633  bool HasTBM;
1634  bool HasFMA;
1635  bool HasF16C;
1636  bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
1637  bool HasSHA;
1638  bool HasCX16;
1639
1640  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1641  ///
1642  /// Each enumeration represents a particular CPU supported by Clang. These
1643  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1644  enum CPUKind {
1645    CK_Generic,
1646
1647    /// \name i386
1648    /// i386-generation processors.
1649    //@{
1650    CK_i386,
1651    //@}
1652
1653    /// \name i486
1654    /// i486-generation processors.
1655    //@{
1656    CK_i486,
1657    CK_WinChipC6,
1658    CK_WinChip2,
1659    CK_C3,
1660    //@}
1661
1662    /// \name i586
1663    /// i586-generation processors, P5 microarchitecture based.
1664    //@{
1665    CK_i586,
1666    CK_Pentium,
1667    CK_PentiumMMX,
1668    //@}
1669
1670    /// \name i686
1671    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1672    //@{
1673    CK_i686,
1674    CK_PentiumPro,
1675    CK_Pentium2,
1676    CK_Pentium3,
1677    CK_Pentium3M,
1678    CK_PentiumM,
1679    CK_C3_2,
1680
1681    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1682    /// Clang however has some logic to suport this.
1683    // FIXME: Warn, deprecate, and potentially remove this.
1684    CK_Yonah,
1685    //@}
1686
1687    /// \name Netburst
1688    /// Netburst microarchitecture based processors.
1689    //@{
1690    CK_Pentium4,
1691    CK_Pentium4M,
1692    CK_Prescott,
1693    CK_Nocona,
1694    //@}
1695
1696    /// \name Core
1697    /// Core microarchitecture based processors.
1698    //@{
1699    CK_Core2,
1700
1701    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1702    /// codename which GCC no longer accepts as an option to -march, but Clang
1703    /// has some logic for recognizing it.
1704    // FIXME: Warn, deprecate, and potentially remove this.
1705    CK_Penryn,
1706    //@}
1707
1708    /// \name Atom
1709    /// Atom processors
1710    //@{
1711    CK_Atom,
1712    CK_Silvermont,
1713    //@}
1714
1715    /// \name Nehalem
1716    /// Nehalem microarchitecture based processors.
1717    //@{
1718    CK_Corei7,
1719    CK_Corei7AVX,
1720    CK_CoreAVXi,
1721    CK_CoreAVX2,
1722    //@}
1723
1724    /// \name Knights Landing
1725    /// Knights Landing processor.
1726    CK_KNL,
1727
1728    /// \name K6
1729    /// K6 architecture processors.
1730    //@{
1731    CK_K6,
1732    CK_K6_2,
1733    CK_K6_3,
1734    //@}
1735
1736    /// \name K7
1737    /// K7 architecture processors.
1738    //@{
1739    CK_Athlon,
1740    CK_AthlonThunderbird,
1741    CK_Athlon4,
1742    CK_AthlonXP,
1743    CK_AthlonMP,
1744    //@}
1745
1746    /// \name K8
1747    /// K8 architecture processors.
1748    //@{
1749    CK_Athlon64,
1750    CK_Athlon64SSE3,
1751    CK_AthlonFX,
1752    CK_K8,
1753    CK_K8SSE3,
1754    CK_Opteron,
1755    CK_OpteronSSE3,
1756    CK_AMDFAM10,
1757    //@}
1758
1759    /// \name Bobcat
1760    /// Bobcat architecture processors.
1761    //@{
1762    CK_BTVER1,
1763    CK_BTVER2,
1764    //@}
1765
1766    /// \name Bulldozer
1767    /// Bulldozer architecture processors.
1768    //@{
1769    CK_BDVER1,
1770    CK_BDVER2,
1771    CK_BDVER3,
1772    //@}
1773
1774    /// This specification is deprecated and will be removed in the future.
1775    /// Users should prefer \see CK_K8.
1776    // FIXME: Warn on this when the CPU is set to it.
1777    CK_x86_64,
1778    //@}
1779
1780    /// \name Geode
1781    /// Geode processors.
1782    //@{
1783    CK_Geode
1784    //@}
1785  } CPU;
1786
1787  enum FPMathKind {
1788    FP_Default,
1789    FP_SSE,
1790    FP_387
1791  } FPMath;
1792
1793public:
1794  X86TargetInfo(const llvm::Triple &Triple)
1795      : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1796        XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1797        HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1798        HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
1799        HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
1800        HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
1801        FPMath(FP_Default) {
1802    BigEndian = false;
1803    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1804  }
1805  virtual unsigned getFloatEvalMethod() const {
1806    // X87 evaluates with 80 bits "long double" precision.
1807    return SSELevel == NoSSE ? 2 : 0;
1808  }
1809  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1810                                 unsigned &NumRecords) const {
1811    Records = BuiltinInfo;
1812    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1813  }
1814  virtual void getGCCRegNames(const char * const *&Names,
1815                              unsigned &NumNames) const {
1816    Names = GCCRegNames;
1817    NumNames = llvm::array_lengthof(GCCRegNames);
1818  }
1819  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1820                                unsigned &NumAliases) const {
1821    Aliases = 0;
1822    NumAliases = 0;
1823  }
1824  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1825                                  unsigned &NumNames) const {
1826    Names = AddlRegNames;
1827    NumNames = llvm::array_lengthof(AddlRegNames);
1828  }
1829  virtual bool validateAsmConstraint(const char *&Name,
1830                                     TargetInfo::ConstraintInfo &info) const;
1831  virtual std::string convertConstraint(const char *&Constraint) const;
1832  virtual const char *getClobbers() const {
1833    return "~{dirflag},~{fpsr},~{flags}";
1834  }
1835  virtual void getTargetDefines(const LangOptions &Opts,
1836                                MacroBuilder &Builder) const;
1837  static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1838                          bool Enabled);
1839  static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1840                          bool Enabled);
1841  static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1842                          bool Enabled);
1843  virtual void setFeatureEnabled(llvm::StringMap<bool> &Features,
1844                                 StringRef Name, bool Enabled) const {
1845    setFeatureEnabledImpl(Features, Name, Enabled);
1846  }
1847  // This exists purely to cut down on the number of virtual calls in
1848  // getDefaultFeatures which calls this repeatedly.
1849  static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1850                                    StringRef Name, bool Enabled);
1851  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1852  virtual bool hasFeature(StringRef Feature) const;
1853  virtual bool handleTargetFeatures(std::vector<std::string> &Features,
1854                                    DiagnosticsEngine &Diags);
1855  virtual const char* getABI() const {
1856    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1857      return "avx";
1858    else if (getTriple().getArch() == llvm::Triple::x86 &&
1859             MMX3DNowLevel == NoMMX3DNow)
1860      return "no-mmx";
1861    return "";
1862  }
1863  virtual bool setCPU(const std::string &Name) {
1864    CPU = llvm::StringSwitch<CPUKind>(Name)
1865      .Case("i386", CK_i386)
1866      .Case("i486", CK_i486)
1867      .Case("winchip-c6", CK_WinChipC6)
1868      .Case("winchip2", CK_WinChip2)
1869      .Case("c3", CK_C3)
1870      .Case("i586", CK_i586)
1871      .Case("pentium", CK_Pentium)
1872      .Case("pentium-mmx", CK_PentiumMMX)
1873      .Case("i686", CK_i686)
1874      .Case("pentiumpro", CK_PentiumPro)
1875      .Case("pentium2", CK_Pentium2)
1876      .Case("pentium3", CK_Pentium3)
1877      .Case("pentium3m", CK_Pentium3M)
1878      .Case("pentium-m", CK_PentiumM)
1879      .Case("c3-2", CK_C3_2)
1880      .Case("yonah", CK_Yonah)
1881      .Case("pentium4", CK_Pentium4)
1882      .Case("pentium4m", CK_Pentium4M)
1883      .Case("prescott", CK_Prescott)
1884      .Case("nocona", CK_Nocona)
1885      .Case("core2", CK_Core2)
1886      .Case("penryn", CK_Penryn)
1887      .Case("atom", CK_Atom)
1888      .Case("slm", CK_Silvermont)
1889      .Case("corei7", CK_Corei7)
1890      .Case("corei7-avx", CK_Corei7AVX)
1891      .Case("core-avx-i", CK_CoreAVXi)
1892      .Case("core-avx2", CK_CoreAVX2)
1893      .Case("knl", CK_KNL)
1894      .Case("k6", CK_K6)
1895      .Case("k6-2", CK_K6_2)
1896      .Case("k6-3", CK_K6_3)
1897      .Case("athlon", CK_Athlon)
1898      .Case("athlon-tbird", CK_AthlonThunderbird)
1899      .Case("athlon-4", CK_Athlon4)
1900      .Case("athlon-xp", CK_AthlonXP)
1901      .Case("athlon-mp", CK_AthlonMP)
1902      .Case("athlon64", CK_Athlon64)
1903      .Case("athlon64-sse3", CK_Athlon64SSE3)
1904      .Case("athlon-fx", CK_AthlonFX)
1905      .Case("k8", CK_K8)
1906      .Case("k8-sse3", CK_K8SSE3)
1907      .Case("opteron", CK_Opteron)
1908      .Case("opteron-sse3", CK_OpteronSSE3)
1909      .Case("amdfam10", CK_AMDFAM10)
1910      .Case("btver1", CK_BTVER1)
1911      .Case("btver2", CK_BTVER2)
1912      .Case("bdver1", CK_BDVER1)
1913      .Case("bdver2", CK_BDVER2)
1914      .Case("bdver3", CK_BDVER3)
1915      .Case("x86-64", CK_x86_64)
1916      .Case("geode", CK_Geode)
1917      .Default(CK_Generic);
1918
1919    // Perform any per-CPU checks necessary to determine if this CPU is
1920    // acceptable.
1921    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1922    // invalid without explaining *why*.
1923    switch (CPU) {
1924    case CK_Generic:
1925      // No processor selected!
1926      return false;
1927
1928    case CK_i386:
1929    case CK_i486:
1930    case CK_WinChipC6:
1931    case CK_WinChip2:
1932    case CK_C3:
1933    case CK_i586:
1934    case CK_Pentium:
1935    case CK_PentiumMMX:
1936    case CK_i686:
1937    case CK_PentiumPro:
1938    case CK_Pentium2:
1939    case CK_Pentium3:
1940    case CK_Pentium3M:
1941    case CK_PentiumM:
1942    case CK_Yonah:
1943    case CK_C3_2:
1944    case CK_Pentium4:
1945    case CK_Pentium4M:
1946    case CK_Prescott:
1947    case CK_K6:
1948    case CK_K6_2:
1949    case CK_K6_3:
1950    case CK_Athlon:
1951    case CK_AthlonThunderbird:
1952    case CK_Athlon4:
1953    case CK_AthlonXP:
1954    case CK_AthlonMP:
1955    case CK_Geode:
1956      // Only accept certain architectures when compiling in 32-bit mode.
1957      if (getTriple().getArch() != llvm::Triple::x86)
1958        return false;
1959
1960      // Fallthrough
1961    case CK_Nocona:
1962    case CK_Core2:
1963    case CK_Penryn:
1964    case CK_Atom:
1965    case CK_Silvermont:
1966    case CK_Corei7:
1967    case CK_Corei7AVX:
1968    case CK_CoreAVXi:
1969    case CK_CoreAVX2:
1970    case CK_KNL:
1971    case CK_Athlon64:
1972    case CK_Athlon64SSE3:
1973    case CK_AthlonFX:
1974    case CK_K8:
1975    case CK_K8SSE3:
1976    case CK_Opteron:
1977    case CK_OpteronSSE3:
1978    case CK_AMDFAM10:
1979    case CK_BTVER1:
1980    case CK_BTVER2:
1981    case CK_BDVER1:
1982    case CK_BDVER2:
1983    case CK_BDVER3:
1984    case CK_x86_64:
1985      return true;
1986    }
1987    llvm_unreachable("Unhandled CPU kind");
1988  }
1989
1990  virtual bool setFPMath(StringRef Name);
1991
1992  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1993    // We accept all non-ARM calling conventions
1994    return (CC == CC_X86ThisCall ||
1995            CC == CC_X86FastCall ||
1996            CC == CC_X86StdCall ||
1997            CC == CC_C ||
1998            CC == CC_X86Pascal ||
1999            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2000  }
2001
2002  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2003    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2004  }
2005};
2006
2007bool X86TargetInfo::setFPMath(StringRef Name) {
2008  if (Name == "387") {
2009    FPMath = FP_387;
2010    return true;
2011  }
2012  if (Name == "sse") {
2013    FPMath = FP_SSE;
2014    return true;
2015  }
2016  return false;
2017}
2018
2019void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2020  // FIXME: This *really* should not be here.
2021
2022  // X86_64 always has SSE2.
2023  if (getTriple().getArch() == llvm::Triple::x86_64)
2024    setFeatureEnabledImpl(Features, "sse2", true);
2025
2026  switch (CPU) {
2027  case CK_Generic:
2028  case CK_i386:
2029  case CK_i486:
2030  case CK_i586:
2031  case CK_Pentium:
2032  case CK_i686:
2033  case CK_PentiumPro:
2034    break;
2035  case CK_PentiumMMX:
2036  case CK_Pentium2:
2037    setFeatureEnabledImpl(Features, "mmx", true);
2038    break;
2039  case CK_Pentium3:
2040  case CK_Pentium3M:
2041    setFeatureEnabledImpl(Features, "sse", true);
2042    break;
2043  case CK_PentiumM:
2044  case CK_Pentium4:
2045  case CK_Pentium4M:
2046  case CK_x86_64:
2047    setFeatureEnabledImpl(Features, "sse2", true);
2048    break;
2049  case CK_Yonah:
2050  case CK_Prescott:
2051  case CK_Nocona:
2052    setFeatureEnabledImpl(Features, "sse3", true);
2053    setFeatureEnabledImpl(Features, "cx16", true);
2054    break;
2055  case CK_Core2:
2056    setFeatureEnabledImpl(Features, "ssse3", true);
2057    setFeatureEnabledImpl(Features, "cx16", true);
2058    break;
2059  case CK_Penryn:
2060    setFeatureEnabledImpl(Features, "sse4.1", true);
2061    setFeatureEnabledImpl(Features, "cx16", true);
2062    break;
2063  case CK_Atom:
2064    setFeatureEnabledImpl(Features, "ssse3", true);
2065    setFeatureEnabledImpl(Features, "cx16", true);
2066    break;
2067  case CK_Silvermont:
2068    setFeatureEnabledImpl(Features, "sse4.2", true);
2069    setFeatureEnabledImpl(Features, "aes", true);
2070    setFeatureEnabledImpl(Features, "cx16", true);
2071    setFeatureEnabledImpl(Features, "pclmul", true);
2072    break;
2073  case CK_Corei7:
2074    setFeatureEnabledImpl(Features, "sse4.2", true);
2075    setFeatureEnabledImpl(Features, "cx16", true);
2076    break;
2077  case CK_Corei7AVX:
2078    setFeatureEnabledImpl(Features, "avx", true);
2079    setFeatureEnabledImpl(Features, "aes", true);
2080    setFeatureEnabledImpl(Features, "cx16", true);
2081    setFeatureEnabledImpl(Features, "pclmul", true);
2082    break;
2083  case CK_CoreAVXi:
2084    setFeatureEnabledImpl(Features, "avx", true);
2085    setFeatureEnabledImpl(Features, "aes", true);
2086    setFeatureEnabledImpl(Features, "pclmul", true);
2087    setFeatureEnabledImpl(Features, "rdrnd", true);
2088    setFeatureEnabledImpl(Features, "f16c", true);
2089    break;
2090  case CK_CoreAVX2:
2091    setFeatureEnabledImpl(Features, "avx2", true);
2092    setFeatureEnabledImpl(Features, "aes", true);
2093    setFeatureEnabledImpl(Features, "pclmul", true);
2094    setFeatureEnabledImpl(Features, "lzcnt", true);
2095    setFeatureEnabledImpl(Features, "rdrnd", true);
2096    setFeatureEnabledImpl(Features, "f16c", true);
2097    setFeatureEnabledImpl(Features, "bmi", true);
2098    setFeatureEnabledImpl(Features, "bmi2", true);
2099    setFeatureEnabledImpl(Features, "rtm", true);
2100    setFeatureEnabledImpl(Features, "fma", true);
2101    setFeatureEnabledImpl(Features, "cx16", true);
2102    break;
2103  case CK_KNL:
2104    setFeatureEnabledImpl(Features, "avx512f", true);
2105    setFeatureEnabledImpl(Features, "avx512cd", true);
2106    setFeatureEnabledImpl(Features, "avx512er", true);
2107    setFeatureEnabledImpl(Features, "avx512pf", true);
2108    setFeatureEnabledImpl(Features, "aes", true);
2109    setFeatureEnabledImpl(Features, "pclmul", true);
2110    setFeatureEnabledImpl(Features, "lzcnt", true);
2111    setFeatureEnabledImpl(Features, "rdrnd", true);
2112    setFeatureEnabledImpl(Features, "f16c", true);
2113    setFeatureEnabledImpl(Features, "bmi", true);
2114    setFeatureEnabledImpl(Features, "bmi2", true);
2115    setFeatureEnabledImpl(Features, "rtm", true);
2116    setFeatureEnabledImpl(Features, "fma", true);
2117    break;
2118  case CK_K6:
2119  case CK_WinChipC6:
2120    setFeatureEnabledImpl(Features, "mmx", true);
2121    break;
2122  case CK_K6_2:
2123  case CK_K6_3:
2124  case CK_WinChip2:
2125  case CK_C3:
2126    setFeatureEnabledImpl(Features, "3dnow", true);
2127    break;
2128  case CK_Athlon:
2129  case CK_AthlonThunderbird:
2130  case CK_Geode:
2131    setFeatureEnabledImpl(Features, "3dnowa", true);
2132    break;
2133  case CK_Athlon4:
2134  case CK_AthlonXP:
2135  case CK_AthlonMP:
2136    setFeatureEnabledImpl(Features, "sse", true);
2137    setFeatureEnabledImpl(Features, "3dnowa", true);
2138    break;
2139  case CK_K8:
2140  case CK_Opteron:
2141  case CK_Athlon64:
2142  case CK_AthlonFX:
2143    setFeatureEnabledImpl(Features, "sse2", true);
2144    setFeatureEnabledImpl(Features, "3dnowa", true);
2145    break;
2146  case CK_K8SSE3:
2147  case CK_OpteronSSE3:
2148  case CK_Athlon64SSE3:
2149    setFeatureEnabledImpl(Features, "sse3", true);
2150    setFeatureEnabledImpl(Features, "3dnowa", true);
2151    break;
2152  case CK_AMDFAM10:
2153    setFeatureEnabledImpl(Features, "sse3", true);
2154    setFeatureEnabledImpl(Features, "sse4a", true);
2155    setFeatureEnabledImpl(Features, "3dnowa", true);
2156    setFeatureEnabledImpl(Features, "lzcnt", true);
2157    setFeatureEnabledImpl(Features, "popcnt", true);
2158    break;
2159  case CK_BTVER1:
2160    setFeatureEnabledImpl(Features, "ssse3", true);
2161    setFeatureEnabledImpl(Features, "sse4a", true);
2162    setFeatureEnabledImpl(Features, "cx16", true);
2163    setFeatureEnabledImpl(Features, "lzcnt", true);
2164    setFeatureEnabledImpl(Features, "popcnt", true);
2165    setFeatureEnabledImpl(Features, "prfchw", true);
2166    break;
2167  case CK_BTVER2:
2168    setFeatureEnabledImpl(Features, "avx", true);
2169    setFeatureEnabledImpl(Features, "sse4a", true);
2170    setFeatureEnabledImpl(Features, "lzcnt", true);
2171    setFeatureEnabledImpl(Features, "aes", true);
2172    setFeatureEnabledImpl(Features, "pclmul", true);
2173    setFeatureEnabledImpl(Features, "prfchw", true);
2174    setFeatureEnabledImpl(Features, "bmi", true);
2175    setFeatureEnabledImpl(Features, "f16c", true);
2176    setFeatureEnabledImpl(Features, "cx16", true);
2177    break;
2178  case CK_BDVER1:
2179    setFeatureEnabledImpl(Features, "xop", true);
2180    setFeatureEnabledImpl(Features, "lzcnt", true);
2181    setFeatureEnabledImpl(Features, "aes", true);
2182    setFeatureEnabledImpl(Features, "pclmul", true);
2183    setFeatureEnabledImpl(Features, "prfchw", true);
2184    setFeatureEnabledImpl(Features, "cx16", true);
2185    break;
2186  case CK_BDVER2:
2187  case CK_BDVER3:
2188    setFeatureEnabledImpl(Features, "xop", true);
2189    setFeatureEnabledImpl(Features, "lzcnt", true);
2190    setFeatureEnabledImpl(Features, "aes", true);
2191    setFeatureEnabledImpl(Features, "pclmul", true);
2192    setFeatureEnabledImpl(Features, "prfchw", true);
2193    setFeatureEnabledImpl(Features, "bmi", true);
2194    setFeatureEnabledImpl(Features, "fma", true);
2195    setFeatureEnabledImpl(Features, "f16c", true);
2196    setFeatureEnabledImpl(Features, "tbm", true);
2197    setFeatureEnabledImpl(Features, "cx16", true);
2198    break;
2199  case CK_C3_2:
2200    setFeatureEnabledImpl(Features, "sse", true);
2201    break;
2202  }
2203}
2204
2205void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2206                                X86SSEEnum Level, bool Enabled) {
2207  if (Enabled) {
2208    switch (Level) {
2209    case AVX512F:
2210      Features["avx512f"] = true;
2211    case AVX2:
2212      Features["avx2"] = true;
2213    case AVX:
2214      Features["avx"] = true;
2215    case SSE42:
2216      Features["sse4.2"] = true;
2217    case SSE41:
2218      Features["sse4.1"] = true;
2219    case SSSE3:
2220      Features["ssse3"] = true;
2221    case SSE3:
2222      Features["sse3"] = true;
2223    case SSE2:
2224      Features["sse2"] = true;
2225    case SSE1:
2226      Features["sse"] = true;
2227    case NoSSE:
2228      break;
2229    }
2230    return;
2231  }
2232
2233  switch (Level) {
2234  case NoSSE:
2235  case SSE1:
2236    Features["sse"] = false;
2237  case SSE2:
2238    Features["sse2"] = Features["pclmul"] = Features["aes"] =
2239      Features["sha"] = false;
2240  case SSE3:
2241    Features["sse3"] = false;
2242    setXOPLevel(Features, NoXOP, false);
2243  case SSSE3:
2244    Features["ssse3"] = false;
2245  case SSE41:
2246    Features["sse4.1"] = false;
2247  case SSE42:
2248    Features["sse4.2"] = false;
2249  case AVX:
2250    Features["fma"] = Features["avx"] = Features["f16c"] = false;
2251    setXOPLevel(Features, FMA4, false);
2252  case AVX2:
2253    Features["avx2"] = false;
2254  case AVX512F:
2255    Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2256      Features["avx512pf"] = false;
2257  }
2258}
2259
2260void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2261                                MMX3DNowEnum Level, bool Enabled) {
2262  if (Enabled) {
2263    switch (Level) {
2264    case AMD3DNowAthlon:
2265      Features["3dnowa"] = true;
2266    case AMD3DNow:
2267      Features["3dnow"] = true;
2268    case MMX:
2269      Features["mmx"] = true;
2270    case NoMMX3DNow:
2271      break;
2272    }
2273    return;
2274  }
2275
2276  switch (Level) {
2277  case NoMMX3DNow:
2278  case MMX:
2279    Features["mmx"] = false;
2280  case AMD3DNow:
2281    Features["3dnow"] = false;
2282  case AMD3DNowAthlon:
2283    Features["3dnowa"] = false;
2284  }
2285}
2286
2287void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2288                                bool Enabled) {
2289  if (Enabled) {
2290    switch (Level) {
2291    case XOP:
2292      Features["xop"] = true;
2293    case FMA4:
2294      Features["fma4"] = true;
2295      setSSELevel(Features, AVX, true);
2296    case SSE4A:
2297      Features["sse4a"] = true;
2298      setSSELevel(Features, SSE3, true);
2299    case NoXOP:
2300      break;
2301    }
2302    return;
2303  }
2304
2305  switch (Level) {
2306  case NoXOP:
2307  case SSE4A:
2308    Features["sse4a"] = false;
2309  case FMA4:
2310    Features["fma4"] = false;
2311  case XOP:
2312    Features["xop"] = false;
2313  }
2314}
2315
2316void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2317                                          StringRef Name, bool Enabled) {
2318  // FIXME: This *really* should not be here.  We need some way of translating
2319  // options into llvm subtarget features.
2320  if (Name == "sse4")
2321    Name = "sse4.2";
2322
2323  Features[Name] = Enabled;
2324
2325  if (Name == "mmx") {
2326    setMMXLevel(Features, MMX, Enabled);
2327  } else if (Name == "sse") {
2328    setSSELevel(Features, SSE1, Enabled);
2329  } else if (Name == "sse2") {
2330    setSSELevel(Features, SSE2, Enabled);
2331  } else if (Name == "sse3") {
2332    setSSELevel(Features, SSE3, Enabled);
2333  } else if (Name == "ssse3") {
2334    setSSELevel(Features, SSSE3, Enabled);
2335  } else if (Name == "sse4.2") {
2336    setSSELevel(Features, SSE42, Enabled);
2337  } else if (Name == "sse4.1") {
2338    setSSELevel(Features, SSE41, Enabled);
2339  } else if (Name == "3dnow") {
2340    setMMXLevel(Features, AMD3DNow, Enabled);
2341  } else if (Name == "3dnowa") {
2342    setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2343  } else if (Name == "aes") {
2344    if (Enabled)
2345      setSSELevel(Features, SSE2, Enabled);
2346  } else if (Name == "pclmul") {
2347    if (Enabled)
2348      setSSELevel(Features, SSE2, Enabled);
2349  } else if (Name == "avx") {
2350    setSSELevel(Features, AVX, Enabled);
2351  } else if (Name == "avx2") {
2352    setSSELevel(Features, AVX2, Enabled);
2353  } else if (Name == "avx512f") {
2354    setSSELevel(Features, AVX512F, Enabled);
2355  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
2356    if (Enabled)
2357      setSSELevel(Features, AVX512F, Enabled);
2358  } else if (Name == "fma") {
2359    if (Enabled)
2360      setSSELevel(Features, AVX, Enabled);
2361  } else if (Name == "fma4") {
2362    setXOPLevel(Features, FMA4, Enabled);
2363  } else if (Name == "xop") {
2364    setXOPLevel(Features, XOP, Enabled);
2365  } else if (Name == "sse4a") {
2366    setXOPLevel(Features, SSE4A, Enabled);
2367  } else if (Name == "f16c") {
2368    if (Enabled)
2369      setSSELevel(Features, AVX, Enabled);
2370  } else if (Name == "sha") {
2371    if (Enabled)
2372      setSSELevel(Features, SSE2, Enabled);
2373  }
2374}
2375
2376/// handleTargetFeatures - Perform initialization based on the user
2377/// configured set of features.
2378bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2379                                         DiagnosticsEngine &Diags) {
2380  // Remember the maximum enabled sselevel.
2381  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2382    // Ignore disabled features.
2383    if (Features[i][0] == '-')
2384      continue;
2385
2386    StringRef Feature = StringRef(Features[i]).substr(1);
2387
2388    if (Feature == "aes") {
2389      HasAES = true;
2390      continue;
2391    }
2392
2393    if (Feature == "pclmul") {
2394      HasPCLMUL = true;
2395      continue;
2396    }
2397
2398    if (Feature == "lzcnt") {
2399      HasLZCNT = true;
2400      continue;
2401    }
2402
2403    if (Feature == "rdrnd") {
2404      HasRDRND = true;
2405      continue;
2406    }
2407
2408    if (Feature == "bmi") {
2409      HasBMI = true;
2410      continue;
2411    }
2412
2413    if (Feature == "bmi2") {
2414      HasBMI2 = true;
2415      continue;
2416    }
2417
2418    if (Feature == "popcnt") {
2419      HasPOPCNT = true;
2420      continue;
2421    }
2422
2423    if (Feature == "rtm") {
2424      HasRTM = true;
2425      continue;
2426    }
2427
2428    if (Feature == "prfchw") {
2429      HasPRFCHW = true;
2430      continue;
2431    }
2432
2433    if (Feature == "rdseed") {
2434      HasRDSEED = true;
2435      continue;
2436    }
2437
2438    if (Feature == "tbm") {
2439      HasTBM = true;
2440      continue;
2441    }
2442
2443    if (Feature == "fma") {
2444      HasFMA = true;
2445      continue;
2446    }
2447
2448    if (Feature == "f16c") {
2449      HasF16C = true;
2450      continue;
2451    }
2452
2453    if (Feature == "avx512cd") {
2454      HasAVX512CD = true;
2455      continue;
2456    }
2457
2458    if (Feature == "avx512er") {
2459      HasAVX512ER = true;
2460      continue;
2461    }
2462
2463    if (Feature == "avx512pf") {
2464      HasAVX512PF = true;
2465      continue;
2466    }
2467
2468    if (Feature == "sha") {
2469      HasSHA = true;
2470      continue;
2471    }
2472
2473    if (Feature == "cx16") {
2474      HasCX16 = true;
2475      continue;
2476    }
2477
2478    assert(Features[i][0] == '+' && "Invalid target feature!");
2479    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2480      .Case("avx512f", AVX512F)
2481      .Case("avx2", AVX2)
2482      .Case("avx", AVX)
2483      .Case("sse4.2", SSE42)
2484      .Case("sse4.1", SSE41)
2485      .Case("ssse3", SSSE3)
2486      .Case("sse3", SSE3)
2487      .Case("sse2", SSE2)
2488      .Case("sse", SSE1)
2489      .Default(NoSSE);
2490    SSELevel = std::max(SSELevel, Level);
2491
2492    MMX3DNowEnum ThreeDNowLevel =
2493      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2494        .Case("3dnowa", AMD3DNowAthlon)
2495        .Case("3dnow", AMD3DNow)
2496        .Case("mmx", MMX)
2497        .Default(NoMMX3DNow);
2498    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2499
2500    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2501        .Case("xop", XOP)
2502        .Case("fma4", FMA4)
2503        .Case("sse4a", SSE4A)
2504        .Default(NoXOP);
2505    XOPLevel = std::max(XOPLevel, XLevel);
2506  }
2507
2508  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2509  // Can't do this earlier because we need to be able to explicitly enable
2510  // popcnt and still disable sse4.2.
2511  if (!HasPOPCNT && SSELevel >= SSE42 &&
2512      std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2513    HasPOPCNT = true;
2514    Features.push_back("+popcnt");
2515  }
2516
2517  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2518  if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2519      std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2520    HasPRFCHW = true;
2521    Features.push_back("+prfchw");
2522  }
2523
2524  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2525  // matches the selected sse level.
2526  if (FPMath == FP_SSE && SSELevel < SSE1) {
2527    Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2528    return false;
2529  } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2530    Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2531    return false;
2532  }
2533
2534  // Don't tell the backend if we're turning off mmx; it will end up disabling
2535  // SSE, which we don't want.
2536  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2537  // then enable MMX.
2538  std::vector<std::string>::iterator it;
2539  it = std::find(Features.begin(), Features.end(), "-mmx");
2540  if (it != Features.end())
2541    Features.erase(it);
2542  else if (SSELevel > NoSSE)
2543    MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2544  return true;
2545}
2546
2547/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2548/// definitions for this particular subtarget.
2549void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2550                                     MacroBuilder &Builder) const {
2551  // Target identification.
2552  if (getTriple().getArch() == llvm::Triple::x86_64) {
2553    Builder.defineMacro("__amd64__");
2554    Builder.defineMacro("__amd64");
2555    Builder.defineMacro("__x86_64");
2556    Builder.defineMacro("__x86_64__");
2557  } else {
2558    DefineStd(Builder, "i386", Opts);
2559  }
2560
2561  // Subtarget options.
2562  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2563  // truly should be based on -mtune options.
2564  switch (CPU) {
2565  case CK_Generic:
2566    break;
2567  case CK_i386:
2568    // The rest are coming from the i386 define above.
2569    Builder.defineMacro("__tune_i386__");
2570    break;
2571  case CK_i486:
2572  case CK_WinChipC6:
2573  case CK_WinChip2:
2574  case CK_C3:
2575    defineCPUMacros(Builder, "i486");
2576    break;
2577  case CK_PentiumMMX:
2578    Builder.defineMacro("__pentium_mmx__");
2579    Builder.defineMacro("__tune_pentium_mmx__");
2580    // Fallthrough
2581  case CK_i586:
2582  case CK_Pentium:
2583    defineCPUMacros(Builder, "i586");
2584    defineCPUMacros(Builder, "pentium");
2585    break;
2586  case CK_Pentium3:
2587  case CK_Pentium3M:
2588  case CK_PentiumM:
2589    Builder.defineMacro("__tune_pentium3__");
2590    // Fallthrough
2591  case CK_Pentium2:
2592  case CK_C3_2:
2593    Builder.defineMacro("__tune_pentium2__");
2594    // Fallthrough
2595  case CK_PentiumPro:
2596    Builder.defineMacro("__tune_i686__");
2597    Builder.defineMacro("__tune_pentiumpro__");
2598    // Fallthrough
2599  case CK_i686:
2600    Builder.defineMacro("__i686");
2601    Builder.defineMacro("__i686__");
2602    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2603    Builder.defineMacro("__pentiumpro");
2604    Builder.defineMacro("__pentiumpro__");
2605    break;
2606  case CK_Pentium4:
2607  case CK_Pentium4M:
2608    defineCPUMacros(Builder, "pentium4");
2609    break;
2610  case CK_Yonah:
2611  case CK_Prescott:
2612  case CK_Nocona:
2613    defineCPUMacros(Builder, "nocona");
2614    break;
2615  case CK_Core2:
2616  case CK_Penryn:
2617    defineCPUMacros(Builder, "core2");
2618    break;
2619  case CK_Atom:
2620    defineCPUMacros(Builder, "atom");
2621    break;
2622  case CK_Silvermont:
2623    defineCPUMacros(Builder, "slm");
2624    break;
2625  case CK_Corei7:
2626  case CK_Corei7AVX:
2627  case CK_CoreAVXi:
2628  case CK_CoreAVX2:
2629    defineCPUMacros(Builder, "corei7");
2630    break;
2631  case CK_KNL:
2632    defineCPUMacros(Builder, "knl");
2633    break;
2634  case CK_K6_2:
2635    Builder.defineMacro("__k6_2__");
2636    Builder.defineMacro("__tune_k6_2__");
2637    // Fallthrough
2638  case CK_K6_3:
2639    if (CPU != CK_K6_2) {  // In case of fallthrough
2640      // FIXME: GCC may be enabling these in cases where some other k6
2641      // architecture is specified but -m3dnow is explicitly provided. The
2642      // exact semantics need to be determined and emulated here.
2643      Builder.defineMacro("__k6_3__");
2644      Builder.defineMacro("__tune_k6_3__");
2645    }
2646    // Fallthrough
2647  case CK_K6:
2648    defineCPUMacros(Builder, "k6");
2649    break;
2650  case CK_Athlon:
2651  case CK_AthlonThunderbird:
2652  case CK_Athlon4:
2653  case CK_AthlonXP:
2654  case CK_AthlonMP:
2655    defineCPUMacros(Builder, "athlon");
2656    if (SSELevel != NoSSE) {
2657      Builder.defineMacro("__athlon_sse__");
2658      Builder.defineMacro("__tune_athlon_sse__");
2659    }
2660    break;
2661  case CK_K8:
2662  case CK_K8SSE3:
2663  case CK_x86_64:
2664  case CK_Opteron:
2665  case CK_OpteronSSE3:
2666  case CK_Athlon64:
2667  case CK_Athlon64SSE3:
2668  case CK_AthlonFX:
2669    defineCPUMacros(Builder, "k8");
2670    break;
2671  case CK_AMDFAM10:
2672    defineCPUMacros(Builder, "amdfam10");
2673    break;
2674  case CK_BTVER1:
2675    defineCPUMacros(Builder, "btver1");
2676    break;
2677  case CK_BTVER2:
2678    defineCPUMacros(Builder, "btver2");
2679    break;
2680  case CK_BDVER1:
2681    defineCPUMacros(Builder, "bdver1");
2682    break;
2683  case CK_BDVER2:
2684    defineCPUMacros(Builder, "bdver2");
2685    break;
2686  case CK_BDVER3:
2687    defineCPUMacros(Builder, "bdver3");
2688    break;
2689  case CK_Geode:
2690    defineCPUMacros(Builder, "geode");
2691    break;
2692  }
2693
2694  // Target properties.
2695  Builder.defineMacro("__LITTLE_ENDIAN__");
2696  Builder.defineMacro("__REGISTER_PREFIX__", "");
2697
2698  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2699  // functions in glibc header files that use FP Stack inline asm which the
2700  // backend can't deal with (PR879).
2701  Builder.defineMacro("__NO_MATH_INLINES");
2702
2703  if (HasAES)
2704    Builder.defineMacro("__AES__");
2705
2706  if (HasPCLMUL)
2707    Builder.defineMacro("__PCLMUL__");
2708
2709  if (HasLZCNT)
2710    Builder.defineMacro("__LZCNT__");
2711
2712  if (HasRDRND)
2713    Builder.defineMacro("__RDRND__");
2714
2715  if (HasBMI)
2716    Builder.defineMacro("__BMI__");
2717
2718  if (HasBMI2)
2719    Builder.defineMacro("__BMI2__");
2720
2721  if (HasPOPCNT)
2722    Builder.defineMacro("__POPCNT__");
2723
2724  if (HasRTM)
2725    Builder.defineMacro("__RTM__");
2726
2727  if (HasPRFCHW)
2728    Builder.defineMacro("__PRFCHW__");
2729
2730  if (HasRDSEED)
2731    Builder.defineMacro("__RDSEED__");
2732
2733  if (HasTBM)
2734    Builder.defineMacro("__TBM__");
2735
2736  switch (XOPLevel) {
2737  case XOP:
2738    Builder.defineMacro("__XOP__");
2739  case FMA4:
2740    Builder.defineMacro("__FMA4__");
2741  case SSE4A:
2742    Builder.defineMacro("__SSE4A__");
2743  case NoXOP:
2744    break;
2745  }
2746
2747  if (HasFMA)
2748    Builder.defineMacro("__FMA__");
2749
2750  if (HasF16C)
2751    Builder.defineMacro("__F16C__");
2752
2753  if (HasAVX512CD)
2754    Builder.defineMacro("__AVX512CD__");
2755  if (HasAVX512ER)
2756    Builder.defineMacro("__AVX512ER__");
2757  if (HasAVX512PF)
2758    Builder.defineMacro("__AVX512PF__");
2759
2760  if (HasSHA)
2761    Builder.defineMacro("__SHA__");
2762
2763  if (HasCX16)
2764    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2765
2766  // Each case falls through to the previous one here.
2767  switch (SSELevel) {
2768  case AVX512F:
2769    Builder.defineMacro("__AVX512F__");
2770  case AVX2:
2771    Builder.defineMacro("__AVX2__");
2772  case AVX:
2773    Builder.defineMacro("__AVX__");
2774  case SSE42:
2775    Builder.defineMacro("__SSE4_2__");
2776  case SSE41:
2777    Builder.defineMacro("__SSE4_1__");
2778  case SSSE3:
2779    Builder.defineMacro("__SSSE3__");
2780  case SSE3:
2781    Builder.defineMacro("__SSE3__");
2782  case SSE2:
2783    Builder.defineMacro("__SSE2__");
2784    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2785  case SSE1:
2786    Builder.defineMacro("__SSE__");
2787    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2788  case NoSSE:
2789    break;
2790  }
2791
2792  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2793    switch (SSELevel) {
2794    case AVX512F:
2795    case AVX2:
2796    case AVX:
2797    case SSE42:
2798    case SSE41:
2799    case SSSE3:
2800    case SSE3:
2801    case SSE2:
2802      Builder.defineMacro("_M_IX86_FP", Twine(2));
2803      break;
2804    case SSE1:
2805      Builder.defineMacro("_M_IX86_FP", Twine(1));
2806      break;
2807    default:
2808      Builder.defineMacro("_M_IX86_FP", Twine(0));
2809    }
2810  }
2811
2812  // Each case falls through to the previous one here.
2813  switch (MMX3DNowLevel) {
2814  case AMD3DNowAthlon:
2815    Builder.defineMacro("__3dNOW_A__");
2816  case AMD3DNow:
2817    Builder.defineMacro("__3dNOW__");
2818  case MMX:
2819    Builder.defineMacro("__MMX__");
2820  case NoMMX3DNow:
2821    break;
2822  }
2823
2824  if (CPU >= CK_i486) {
2825    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2826    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2827    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2828  }
2829  if (CPU >= CK_i586)
2830    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2831}
2832
2833bool X86TargetInfo::hasFeature(StringRef Feature) const {
2834  return llvm::StringSwitch<bool>(Feature)
2835      .Case("aes", HasAES)
2836      .Case("avx", SSELevel >= AVX)
2837      .Case("avx2", SSELevel >= AVX2)
2838      .Case("avx512f", SSELevel >= AVX512F)
2839      .Case("avx512cd", HasAVX512CD)
2840      .Case("avx512er", HasAVX512ER)
2841      .Case("avx512pf", HasAVX512PF)
2842      .Case("bmi", HasBMI)
2843      .Case("bmi2", HasBMI2)
2844      .Case("cx16", HasCX16)
2845      .Case("f16c", HasF16C)
2846      .Case("fma", HasFMA)
2847      .Case("fma4", XOPLevel >= FMA4)
2848      .Case("tbm", HasTBM)
2849      .Case("lzcnt", HasLZCNT)
2850      .Case("rdrnd", HasRDRND)
2851      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2852      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2853      .Case("mmx", MMX3DNowLevel >= MMX)
2854      .Case("pclmul", HasPCLMUL)
2855      .Case("popcnt", HasPOPCNT)
2856      .Case("rtm", HasRTM)
2857      .Case("prfchw", HasPRFCHW)
2858      .Case("rdseed", HasRDSEED)
2859      .Case("sha", HasSHA)
2860      .Case("sse", SSELevel >= SSE1)
2861      .Case("sse2", SSELevel >= SSE2)
2862      .Case("sse3", SSELevel >= SSE3)
2863      .Case("ssse3", SSELevel >= SSSE3)
2864      .Case("sse4.1", SSELevel >= SSE41)
2865      .Case("sse4.2", SSELevel >= SSE42)
2866      .Case("sse4a", XOPLevel >= SSE4A)
2867      .Case("x86", true)
2868      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2869      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2870      .Case("xop", XOPLevel >= XOP)
2871      .Default(false);
2872}
2873
2874bool
2875X86TargetInfo::validateAsmConstraint(const char *&Name,
2876                                     TargetInfo::ConstraintInfo &Info) const {
2877  switch (*Name) {
2878  default: return false;
2879  case 'Y': // first letter of a pair:
2880    switch (*(Name+1)) {
2881    default: return false;
2882    case '0':  // First SSE register.
2883    case 't':  // Any SSE register, when SSE2 is enabled.
2884    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2885    case 'm':  // any MMX register, when inter-unit moves enabled.
2886      break;   // falls through to setAllowsRegister.
2887  }
2888  case 'a': // eax.
2889  case 'b': // ebx.
2890  case 'c': // ecx.
2891  case 'd': // edx.
2892  case 'S': // esi.
2893  case 'D': // edi.
2894  case 'A': // edx:eax.
2895  case 'f': // any x87 floating point stack register.
2896  case 't': // top of floating point stack.
2897  case 'u': // second from top of floating point stack.
2898  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2899  case 'y': // Any MMX register.
2900  case 'x': // Any SSE register.
2901  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2902  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2903  case 'l': // "Index" registers: any general register that can be used as an
2904            // index in a base+index memory access.
2905    Info.setAllowsRegister();
2906    return true;
2907  case 'C': // SSE floating point constant.
2908  case 'G': // x87 floating point constant.
2909  case 'e': // 32-bit signed integer constant for use with zero-extending
2910            // x86_64 instructions.
2911  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2912            // x86_64 instructions.
2913    return true;
2914  }
2915}
2916
2917
2918std::string
2919X86TargetInfo::convertConstraint(const char *&Constraint) const {
2920  switch (*Constraint) {
2921  case 'a': return std::string("{ax}");
2922  case 'b': return std::string("{bx}");
2923  case 'c': return std::string("{cx}");
2924  case 'd': return std::string("{dx}");
2925  case 'S': return std::string("{si}");
2926  case 'D': return std::string("{di}");
2927  case 'p': // address
2928    return std::string("im");
2929  case 't': // top of floating point stack.
2930    return std::string("{st}");
2931  case 'u': // second from top of floating point stack.
2932    return std::string("{st(1)}"); // second from top of floating point stack.
2933  default:
2934    return std::string(1, *Constraint);
2935  }
2936}
2937} // end anonymous namespace
2938
2939namespace {
2940// X86-32 generic target
2941class X86_32TargetInfo : public X86TargetInfo {
2942public:
2943  X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2944    DoubleAlign = LongLongAlign = 32;
2945    LongDoubleWidth = 96;
2946    LongDoubleAlign = 32;
2947    SuitableAlign = 128;
2948    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2949                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2950                        "a0:0:64-f80:32:32-n8:16:32-S128";
2951    SizeType = UnsignedInt;
2952    PtrDiffType = SignedInt;
2953    IntPtrType = SignedInt;
2954    RegParmMax = 3;
2955
2956    // Use fpret for all types.
2957    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2958                             (1 << TargetInfo::Double) |
2959                             (1 << TargetInfo::LongDouble));
2960
2961    // x86-32 has atomics up to 8 bytes
2962    // FIXME: Check that we actually have cmpxchg8b before setting
2963    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2964    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2965  }
2966  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2967    return TargetInfo::CharPtrBuiltinVaList;
2968  }
2969
2970  int getEHDataRegisterNumber(unsigned RegNo) const {
2971    if (RegNo == 0) return 0;
2972    if (RegNo == 1) return 2;
2973    return -1;
2974  }
2975  virtual bool validateInputSize(StringRef Constraint,
2976                                 unsigned Size) const {
2977    switch (Constraint[0]) {
2978    default: break;
2979    case 'a':
2980    case 'b':
2981    case 'c':
2982    case 'd':
2983      return Size <= 32;
2984    }
2985
2986    return true;
2987  }
2988};
2989} // end anonymous namespace
2990
2991namespace {
2992class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2993public:
2994  NetBSDI386TargetInfo(const llvm::Triple &Triple)
2995      : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
2996
2997  virtual unsigned getFloatEvalMethod() const {
2998    unsigned Major, Minor, Micro;
2999    getTriple().getOSVersion(Major, Minor, Micro);
3000    // New NetBSD uses the default rounding mode.
3001    if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3002      return X86_32TargetInfo::getFloatEvalMethod();
3003    // NetBSD before 6.99.26 defaults to "double" rounding.
3004    return 1;
3005  }
3006};
3007} // end anonymous namespace
3008
3009namespace {
3010class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3011public:
3012  OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3013      : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3014    SizeType = UnsignedLong;
3015    IntPtrType = SignedLong;
3016    PtrDiffType = SignedLong;
3017  }
3018};
3019} // end anonymous namespace
3020
3021namespace {
3022class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3023public:
3024  BitrigI386TargetInfo(const llvm::Triple &Triple)
3025      : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3026    SizeType = UnsignedLong;
3027    IntPtrType = SignedLong;
3028    PtrDiffType = SignedLong;
3029  }
3030};
3031} // end anonymous namespace
3032
3033namespace {
3034class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3035public:
3036  DarwinI386TargetInfo(const llvm::Triple &Triple)
3037      : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3038    LongDoubleWidth = 128;
3039    LongDoubleAlign = 128;
3040    SuitableAlign = 128;
3041    MaxVectorAlign = 256;
3042    SizeType = UnsignedLong;
3043    IntPtrType = SignedLong;
3044    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3045                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
3046                        "a0:0:64-f80:128:128-n8:16:32-S128";
3047    HasAlignMac68kSupport = true;
3048  }
3049
3050};
3051} // end anonymous namespace
3052
3053namespace {
3054// x86-32 Windows target
3055class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3056public:
3057  WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3058      : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3059    TLSSupported = false;
3060    WCharType = UnsignedShort;
3061    DoubleAlign = LongLongAlign = 64;
3062    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3063                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
3064                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
3065  }
3066  virtual void getTargetDefines(const LangOptions &Opts,
3067                                MacroBuilder &Builder) const {
3068    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3069  }
3070};
3071} // end anonymous namespace
3072
3073namespace {
3074
3075// x86-32 Windows Visual Studio target
3076class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
3077public:
3078  VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
3079      : WindowsX86_32TargetInfo(Triple) {
3080    LongDoubleWidth = LongDoubleAlign = 64;
3081    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3082  }
3083  virtual void getTargetDefines(const LangOptions &Opts,
3084                                MacroBuilder &Builder) const {
3085    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3086    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3087    // The value of the following reflects processor type.
3088    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3089    // We lost the original triple, so we use the default.
3090    Builder.defineMacro("_M_IX86", "600");
3091  }
3092};
3093} // end anonymous namespace
3094
3095namespace {
3096// x86-32 MinGW target
3097class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3098public:
3099  MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3100      : WindowsX86_32TargetInfo(Triple) {}
3101  virtual void getTargetDefines(const LangOptions &Opts,
3102                                MacroBuilder &Builder) const {
3103    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3104    DefineStd(Builder, "WIN32", Opts);
3105    DefineStd(Builder, "WINNT", Opts);
3106    Builder.defineMacro("_X86_");
3107    Builder.defineMacro("__MSVCRT__");
3108    Builder.defineMacro("__MINGW32__");
3109
3110    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3111    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3112    if (Opts.MicrosoftExt)
3113      // Provide "as-is" __declspec.
3114      Builder.defineMacro("__declspec", "__declspec");
3115    else
3116      // Provide alias of __attribute__ like mingw32-gcc.
3117      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3118  }
3119};
3120} // end anonymous namespace
3121
3122namespace {
3123// x86-32 Cygwin target
3124class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3125public:
3126  CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3127      : X86_32TargetInfo(Triple) {
3128    TLSSupported = false;
3129    WCharType = UnsignedShort;
3130    DoubleAlign = LongLongAlign = 64;
3131    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3132                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3133                        "a0:0:64-f80:32:32-n8:16:32-S32";
3134  }
3135  virtual void getTargetDefines(const LangOptions &Opts,
3136                                MacroBuilder &Builder) const {
3137    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3138    Builder.defineMacro("_X86_");
3139    Builder.defineMacro("__CYGWIN__");
3140    Builder.defineMacro("__CYGWIN32__");
3141    DefineStd(Builder, "unix", Opts);
3142    if (Opts.CPlusPlus)
3143      Builder.defineMacro("_GNU_SOURCE");
3144  }
3145};
3146} // end anonymous namespace
3147
3148namespace {
3149// x86-32 Haiku target
3150class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3151public:
3152  HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3153    SizeType = UnsignedLong;
3154    IntPtrType = SignedLong;
3155    PtrDiffType = SignedLong;
3156    ProcessIDType = SignedLong;
3157    this->UserLabelPrefix = "";
3158    this->TLSSupported = false;
3159  }
3160  virtual void getTargetDefines(const LangOptions &Opts,
3161                                MacroBuilder &Builder) const {
3162    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3163    Builder.defineMacro("__INTEL__");
3164    Builder.defineMacro("__HAIKU__");
3165  }
3166};
3167} // end anonymous namespace
3168
3169// RTEMS Target
3170template<typename Target>
3171class RTEMSTargetInfo : public OSTargetInfo<Target> {
3172protected:
3173  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3174                            MacroBuilder &Builder) const {
3175    // RTEMS defines; list based off of gcc output
3176
3177    Builder.defineMacro("__rtems__");
3178    Builder.defineMacro("__ELF__");
3179  }
3180
3181public:
3182  RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3183    this->UserLabelPrefix = "";
3184
3185    switch (Triple.getArch()) {
3186    default:
3187    case llvm::Triple::x86:
3188      // this->MCountName = ".mcount";
3189      break;
3190    case llvm::Triple::mips:
3191    case llvm::Triple::mipsel:
3192    case llvm::Triple::ppc:
3193    case llvm::Triple::ppc64:
3194    case llvm::Triple::ppc64le:
3195      // this->MCountName = "_mcount";
3196      break;
3197    case llvm::Triple::arm:
3198      // this->MCountName = "__mcount";
3199      break;
3200    }
3201  }
3202};
3203
3204namespace {
3205// x86-32 RTEMS target
3206class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3207public:
3208  RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3209    SizeType = UnsignedLong;
3210    IntPtrType = SignedLong;
3211    PtrDiffType = SignedLong;
3212    this->UserLabelPrefix = "";
3213  }
3214  virtual void getTargetDefines(const LangOptions &Opts,
3215                                MacroBuilder &Builder) const {
3216    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3217    Builder.defineMacro("__INTEL__");
3218    Builder.defineMacro("__rtems__");
3219  }
3220};
3221} // end anonymous namespace
3222
3223namespace {
3224// x86-64 generic target
3225class X86_64TargetInfo : public X86TargetInfo {
3226public:
3227  X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3228    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3229    LongDoubleWidth = 128;
3230    LongDoubleAlign = 128;
3231    LargeArrayMinWidth = 128;
3232    LargeArrayAlign = 128;
3233    SuitableAlign = 128;
3234    IntMaxType = SignedLong;
3235    UIntMaxType = UnsignedLong;
3236    Int64Type = SignedLong;
3237    RegParmMax = 6;
3238
3239    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3240                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3241                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3242
3243    // Use fpret only for long double.
3244    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3245
3246    // Use fp2ret for _Complex long double.
3247    ComplexLongDoubleUsesFP2Ret = true;
3248
3249    // x86-64 has atomics up to 16 bytes.
3250    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3251    // on CPUs with cmpxchg16b
3252    MaxAtomicPromoteWidth = 128;
3253    MaxAtomicInlineWidth = 64;
3254  }
3255  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3256    return TargetInfo::X86_64ABIBuiltinVaList;
3257  }
3258
3259  int getEHDataRegisterNumber(unsigned RegNo) const {
3260    if (RegNo == 0) return 0;
3261    if (RegNo == 1) return 1;
3262    return -1;
3263  }
3264
3265  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3266    return (CC == CC_C ||
3267            CC == CC_IntelOclBicc ||
3268            CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3269  }
3270
3271  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3272    return CC_C;
3273  }
3274
3275};
3276} // end anonymous namespace
3277
3278namespace {
3279// x86-64 Windows target
3280class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3281public:
3282  WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3283      : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3284    TLSSupported = false;
3285    WCharType = UnsignedShort;
3286    LongWidth = LongAlign = 32;
3287    DoubleAlign = LongLongAlign = 64;
3288    IntMaxType = SignedLongLong;
3289    UIntMaxType = UnsignedLongLong;
3290    Int64Type = SignedLongLong;
3291    SizeType = UnsignedLongLong;
3292    PtrDiffType = SignedLongLong;
3293    IntPtrType = SignedLongLong;
3294    this->UserLabelPrefix = "";
3295  }
3296  virtual void getTargetDefines(const LangOptions &Opts,
3297                                MacroBuilder &Builder) const {
3298    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3299    Builder.defineMacro("_WIN64");
3300  }
3301  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3302    return TargetInfo::CharPtrBuiltinVaList;
3303  }
3304  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3305    return (CC == CC_C ||
3306            CC == CC_IntelOclBicc ||
3307            CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3308  }
3309};
3310} // end anonymous namespace
3311
3312namespace {
3313// x86-64 Windows Visual Studio target
3314class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3315public:
3316  VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3317      : WindowsX86_64TargetInfo(Triple) {
3318    LongDoubleWidth = LongDoubleAlign = 64;
3319    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3320  }
3321  virtual void getTargetDefines(const LangOptions &Opts,
3322                                MacroBuilder &Builder) const {
3323    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3324    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3325    Builder.defineMacro("_M_X64");
3326    Builder.defineMacro("_M_AMD64");
3327  }
3328};
3329} // end anonymous namespace
3330
3331namespace {
3332// x86-64 MinGW target
3333class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3334public:
3335  MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3336      : WindowsX86_64TargetInfo(Triple) {}
3337  virtual void getTargetDefines(const LangOptions &Opts,
3338                                MacroBuilder &Builder) const {
3339    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3340    DefineStd(Builder, "WIN64", Opts);
3341    Builder.defineMacro("__MSVCRT__");
3342    Builder.defineMacro("__MINGW32__");
3343    Builder.defineMacro("__MINGW64__");
3344
3345    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3346    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3347    if (Opts.MicrosoftExt)
3348      // Provide "as-is" __declspec.
3349      Builder.defineMacro("__declspec", "__declspec");
3350    else
3351      // Provide alias of __attribute__ like mingw32-gcc.
3352      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3353  }
3354};
3355} // end anonymous namespace
3356
3357namespace {
3358class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3359public:
3360  DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3361      : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3362    Int64Type = SignedLongLong;
3363    MaxVectorAlign = 256;
3364  }
3365};
3366} // end anonymous namespace
3367
3368namespace {
3369class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3370public:
3371  OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3372      : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3373    IntMaxType = SignedLongLong;
3374    UIntMaxType = UnsignedLongLong;
3375    Int64Type = SignedLongLong;
3376  }
3377};
3378} // end anonymous namespace
3379
3380namespace {
3381class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3382public:
3383  BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3384      : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3385    IntMaxType = SignedLongLong;
3386    UIntMaxType = UnsignedLongLong;
3387    Int64Type = SignedLongLong;
3388  }
3389};
3390}
3391
3392namespace {
3393class AArch64TargetInfo : public TargetInfo {
3394  static const char * const GCCRegNames[];
3395  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3396
3397  enum FPUModeEnum {
3398    FPUMode,
3399    NeonMode
3400  };
3401
3402  unsigned FPU;
3403  static const Builtin::Info BuiltinInfo[];
3404
3405public:
3406  AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3407    BigEndian = false;
3408    LongWidth = LongAlign = 64;
3409    LongDoubleWidth = LongDoubleAlign = 128;
3410    PointerWidth = PointerAlign = 64;
3411    SuitableAlign = 128;
3412    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3413                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3414                        "f128:128:128-n32:64-S128";
3415
3416    WCharType = UnsignedInt;
3417    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3418
3419    // AArch64 backend supports 64-bit operations at the moment. In principle
3420    // 128-bit is possible if register-pairs are used.
3421    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3422
3423    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3424  }
3425  virtual void getTargetDefines(const LangOptions &Opts,
3426                                MacroBuilder &Builder) const {
3427    // GCC defines theses currently
3428    Builder.defineMacro("__aarch64__");
3429    Builder.defineMacro("__AARCH64EL__");
3430
3431    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3432
3433    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3434    // which was intended to be compatible with a 64-bit implementation. They
3435    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3436    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3437    Builder.defineMacro("__ARM_ACLE",         "101");
3438    Builder.defineMacro("__ARM_ARCH",         "8");
3439    Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3440
3441    Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3442    Builder.defineMacro("__ARM_FEATURE_CLZ");
3443    Builder.defineMacro("__ARM_FEATURE_FMA");
3444
3445    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3446    // 128-bit LDXP present, at which point this becomes 0x1f.
3447    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3448
3449    // 0xe implies support for half, single and double precision operations.
3450    Builder.defineMacro("__ARM_FP", "0xe");
3451
3452    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3453    // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3454    Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3455
3456    if (Opts.FastMath || Opts.FiniteMathOnly)
3457      Builder.defineMacro("__ARM_FP_FAST");
3458
3459    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3460      Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3461
3462    Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3463                        Opts.ShortWChar ? "2" : "4");
3464
3465    Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3466                        Opts.ShortEnums ? "1" : "4");
3467
3468    if (BigEndian)
3469      Builder.defineMacro("__AARCH_BIG_ENDIAN");
3470
3471    if (FPU == NeonMode) {
3472      Builder.defineMacro("__AARCH_FEATURE_ADVSIMD");
3473
3474      // 64-bit NEON supports half, single and double precision operations.
3475      Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe");
3476    }
3477  }
3478  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3479                                 unsigned &NumRecords) const {
3480    Records = BuiltinInfo;
3481    NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3482  }
3483  virtual bool hasFeature(StringRef Feature) const {
3484    return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);
3485  }
3486
3487  virtual bool setCPU(const std::string &Name) {
3488    return llvm::StringSwitch<bool>(Name)
3489             .Case("generic", true)
3490             .Cases("cortex-a53", "cortex-a57", true)
3491             .Default(false);
3492  }
3493
3494  virtual bool handleTargetFeatures(std::vector<std::string> &Features,
3495                                    DiagnosticsEngine &Diags) {
3496    FPU = FPUMode;
3497    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3498      if (Features[i] == "+neon")
3499        FPU = NeonMode;
3500    }
3501    return true;
3502  }
3503
3504  virtual void getGCCRegNames(const char *const *&Names,
3505                              unsigned &NumNames) const;
3506  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3507                                unsigned &NumAliases) const;
3508
3509  virtual bool isCLZForZeroUndef() const { return false; }
3510
3511  virtual bool validateAsmConstraint(const char *&Name,
3512                                     TargetInfo::ConstraintInfo &Info) const {
3513    switch (*Name) {
3514    default: return false;
3515    case 'w': // An FP/SIMD vector register
3516      Info.setAllowsRegister();
3517      return true;
3518    case 'I': // Constant that can be used with an ADD instruction
3519    case 'J': // Constant that can be used with a SUB instruction
3520    case 'K': // Constant that can be used with a 32-bit logical instruction
3521    case 'L': // Constant that can be used with a 64-bit logical instruction
3522    case 'M': // Constant that can be used as a 32-bit MOV immediate
3523    case 'N': // Constant that can be used as a 64-bit MOV immediate
3524    case 'Y': // Floating point constant zero
3525    case 'Z': // Integer constant zero
3526      return true;
3527    case 'Q': // A memory reference with base register and no offset
3528      Info.setAllowsMemory();
3529      return true;
3530    case 'S': // A symbolic address
3531      Info.setAllowsRegister();
3532      return true;
3533    case 'U':
3534      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3535      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3536      // Usa: An absolute symbolic address
3537      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3538      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3539    }
3540  }
3541
3542  virtual const char *getClobbers() const {
3543    // There are no AArch64 clobbers shared by all asm statements.
3544    return "";
3545  }
3546
3547  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3548    return TargetInfo::AArch64ABIBuiltinVaList;
3549  }
3550};
3551
3552const char * const AArch64TargetInfo::GCCRegNames[] = {
3553  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3554  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3555  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3556  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3557
3558  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3559  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3560  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3561  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3562
3563  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3564  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3565  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3566  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3567
3568  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3569  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3570  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3571  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3572
3573  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3574  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3575  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3576  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3577
3578  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3579  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3580  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3581  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3582
3583  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3584  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3585  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3586  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3587};
3588
3589void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3590                                       unsigned &NumNames) const {
3591  Names = GCCRegNames;
3592  NumNames = llvm::array_lengthof(GCCRegNames);
3593}
3594
3595const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3596  { { "x16" }, "ip0"},
3597  { { "x17" }, "ip1"},
3598  { { "x29" }, "fp" },
3599  { { "x30" }, "lr" }
3600};
3601
3602void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3603                                         unsigned &NumAliases) const {
3604  Aliases = GCCRegAliases;
3605  NumAliases = llvm::array_lengthof(GCCRegAliases);
3606
3607}
3608
3609const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3610#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3611#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3612                                              ALL_LANGUAGES },
3613#include "clang/Basic/BuiltinsAArch64.def"
3614};
3615
3616} // end anonymous namespace
3617
3618namespace {
3619class ARMTargetInfo : public TargetInfo {
3620  // Possible FPU choices.
3621  enum FPUMode {
3622    VFP2FPU = (1 << 0),
3623    VFP3FPU = (1 << 1),
3624    VFP4FPU = (1 << 2),
3625    NeonFPU = (1 << 3),
3626    FPARMV8 = (1 << 4)
3627  };
3628
3629  // Possible HWDiv features.
3630  enum HWDivMode {
3631    HWDivThumb = (1 << 0),
3632    HWDivARM = (1 << 1)
3633  };
3634
3635  static bool FPUModeIsVFP(FPUMode Mode) {
3636    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3637  }
3638
3639  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3640  static const char * const GCCRegNames[];
3641
3642  std::string ABI, CPU;
3643
3644  enum {
3645    FP_Default,
3646    FP_VFP,
3647    FP_Neon
3648  } FPMath;
3649
3650  unsigned FPU : 5;
3651
3652  unsigned IsAAPCS : 1;
3653  unsigned IsThumb : 1;
3654  unsigned HWDiv : 2;
3655
3656  // Initialized via features.
3657  unsigned SoftFloat : 1;
3658  unsigned SoftFloatABI : 1;
3659
3660  unsigned CRC : 1;
3661
3662  static const Builtin::Info BuiltinInfo[];
3663
3664  static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3665    // On linux, binaries targeting old cpus call functions in libgcc to
3666    // perform atomic operations. The implementation in libgcc then calls into
3667    // the kernel which on armv6 and newer uses ldrex and strex. The net result
3668    // is that if we assume the kernel is at least as recent as the hardware,
3669    // it is safe to use atomic instructions on armv6 and newer.
3670    if (!T.isOSLinux() &&
3671        T.getOS() != llvm::Triple::FreeBSD &&
3672        T.getOS() != llvm::Triple::Bitrig)
3673      return false;
3674    StringRef ArchName = T.getArchName();
3675    if (T.getArch() == llvm::Triple::arm) {
3676      if (!ArchName.startswith("armv"))
3677        return false;
3678      StringRef VersionStr = ArchName.substr(4);
3679      unsigned Version;
3680      if (VersionStr.getAsInteger(10, Version))
3681        return false;
3682      return Version >= 6;
3683    }
3684    assert(T.getArch() == llvm::Triple::thumb);
3685    if (!ArchName.startswith("thumbv"))
3686      return false;
3687    StringRef VersionStr = ArchName.substr(6);
3688    unsigned Version;
3689    if (VersionStr.getAsInteger(10, Version))
3690      return false;
3691    return Version >= 7;
3692  }
3693
3694public:
3695  ARMTargetInfo(const llvm::Triple &Triple)
3696      : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3697        FPMath(FP_Default), IsAAPCS(true) {
3698    BigEndian = false;
3699    SizeType = UnsignedInt;
3700    PtrDiffType = SignedInt;
3701    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3702    WCharType = UnsignedInt;
3703
3704    // {} in inline assembly are neon specifiers, not assembly variant
3705    // specifiers.
3706    NoAsmVariants = true;
3707
3708    // FIXME: Should we just treat this as a feature?
3709    IsThumb = getTriple().getArchName().startswith("thumb");
3710    if (IsThumb) {
3711      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3712      // so set preferred for small types to 32.
3713      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3714                           "i64:64:64-f32:32:32-f64:64:64-"
3715                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3716    } else {
3717      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3718                           "i64:64:64-f32:32:32-f64:64:64-"
3719                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3720    }
3721
3722    // ARM targets default to using the ARM C++ ABI.
3723    TheCXXABI.set(TargetCXXABI::GenericARM);
3724
3725    // ARM has atomics up to 8 bytes
3726    MaxAtomicPromoteWidth = 64;
3727    if (shouldUseInlineAtomic(getTriple()))
3728      MaxAtomicInlineWidth = 64;
3729
3730    // Do force alignment of members that follow zero length bitfields.  If
3731    // the alignment of the zero-length bitfield is greater than the member
3732    // that follows it, `bar', `bar' will be aligned as the  type of the
3733    // zero length bitfield.
3734    UseZeroLengthBitfieldAlignment = true;
3735  }
3736  virtual const char *getABI() const { return ABI.c_str(); }
3737  virtual bool setABI(const std::string &Name) {
3738    ABI = Name;
3739
3740    // The defaults (above) are for AAPCS, check if we need to change them.
3741    //
3742    // FIXME: We need support for -meabi... we could just mangle it into the
3743    // name.
3744    if (Name == "apcs-gnu") {
3745      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3746      // size_t is unsigned int on FreeBSD.
3747      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3748        SizeType = UnsignedLong;
3749
3750      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3751      WCharType = SignedInt;
3752
3753      // Do not respect the alignment of bit-field types when laying out
3754      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3755      UseBitFieldTypeAlignment = false;
3756
3757      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3758      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3759      /// gcc.
3760      ZeroLengthBitfieldBoundary = 32;
3761
3762      IsAAPCS = false;
3763
3764      if (IsThumb) {
3765        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3766        // so set preferred for small types to 32.
3767        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3768                             "i64:32:64-f32:32:32-f64:32:64-"
3769                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3770      } else {
3771        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3772                             "i64:32:64-f32:32:32-f64:32:64-"
3773                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3774      }
3775
3776      // FIXME: Override "preferred align" for double and long long.
3777    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3778      // size_t is unsigned long on Darwin.
3779      if (getTriple().isOSDarwin())
3780        SizeType = UnsignedLong;
3781      IsAAPCS = true;
3782      // FIXME: Enumerated types are variable width in straight AAPCS.
3783    } else if (Name == "aapcs-linux") {
3784      IsAAPCS = true;
3785    } else
3786      return false;
3787
3788    return true;
3789  }
3790
3791  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3792    StringRef ArchName = getTriple().getArchName();
3793    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3794      Features["vfp2"] = true;
3795    else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3796             CPU == "cortex-a9-mp") {
3797      Features["vfp3"] = true;
3798      Features["neon"] = true;
3799    }
3800    else if (CPU == "cortex-a5") {
3801      Features["vfp4"] = true;
3802      Features["neon"] = true;
3803    } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") {
3804      Features["vfp4"] = true;
3805      Features["neon"] = true;
3806      Features["hwdiv"] = true;
3807      Features["hwdiv-arm"] = true;
3808    } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3809      Features["fp-armv8"] = true;
3810      Features["neon"] = true;
3811      Features["hwdiv"] = true;
3812      Features["hwdiv-arm"] = true;
3813      Features["crc"] = true;
3814    } else if (CPU == "cortex-r5" || CPU == "cortex-m3" ||
3815               CPU == "cortex-m4" ||
3816               // Enable the hwdiv extension for all v8a AArch32 cores by
3817               // default.
3818               ArchName == "armv8a" || ArchName == "armv8" ||
3819               ArchName == "thumbv8a" || ArchName == "thumbv8") {
3820      Features["hwdiv"] = true;
3821      Features["hwdiv-arm"] = true;
3822    }
3823  }
3824
3825  virtual bool handleTargetFeatures(std::vector<std::string> &Features,
3826                                    DiagnosticsEngine &Diags) {
3827    FPU = 0;
3828    CRC = 0;
3829    SoftFloat = SoftFloatABI = false;
3830    HWDiv = 0;
3831    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3832      if (Features[i] == "+soft-float")
3833        SoftFloat = true;
3834      else if (Features[i] == "+soft-float-abi")
3835        SoftFloatABI = true;
3836      else if (Features[i] == "+vfp2")
3837        FPU |= VFP2FPU;
3838      else if (Features[i] == "+vfp3")
3839        FPU |= VFP3FPU;
3840      else if (Features[i] == "+vfp4")
3841        FPU |= VFP4FPU;
3842      else if (Features[i] == "+fp-armv8")
3843        FPU |= FPARMV8;
3844      else if (Features[i] == "+neon")
3845        FPU |= NeonFPU;
3846      else if (Features[i] == "+hwdiv")
3847        HWDiv |= HWDivThumb;
3848      else if (Features[i] == "+hwdiv-arm")
3849        HWDiv |= HWDivARM;
3850      else if (Features[i] == "+crc")
3851        CRC = 1;
3852    }
3853
3854    if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3855      Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3856      return false;
3857    }
3858
3859    if (FPMath == FP_Neon)
3860      Features.push_back("+neonfp");
3861    else if (FPMath == FP_VFP)
3862      Features.push_back("-neonfp");
3863
3864    // Remove front-end specific options which the backend handles differently.
3865    std::vector<std::string>::iterator it;
3866    it = std::find(Features.begin(), Features.end(), "+soft-float");
3867    if (it != Features.end())
3868      Features.erase(it);
3869    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3870    if (it != Features.end())
3871      Features.erase(it);
3872    return true;
3873  }
3874
3875  virtual bool hasFeature(StringRef Feature) const {
3876    return llvm::StringSwitch<bool>(Feature)
3877        .Case("arm", true)
3878        .Case("softfloat", SoftFloat)
3879        .Case("thumb", IsThumb)
3880        .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3881        .Case("hwdiv", HWDiv & HWDivThumb)
3882        .Case("hwdiv-arm", HWDiv & HWDivARM)
3883        .Default(false);
3884  }
3885  // FIXME: Should we actually have some table instead of these switches?
3886  static const char *getCPUDefineSuffix(StringRef Name) {
3887    return llvm::StringSwitch<const char*>(Name)
3888      .Cases("arm8", "arm810", "4")
3889      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3890      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3891      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3892      .Case("ep9312", "4T")
3893      .Cases("arm10tdmi", "arm1020t", "5T")
3894      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3895      .Case("arm926ej-s", "5TEJ")
3896      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3897      .Cases("xscale", "iwmmxt", "5TE")
3898      .Case("arm1136j-s", "6J")
3899      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3900      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3901      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3902      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3903      .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A")
3904      .Cases("cortex-r4", "cortex-r5", "7R")
3905      .Case("cortex-a9-mp", "7F")
3906      .Case("swift", "7S")
3907      .Cases("cortex-m3", "cortex-m4", "7M")
3908      .Case("cortex-m0", "6M")
3909      .Cases("cortex-a53", "cortex-a57", "8A")
3910      .Default(0);
3911  }
3912  static const char *getCPUProfile(StringRef Name) {
3913    return llvm::StringSwitch<const char*>(Name)
3914      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
3915      .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A")
3916      .Cases("cortex-a53", "cortex-a57", "A")
3917      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3918      .Cases("cortex-r4", "cortex-r5", "R")
3919      .Default("");
3920  }
3921  virtual bool setCPU(const std::string &Name) {
3922    if (!getCPUDefineSuffix(Name))
3923      return false;
3924
3925    CPU = Name;
3926    return true;
3927  }
3928  virtual bool setFPMath(StringRef Name);
3929  virtual void getTargetDefines(const LangOptions &Opts,
3930                                MacroBuilder &Builder) const {
3931    // Target identification.
3932    Builder.defineMacro("__arm");
3933    Builder.defineMacro("__arm__");
3934
3935    // Target properties.
3936    Builder.defineMacro("__ARMEL__");
3937    Builder.defineMacro("__LITTLE_ENDIAN__");
3938    Builder.defineMacro("__REGISTER_PREFIX__", "");
3939
3940    StringRef CPUArch = getCPUDefineSuffix(CPU);
3941    unsigned int CPUArchVer;
3942    if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
3943      llvm_unreachable("Invalid char for architecture version number");
3944    }
3945    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3946    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3947    StringRef CPUProfile = getCPUProfile(CPU);
3948    if (!CPUProfile.empty())
3949      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3950
3951    // Subtarget options.
3952
3953    // FIXME: It's more complicated than this and we don't really support
3954    // interworking.
3955    if (5 <= CPUArchVer && CPUArchVer <= 7)
3956      Builder.defineMacro("__THUMB_INTERWORK__");
3957
3958    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3959      // Embedded targets on Darwin follow AAPCS, but not EABI.
3960      if (!getTriple().isOSDarwin())
3961        Builder.defineMacro("__ARM_EABI__");
3962      Builder.defineMacro("__ARM_PCS", "1");
3963
3964      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3965        Builder.defineMacro("__ARM_PCS_VFP", "1");
3966    }
3967
3968    if (SoftFloat)
3969      Builder.defineMacro("__SOFTFP__");
3970
3971    if (CPU == "xscale")
3972      Builder.defineMacro("__XSCALE__");
3973
3974    if (IsThumb) {
3975      Builder.defineMacro("__THUMBEL__");
3976      Builder.defineMacro("__thumb__");
3977      if (CPUArch == "6T2" || CPUArchVer == 7)
3978        Builder.defineMacro("__thumb2__");
3979    }
3980    if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
3981      Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
3982
3983    // Note, this is always on in gcc, even though it doesn't make sense.
3984    Builder.defineMacro("__APCS_32__");
3985
3986    if (FPUModeIsVFP((FPUMode) FPU)) {
3987      Builder.defineMacro("__VFP_FP__");
3988      if (FPU & VFP2FPU)
3989        Builder.defineMacro("__ARM_VFPV2__");
3990      if (FPU & VFP3FPU)
3991        Builder.defineMacro("__ARM_VFPV3__");
3992      if (FPU & VFP4FPU)
3993        Builder.defineMacro("__ARM_VFPV4__");
3994    }
3995
3996    // This only gets set when Neon instructions are actually available, unlike
3997    // the VFP define, hence the soft float and arch check. This is subtly
3998    // different from gcc, we follow the intent which was that it should be set
3999    // when Neon instructions are actually available.
4000    if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7)
4001      Builder.defineMacro("__ARM_NEON__");
4002
4003    if (CRC)
4004      Builder.defineMacro("__ARM_FEATURE_CRC32");
4005
4006    if (CPUArchVer >= 6 && CPUArch != "6M") {
4007      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4008      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4009      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4010      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4011    }
4012  }
4013  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4014                                 unsigned &NumRecords) const {
4015    Records = BuiltinInfo;
4016    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4017  }
4018  virtual bool isCLZForZeroUndef() const { return false; }
4019  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4020    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4021  }
4022  virtual void getGCCRegNames(const char * const *&Names,
4023                              unsigned &NumNames) const;
4024  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4025                                unsigned &NumAliases) const;
4026  virtual bool validateAsmConstraint(const char *&Name,
4027                                     TargetInfo::ConstraintInfo &Info) const {
4028    switch (*Name) {
4029    default: break;
4030    case 'l': // r0-r7
4031    case 'h': // r8-r15
4032    case 'w': // VFP Floating point register single precision
4033    case 'P': // VFP Floating point register double precision
4034      Info.setAllowsRegister();
4035      return true;
4036    case 'Q': // A memory address that is a single base register.
4037      Info.setAllowsMemory();
4038      return true;
4039    case 'U': // a memory reference...
4040      switch (Name[1]) {
4041      case 'q': // ...ARMV4 ldrsb
4042      case 'v': // ...VFP load/store (reg+constant offset)
4043      case 'y': // ...iWMMXt load/store
4044      case 't': // address valid for load/store opaque types wider
4045                // than 128-bits
4046      case 'n': // valid address for Neon doubleword vector load/store
4047      case 'm': // valid address for Neon element and structure load/store
4048      case 's': // valid address for non-offset loads/stores of quad-word
4049                // values in four ARM registers
4050        Info.setAllowsMemory();
4051        Name++;
4052        return true;
4053      }
4054    }
4055    return false;
4056  }
4057  virtual std::string convertConstraint(const char *&Constraint) const {
4058    std::string R;
4059    switch (*Constraint) {
4060    case 'U':   // Two-character constraint; add "^" hint for later parsing.
4061      R = std::string("^") + std::string(Constraint, 2);
4062      Constraint++;
4063      break;
4064    case 'p': // 'p' should be translated to 'r' by default.
4065      R = std::string("r");
4066      break;
4067    default:
4068      return std::string(1, *Constraint);
4069    }
4070    return R;
4071  }
4072  virtual bool validateConstraintModifier(StringRef Constraint,
4073                                          const char Modifier,
4074                                          unsigned Size) const {
4075    bool isOutput = (Constraint[0] == '=');
4076    bool isInOut = (Constraint[0] == '+');
4077
4078    // Strip off constraint modifiers.
4079    while (Constraint[0] == '=' ||
4080           Constraint[0] == '+' ||
4081           Constraint[0] == '&')
4082      Constraint = Constraint.substr(1);
4083
4084    switch (Constraint[0]) {
4085    default: break;
4086    case 'r': {
4087      switch (Modifier) {
4088      default:
4089        return (isInOut || isOutput || Size <= 32);
4090      case 'q':
4091        // A register of size 32 cannot fit a vector type.
4092        return false;
4093      }
4094    }
4095    }
4096
4097    return true;
4098  }
4099  virtual const char *getClobbers() const {
4100    // FIXME: Is this really right?
4101    return "";
4102  }
4103
4104  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
4105    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4106  }
4107
4108  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4109    if (RegNo == 0) return 0;
4110    if (RegNo == 1) return 1;
4111    return -1;
4112  }
4113};
4114
4115bool ARMTargetInfo::setFPMath(StringRef Name) {
4116  if (Name == "neon") {
4117    FPMath = FP_Neon;
4118    return true;
4119  } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4120             Name == "vfp4") {
4121    FPMath = FP_VFP;
4122    return true;
4123  }
4124  return false;
4125}
4126
4127const char * const ARMTargetInfo::GCCRegNames[] = {
4128  // Integer registers
4129  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4130  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4131
4132  // Float registers
4133  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4134  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4135  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4136  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4137
4138  // Double registers
4139  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4140  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4141  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4142  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4143
4144  // Quad registers
4145  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4146  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4147};
4148
4149void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4150                                   unsigned &NumNames) const {
4151  Names = GCCRegNames;
4152  NumNames = llvm::array_lengthof(GCCRegNames);
4153}
4154
4155const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4156  { { "a1" }, "r0" },
4157  { { "a2" }, "r1" },
4158  { { "a3" }, "r2" },
4159  { { "a4" }, "r3" },
4160  { { "v1" }, "r4" },
4161  { { "v2" }, "r5" },
4162  { { "v3" }, "r6" },
4163  { { "v4" }, "r7" },
4164  { { "v5" }, "r8" },
4165  { { "v6", "rfp" }, "r9" },
4166  { { "sl" }, "r10" },
4167  { { "fp" }, "r11" },
4168  { { "ip" }, "r12" },
4169  { { "r13" }, "sp" },
4170  { { "r14" }, "lr" },
4171  { { "r15" }, "pc" },
4172  // The S, D and Q registers overlap, but aren't really aliases; we
4173  // don't want to substitute one of these for a different-sized one.
4174};
4175
4176void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4177                                       unsigned &NumAliases) const {
4178  Aliases = GCCRegAliases;
4179  NumAliases = llvm::array_lengthof(GCCRegAliases);
4180}
4181
4182const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4183#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4184#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4185                                              ALL_LANGUAGES },
4186#include "clang/Basic/BuiltinsARM.def"
4187};
4188} // end anonymous namespace.
4189
4190namespace {
4191class DarwinARMTargetInfo :
4192  public DarwinTargetInfo<ARMTargetInfo> {
4193protected:
4194  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4195                            MacroBuilder &Builder) const {
4196    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4197  }
4198
4199public:
4200  DarwinARMTargetInfo(const llvm::Triple &Triple)
4201      : DarwinTargetInfo<ARMTargetInfo>(Triple) {
4202    HasAlignMac68kSupport = true;
4203    // iOS always has 64-bit atomic instructions.
4204    // FIXME: This should be based off of the target features in ARMTargetInfo.
4205    MaxAtomicInlineWidth = 64;
4206
4207    // Darwin on iOS uses a variant of the ARM C++ ABI.
4208    TheCXXABI.set(TargetCXXABI::iOS);
4209  }
4210};
4211} // end anonymous namespace.
4212
4213
4214namespace {
4215// Hexagon abstract base class
4216class HexagonTargetInfo : public TargetInfo {
4217  static const Builtin::Info BuiltinInfo[];
4218  static const char * const GCCRegNames[];
4219  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4220  std::string CPU;
4221public:
4222  HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4223    BigEndian = false;
4224    DescriptionString = ("e-p:32:32:32-"
4225                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4226                         "f64:64:64-f32:32:32-a0:0-n32");
4227
4228    // {} in inline assembly are packet specifiers, not assembly variant
4229    // specifiers.
4230    NoAsmVariants = true;
4231  }
4232
4233  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4234                                 unsigned &NumRecords) const {
4235    Records = BuiltinInfo;
4236    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4237  }
4238
4239  virtual bool validateAsmConstraint(const char *&Name,
4240                                     TargetInfo::ConstraintInfo &Info) const {
4241    return true;
4242  }
4243
4244  virtual void getTargetDefines(const LangOptions &Opts,
4245                                MacroBuilder &Builder) const;
4246
4247  virtual bool hasFeature(StringRef Feature) const {
4248    return Feature == "hexagon";
4249  }
4250
4251  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4252    return TargetInfo::CharPtrBuiltinVaList;
4253  }
4254  virtual void getGCCRegNames(const char * const *&Names,
4255                              unsigned &NumNames) const;
4256  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4257                                unsigned &NumAliases) const;
4258  virtual const char *getClobbers() const {
4259    return "";
4260  }
4261
4262  static const char *getHexagonCPUSuffix(StringRef Name) {
4263    return llvm::StringSwitch<const char*>(Name)
4264      .Case("hexagonv4", "4")
4265      .Case("hexagonv5", "5")
4266      .Default(0);
4267  }
4268
4269  virtual bool setCPU(const std::string &Name) {
4270    if (!getHexagonCPUSuffix(Name))
4271      return false;
4272
4273    CPU = Name;
4274    return true;
4275  }
4276};
4277
4278void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4279                                MacroBuilder &Builder) const {
4280  Builder.defineMacro("qdsp6");
4281  Builder.defineMacro("__qdsp6", "1");
4282  Builder.defineMacro("__qdsp6__", "1");
4283
4284  Builder.defineMacro("hexagon");
4285  Builder.defineMacro("__hexagon", "1");
4286  Builder.defineMacro("__hexagon__", "1");
4287
4288  if(CPU == "hexagonv1") {
4289    Builder.defineMacro("__HEXAGON_V1__");
4290    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4291    if(Opts.HexagonQdsp6Compat) {
4292      Builder.defineMacro("__QDSP6_V1__");
4293      Builder.defineMacro("__QDSP6_ARCH__", "1");
4294    }
4295  }
4296  else if(CPU == "hexagonv2") {
4297    Builder.defineMacro("__HEXAGON_V2__");
4298    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4299    if(Opts.HexagonQdsp6Compat) {
4300      Builder.defineMacro("__QDSP6_V2__");
4301      Builder.defineMacro("__QDSP6_ARCH__", "2");
4302    }
4303  }
4304  else if(CPU == "hexagonv3") {
4305    Builder.defineMacro("__HEXAGON_V3__");
4306    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4307    if(Opts.HexagonQdsp6Compat) {
4308      Builder.defineMacro("__QDSP6_V3__");
4309      Builder.defineMacro("__QDSP6_ARCH__", "3");
4310    }
4311  }
4312  else if(CPU == "hexagonv4") {
4313    Builder.defineMacro("__HEXAGON_V4__");
4314    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4315    if(Opts.HexagonQdsp6Compat) {
4316      Builder.defineMacro("__QDSP6_V4__");
4317      Builder.defineMacro("__QDSP6_ARCH__", "4");
4318    }
4319  }
4320  else if(CPU == "hexagonv5") {
4321    Builder.defineMacro("__HEXAGON_V5__");
4322    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4323    if(Opts.HexagonQdsp6Compat) {
4324      Builder.defineMacro("__QDSP6_V5__");
4325      Builder.defineMacro("__QDSP6_ARCH__", "5");
4326    }
4327  }
4328}
4329
4330const char * const HexagonTargetInfo::GCCRegNames[] = {
4331  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4332  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4333  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4334  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4335  "p0", "p1", "p2", "p3",
4336  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4337};
4338
4339void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4340                                   unsigned &NumNames) const {
4341  Names = GCCRegNames;
4342  NumNames = llvm::array_lengthof(GCCRegNames);
4343}
4344
4345
4346const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4347  { { "sp" }, "r29" },
4348  { { "fp" }, "r30" },
4349  { { "lr" }, "r31" },
4350 };
4351
4352void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4353                                     unsigned &NumAliases) const {
4354  Aliases = GCCRegAliases;
4355  NumAliases = llvm::array_lengthof(GCCRegAliases);
4356}
4357
4358
4359const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4360#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4361#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4362                                              ALL_LANGUAGES },
4363#include "clang/Basic/BuiltinsHexagon.def"
4364};
4365}
4366
4367
4368namespace {
4369// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4370class SparcTargetInfo : public TargetInfo {
4371  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4372  static const char * const GCCRegNames[];
4373  bool SoftFloat;
4374public:
4375  SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4376
4377  virtual bool handleTargetFeatures(std::vector<std::string> &Features,
4378                                    DiagnosticsEngine &Diags) {
4379    SoftFloat = false;
4380    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4381      if (Features[i] == "+soft-float")
4382        SoftFloat = true;
4383    return true;
4384  }
4385  virtual void getTargetDefines(const LangOptions &Opts,
4386                                MacroBuilder &Builder) const {
4387    DefineStd(Builder, "sparc", Opts);
4388    Builder.defineMacro("__REGISTER_PREFIX__", "");
4389
4390    if (SoftFloat)
4391      Builder.defineMacro("SOFT_FLOAT", "1");
4392  }
4393
4394  virtual bool hasFeature(StringRef Feature) const {
4395    return llvm::StringSwitch<bool>(Feature)
4396             .Case("softfloat", SoftFloat)
4397             .Case("sparc", true)
4398             .Default(false);
4399  }
4400
4401  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4402                                 unsigned &NumRecords) const {
4403    // FIXME: Implement!
4404  }
4405  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4406    return TargetInfo::VoidPtrBuiltinVaList;
4407  }
4408  virtual void getGCCRegNames(const char * const *&Names,
4409                              unsigned &NumNames) const;
4410  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4411                                unsigned &NumAliases) const;
4412  virtual bool validateAsmConstraint(const char *&Name,
4413                                     TargetInfo::ConstraintInfo &info) const {
4414    // FIXME: Implement!
4415    return false;
4416  }
4417  virtual const char *getClobbers() const {
4418    // FIXME: Implement!
4419    return "";
4420  }
4421};
4422
4423const char * const SparcTargetInfo::GCCRegNames[] = {
4424  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4425  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4426  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4427  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4428};
4429
4430void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4431                                     unsigned &NumNames) const {
4432  Names = GCCRegNames;
4433  NumNames = llvm::array_lengthof(GCCRegNames);
4434}
4435
4436const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4437  { { "g0" }, "r0" },
4438  { { "g1" }, "r1" },
4439  { { "g2" }, "r2" },
4440  { { "g3" }, "r3" },
4441  { { "g4" }, "r4" },
4442  { { "g5" }, "r5" },
4443  { { "g6" }, "r6" },
4444  { { "g7" }, "r7" },
4445  { { "o0" }, "r8" },
4446  { { "o1" }, "r9" },
4447  { { "o2" }, "r10" },
4448  { { "o3" }, "r11" },
4449  { { "o4" }, "r12" },
4450  { { "o5" }, "r13" },
4451  { { "o6", "sp" }, "r14" },
4452  { { "o7" }, "r15" },
4453  { { "l0" }, "r16" },
4454  { { "l1" }, "r17" },
4455  { { "l2" }, "r18" },
4456  { { "l3" }, "r19" },
4457  { { "l4" }, "r20" },
4458  { { "l5" }, "r21" },
4459  { { "l6" }, "r22" },
4460  { { "l7" }, "r23" },
4461  { { "i0" }, "r24" },
4462  { { "i1" }, "r25" },
4463  { { "i2" }, "r26" },
4464  { { "i3" }, "r27" },
4465  { { "i4" }, "r28" },
4466  { { "i5" }, "r29" },
4467  { { "i6", "fp" }, "r30" },
4468  { { "i7" }, "r31" },
4469};
4470
4471void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4472                                       unsigned &NumAliases) const {
4473  Aliases = GCCRegAliases;
4474  NumAliases = llvm::array_lengthof(GCCRegAliases);
4475}
4476
4477// SPARC v8 is the 32-bit mode selected by Triple::sparc.
4478class SparcV8TargetInfo : public SparcTargetInfo {
4479public:
4480  SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4481    // FIXME: Support Sparc quad-precision long double?
4482    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4483                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4484  }
4485
4486  virtual void getTargetDefines(const LangOptions &Opts,
4487                                MacroBuilder &Builder) const {
4488    SparcTargetInfo::getTargetDefines(Opts, Builder);
4489    Builder.defineMacro("__sparcv8");
4490  }
4491};
4492
4493// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4494class SparcV9TargetInfo : public SparcTargetInfo {
4495public:
4496  SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4497    // FIXME: Support Sparc quad-precision long double?
4498    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4499                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4500    // This is an LP64 platform.
4501    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4502
4503    // OpenBSD uses long long for int64_t and intmax_t.
4504    if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4505      IntMaxType = SignedLongLong;
4506      UIntMaxType = UnsignedLongLong;
4507    } else {
4508      IntMaxType = SignedLong;
4509      UIntMaxType = UnsignedLong;
4510    }
4511    Int64Type = IntMaxType;
4512  }
4513
4514  virtual void getTargetDefines(const LangOptions &Opts,
4515                                MacroBuilder &Builder) const {
4516    SparcTargetInfo::getTargetDefines(Opts, Builder);
4517    Builder.defineMacro("__sparcv9");
4518    Builder.defineMacro("__arch64__");
4519    // Solaris and its derivative AuroraUX don't need these variants, but the
4520    // BSDs do.
4521    if (getTriple().getOS() != llvm::Triple::Solaris &&
4522        getTriple().getOS() != llvm::Triple::AuroraUX) {
4523      Builder.defineMacro("__sparc64__");
4524      Builder.defineMacro("__sparc_v9__");
4525      Builder.defineMacro("__sparcv9__");
4526    }
4527  }
4528};
4529
4530} // end anonymous namespace.
4531
4532namespace {
4533class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4534public:
4535  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4536      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4537    SizeType = UnsignedInt;
4538    PtrDiffType = SignedInt;
4539  }
4540};
4541class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4542public:
4543  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4544      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4545    SizeType = UnsignedInt;
4546    PtrDiffType = SignedInt;
4547  }
4548};
4549} // end anonymous namespace.
4550
4551namespace {
4552  class SystemZTargetInfo : public TargetInfo {
4553    static const char *const GCCRegNames[];
4554
4555  public:
4556    SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4557      TLSSupported = true;
4558      IntWidth = IntAlign = 32;
4559      LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4560      PointerWidth = PointerAlign = 64;
4561      LongDoubleWidth = 128;
4562      LongDoubleAlign = 64;
4563      LongDoubleFormat = &llvm::APFloat::IEEEquad;
4564      MinGlobalAlign = 16;
4565      DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4566       "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4567      MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4568    }
4569    virtual void getTargetDefines(const LangOptions &Opts,
4570                                  MacroBuilder &Builder) const {
4571      Builder.defineMacro("__s390__");
4572      Builder.defineMacro("__s390x__");
4573      Builder.defineMacro("__zarch__");
4574      Builder.defineMacro("__LONG_DOUBLE_128__");
4575    }
4576    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4577                                   unsigned &NumRecords) const {
4578      // FIXME: Implement.
4579      Records = 0;
4580      NumRecords = 0;
4581    }
4582
4583    virtual void getGCCRegNames(const char *const *&Names,
4584                                unsigned &NumNames) const;
4585    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4586                                  unsigned &NumAliases) const {
4587      // No aliases.
4588      Aliases = 0;
4589      NumAliases = 0;
4590    }
4591    virtual bool validateAsmConstraint(const char *&Name,
4592                                       TargetInfo::ConstraintInfo &info) const;
4593    virtual const char *getClobbers() const {
4594      // FIXME: Is this really right?
4595      return "";
4596    }
4597    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4598      return TargetInfo::SystemZBuiltinVaList;
4599    }
4600    virtual bool setCPU(const std::string &Name) {
4601      bool CPUKnown = llvm::StringSwitch<bool>(Name)
4602        .Case("z10", true)
4603        .Case("z196", true)
4604        .Case("zEC12", true)
4605        .Default(false);
4606
4607      // No need to store the CPU yet.  There aren't any CPU-specific
4608      // macros to define.
4609      return CPUKnown;
4610    }
4611  };
4612
4613  const char *const SystemZTargetInfo::GCCRegNames[] = {
4614    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4615    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4616    "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4617    "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4618  };
4619
4620  void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4621                                         unsigned &NumNames) const {
4622    Names = GCCRegNames;
4623    NumNames = llvm::array_lengthof(GCCRegNames);
4624  }
4625
4626  bool SystemZTargetInfo::
4627  validateAsmConstraint(const char *&Name,
4628                        TargetInfo::ConstraintInfo &Info) const {
4629    switch (*Name) {
4630    default:
4631      return false;
4632
4633    case 'a': // Address register
4634    case 'd': // Data register (equivalent to 'r')
4635    case 'f': // Floating-point register
4636      Info.setAllowsRegister();
4637      return true;
4638
4639    case 'I': // Unsigned 8-bit constant
4640    case 'J': // Unsigned 12-bit constant
4641    case 'K': // Signed 16-bit constant
4642    case 'L': // Signed 20-bit displacement (on all targets we support)
4643    case 'M': // 0x7fffffff
4644      return true;
4645
4646    case 'Q': // Memory with base and unsigned 12-bit displacement
4647    case 'R': // Likewise, plus an index
4648    case 'S': // Memory with base and signed 20-bit displacement
4649    case 'T': // Likewise, plus an index
4650      Info.setAllowsMemory();
4651      return true;
4652    }
4653  }
4654}
4655
4656namespace {
4657  class MSP430TargetInfo : public TargetInfo {
4658    static const char * const GCCRegNames[];
4659  public:
4660    MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4661      BigEndian = false;
4662      TLSSupported = false;
4663      IntWidth = 16; IntAlign = 16;
4664      LongWidth = 32; LongLongWidth = 64;
4665      LongAlign = LongLongAlign = 16;
4666      PointerWidth = 16; PointerAlign = 16;
4667      SuitableAlign = 16;
4668      SizeType = UnsignedInt;
4669      IntMaxType = SignedLongLong;
4670      UIntMaxType = UnsignedLongLong;
4671      IntPtrType = SignedInt;
4672      PtrDiffType = SignedInt;
4673      SigAtomicType = SignedLong;
4674      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4675   }
4676    virtual void getTargetDefines(const LangOptions &Opts,
4677                                  MacroBuilder &Builder) const {
4678      Builder.defineMacro("MSP430");
4679      Builder.defineMacro("__MSP430__");
4680      // FIXME: defines for different 'flavours' of MCU
4681    }
4682    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4683                                   unsigned &NumRecords) const {
4684     // FIXME: Implement.
4685      Records = 0;
4686      NumRecords = 0;
4687    }
4688    virtual bool hasFeature(StringRef Feature) const {
4689      return Feature == "msp430";
4690    }
4691    virtual void getGCCRegNames(const char * const *&Names,
4692                                unsigned &NumNames) const;
4693    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4694                                  unsigned &NumAliases) const {
4695      // No aliases.
4696      Aliases = 0;
4697      NumAliases = 0;
4698    }
4699    virtual bool validateAsmConstraint(const char *&Name,
4700                                       TargetInfo::ConstraintInfo &info) const {
4701      // No target constraints for now.
4702      return false;
4703    }
4704    virtual const char *getClobbers() const {
4705      // FIXME: Is this really right?
4706      return "";
4707    }
4708    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4709      // FIXME: implement
4710      return TargetInfo::CharPtrBuiltinVaList;
4711   }
4712  };
4713
4714  const char * const MSP430TargetInfo::GCCRegNames[] = {
4715    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4716    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4717  };
4718
4719  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4720                                        unsigned &NumNames) const {
4721    Names = GCCRegNames;
4722    NumNames = llvm::array_lengthof(GCCRegNames);
4723  }
4724}
4725
4726namespace {
4727
4728  // LLVM and Clang cannot be used directly to output native binaries for
4729  // target, but is used to compile C code to llvm bitcode with correct
4730  // type and alignment information.
4731  //
4732  // TCE uses the llvm bitcode as input and uses it for generating customized
4733  // target processor and program binary. TCE co-design environment is
4734  // publicly available in http://tce.cs.tut.fi
4735
4736  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4737      3, // opencl_global
4738      4, // opencl_local
4739      5, // opencl_constant
4740      0, // cuda_device
4741      0, // cuda_constant
4742      0  // cuda_shared
4743  };
4744
4745  class TCETargetInfo : public TargetInfo{
4746  public:
4747    TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4748      TLSSupported = false;
4749      IntWidth = 32;
4750      LongWidth = LongLongWidth = 32;
4751      PointerWidth = 32;
4752      IntAlign = 32;
4753      LongAlign = LongLongAlign = 32;
4754      PointerAlign = 32;
4755      SuitableAlign = 32;
4756      SizeType = UnsignedInt;
4757      IntMaxType = SignedLong;
4758      UIntMaxType = UnsignedLong;
4759      IntPtrType = SignedInt;
4760      PtrDiffType = SignedInt;
4761      FloatWidth = 32;
4762      FloatAlign = 32;
4763      DoubleWidth = 32;
4764      DoubleAlign = 32;
4765      LongDoubleWidth = 32;
4766      LongDoubleAlign = 32;
4767      FloatFormat = &llvm::APFloat::IEEEsingle;
4768      DoubleFormat = &llvm::APFloat::IEEEsingle;
4769      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4770      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4771                          "i16:16:32-i32:32:32-i64:32:32-"
4772                          "f32:32:32-f64:32:32-v64:32:32-"
4773                          "v128:32:32-a0:0:32-n32";
4774      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4775      UseAddrSpaceMapMangling = true;
4776    }
4777
4778    virtual void getTargetDefines(const LangOptions &Opts,
4779                                  MacroBuilder &Builder) const {
4780      DefineStd(Builder, "tce", Opts);
4781      Builder.defineMacro("__TCE__");
4782      Builder.defineMacro("__TCE_V1__");
4783    }
4784    virtual bool hasFeature(StringRef Feature) const {
4785      return Feature == "tce";
4786    }
4787
4788    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4789                                   unsigned &NumRecords) const {}
4790    virtual const char *getClobbers() const {
4791      return "";
4792    }
4793    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4794      return TargetInfo::VoidPtrBuiltinVaList;
4795    }
4796    virtual void getGCCRegNames(const char * const *&Names,
4797                                unsigned &NumNames) const {}
4798    virtual bool validateAsmConstraint(const char *&Name,
4799                                       TargetInfo::ConstraintInfo &info) const {
4800      return true;
4801    }
4802    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4803                                  unsigned &NumAliases) const {}
4804  };
4805}
4806
4807namespace {
4808class MipsTargetInfoBase : public TargetInfo {
4809  virtual void setDescriptionString() = 0;
4810
4811  static const Builtin::Info BuiltinInfo[];
4812  std::string CPU;
4813  bool IsMips16;
4814  bool IsMicromips;
4815  bool IsNan2008;
4816  bool IsSingleFloat;
4817  enum MipsFloatABI {
4818    HardFloat, SoftFloat
4819  } FloatABI;
4820  enum DspRevEnum {
4821    NoDSP, DSP1, DSP2
4822  } DspRev;
4823  bool HasMSA;
4824
4825protected:
4826  bool HasFP64;
4827  std::string ABI;
4828
4829public:
4830  MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4831                     const std::string &CPUStr)
4832      : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4833        IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
4834        DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
4835
4836  virtual const char *getABI() const { return ABI.c_str(); }
4837  virtual bool setABI(const std::string &Name) = 0;
4838  virtual bool setCPU(const std::string &Name) {
4839    CPU = Name;
4840    return true;
4841  }
4842  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4843    Features[ABI] = true;
4844    Features[CPU] = true;
4845  }
4846
4847  virtual void getTargetDefines(const LangOptions &Opts,
4848                                MacroBuilder &Builder) const {
4849    DefineStd(Builder, "mips", Opts);
4850    Builder.defineMacro("_mips");
4851    Builder.defineMacro("__REGISTER_PREFIX__", "");
4852
4853    switch (FloatABI) {
4854    case HardFloat:
4855      Builder.defineMacro("__mips_hard_float", Twine(1));
4856      break;
4857    case SoftFloat:
4858      Builder.defineMacro("__mips_soft_float", Twine(1));
4859      break;
4860    }
4861
4862    if (IsSingleFloat)
4863      Builder.defineMacro("__mips_single_float", Twine(1));
4864
4865    Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
4866    Builder.defineMacro("_MIPS_FPSET",
4867                        Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
4868
4869    if (IsMips16)
4870      Builder.defineMacro("__mips16", Twine(1));
4871
4872    if (IsMicromips)
4873      Builder.defineMacro("__mips_micromips", Twine(1));
4874
4875    if (IsNan2008)
4876      Builder.defineMacro("__mips_nan2008", Twine(1));
4877
4878    switch (DspRev) {
4879    default:
4880      break;
4881    case DSP1:
4882      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4883      Builder.defineMacro("__mips_dsp", Twine(1));
4884      break;
4885    case DSP2:
4886      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4887      Builder.defineMacro("__mips_dspr2", Twine(1));
4888      Builder.defineMacro("__mips_dsp", Twine(1));
4889      break;
4890    }
4891
4892    if (HasMSA)
4893      Builder.defineMacro("__mips_msa", Twine(1));
4894
4895    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4896    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4897    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4898
4899    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4900    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4901  }
4902
4903  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4904                                 unsigned &NumRecords) const {
4905    Records = BuiltinInfo;
4906    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4907  }
4908  virtual bool hasFeature(StringRef Feature) const {
4909    return llvm::StringSwitch<bool>(Feature)
4910      .Case("mips", true)
4911      .Case("fp64", HasFP64)
4912      .Default(false);
4913  }
4914  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4915    return TargetInfo::VoidPtrBuiltinVaList;
4916  }
4917  virtual void getGCCRegNames(const char * const *&Names,
4918                              unsigned &NumNames) const {
4919    static const char * const GCCRegNames[] = {
4920      // CPU register names
4921      // Must match second column of GCCRegAliases
4922      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4923      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4924      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4925      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4926      // Floating point register names
4927      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4928      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4929      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4930      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4931      // Hi/lo and condition register names
4932      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4933      "$fcc5","$fcc6","$fcc7"
4934    };
4935    Names = GCCRegNames;
4936    NumNames = llvm::array_lengthof(GCCRegNames);
4937  }
4938  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4939                                unsigned &NumAliases) const = 0;
4940  virtual bool validateAsmConstraint(const char *&Name,
4941                                     TargetInfo::ConstraintInfo &Info) const {
4942    switch (*Name) {
4943    default:
4944      return false;
4945
4946    case 'r': // CPU registers.
4947    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4948    case 'y': // Equivalent to "r", backwards compatibility only.
4949    case 'f': // floating-point registers.
4950    case 'c': // $25 for indirect jumps
4951    case 'l': // lo register
4952    case 'x': // hilo register pair
4953      Info.setAllowsRegister();
4954      return true;
4955    case 'R': // An address that can be used in a non-macro load or store
4956      Info.setAllowsMemory();
4957      return true;
4958    }
4959  }
4960
4961  virtual const char *getClobbers() const {
4962    // FIXME: Implement!
4963    return "";
4964  }
4965
4966  virtual bool handleTargetFeatures(std::vector<std::string> &Features,
4967                                    DiagnosticsEngine &Diags) {
4968    IsMips16 = false;
4969    IsMicromips = false;
4970    IsNan2008 = false;
4971    IsSingleFloat = false;
4972    FloatABI = HardFloat;
4973    DspRev = NoDSP;
4974    HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64";
4975
4976    for (std::vector<std::string>::iterator it = Features.begin(),
4977         ie = Features.end(); it != ie; ++it) {
4978      if (*it == "+single-float")
4979        IsSingleFloat = true;
4980      else if (*it == "+soft-float")
4981        FloatABI = SoftFloat;
4982      else if (*it == "+mips16")
4983        IsMips16 = true;
4984      else if (*it == "+micromips")
4985        IsMicromips = true;
4986      else if (*it == "+dsp")
4987        DspRev = std::max(DspRev, DSP1);
4988      else if (*it == "+dspr2")
4989        DspRev = std::max(DspRev, DSP2);
4990      else if (*it == "+msa")
4991        HasMSA = true;
4992      else if (*it == "+fp64")
4993        HasFP64 = true;
4994      else if (*it == "-fp64")
4995        HasFP64 = false;
4996      else if (*it == "+nan2008")
4997        IsNan2008 = true;
4998    }
4999
5000    // Remove front-end specific options.
5001    std::vector<std::string>::iterator it =
5002      std::find(Features.begin(), Features.end(), "+soft-float");
5003    if (it != Features.end())
5004      Features.erase(it);
5005    it = std::find(Features.begin(), Features.end(), "+nan2008");
5006    if (it != Features.end())
5007      Features.erase(it);
5008
5009    setDescriptionString();
5010
5011    return true;
5012  }
5013
5014  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
5015    if (RegNo == 0) return 4;
5016    if (RegNo == 1) return 5;
5017    return -1;
5018  }
5019};
5020
5021const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5022#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5023#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5024                                              ALL_LANGUAGES },
5025#include "clang/Basic/BuiltinsMips.def"
5026};
5027
5028class Mips32TargetInfoBase : public MipsTargetInfoBase {
5029public:
5030  Mips32TargetInfoBase(const llvm::Triple &Triple)
5031      : MipsTargetInfoBase(Triple, "o32", "mips32") {
5032    SizeType = UnsignedInt;
5033    PtrDiffType = SignedInt;
5034    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5035  }
5036  virtual bool setABI(const std::string &Name) {
5037    if ((Name == "o32") || (Name == "eabi")) {
5038      ABI = Name;
5039      return true;
5040    } else if (Name == "32") {
5041      ABI = "o32";
5042      return true;
5043    } else
5044      return false;
5045  }
5046  virtual void getTargetDefines(const LangOptions &Opts,
5047                                MacroBuilder &Builder) const {
5048    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5049
5050    if (ABI == "o32") {
5051      Builder.defineMacro("__mips_o32");
5052      Builder.defineMacro("_ABIO32", "1");
5053      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5054    }
5055    else if (ABI == "eabi")
5056      Builder.defineMacro("__mips_eabi");
5057    else
5058      llvm_unreachable("Invalid ABI for Mips32.");
5059  }
5060  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5061                                unsigned &NumAliases) const {
5062    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5063      { { "at" },  "$1" },
5064      { { "v0" },  "$2" },
5065      { { "v1" },  "$3" },
5066      { { "a0" },  "$4" },
5067      { { "a1" },  "$5" },
5068      { { "a2" },  "$6" },
5069      { { "a3" },  "$7" },
5070      { { "t0" },  "$8" },
5071      { { "t1" },  "$9" },
5072      { { "t2" }, "$10" },
5073      { { "t3" }, "$11" },
5074      { { "t4" }, "$12" },
5075      { { "t5" }, "$13" },
5076      { { "t6" }, "$14" },
5077      { { "t7" }, "$15" },
5078      { { "s0" }, "$16" },
5079      { { "s1" }, "$17" },
5080      { { "s2" }, "$18" },
5081      { { "s3" }, "$19" },
5082      { { "s4" }, "$20" },
5083      { { "s5" }, "$21" },
5084      { { "s6" }, "$22" },
5085      { { "s7" }, "$23" },
5086      { { "t8" }, "$24" },
5087      { { "t9" }, "$25" },
5088      { { "k0" }, "$26" },
5089      { { "k1" }, "$27" },
5090      { { "gp" }, "$28" },
5091      { { "sp","$sp" }, "$29" },
5092      { { "fp","$fp" }, "$30" },
5093      { { "ra" }, "$31" }
5094    };
5095    Aliases = GCCRegAliases;
5096    NumAliases = llvm::array_lengthof(GCCRegAliases);
5097  }
5098};
5099
5100class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5101  virtual void setDescriptionString() {
5102    if (HasFP64)
5103      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5104                          "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S128";
5105    else
5106      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5107                          "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
5108  }
5109
5110public:
5111  Mips32EBTargetInfo(const llvm::Triple &Triple)
5112      : Mips32TargetInfoBase(Triple) {
5113  }
5114  virtual void getTargetDefines(const LangOptions &Opts,
5115                                MacroBuilder &Builder) const {
5116    DefineStd(Builder, "MIPSEB", Opts);
5117    Builder.defineMacro("_MIPSEB");
5118    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5119  }
5120};
5121
5122class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5123  virtual void setDescriptionString() {
5124    if (HasFP64)
5125      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5126                          "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S128";
5127    else
5128      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5129                          "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
5130  }
5131
5132public:
5133  Mips32ELTargetInfo(const llvm::Triple &Triple)
5134      : Mips32TargetInfoBase(Triple) {
5135    BigEndian = false;
5136  }
5137  virtual void getTargetDefines(const LangOptions &Opts,
5138                                MacroBuilder &Builder) const {
5139    DefineStd(Builder, "MIPSEL", Opts);
5140    Builder.defineMacro("_MIPSEL");
5141    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5142  }
5143};
5144
5145class Mips64TargetInfoBase : public MipsTargetInfoBase {
5146public:
5147  Mips64TargetInfoBase(const llvm::Triple &Triple)
5148      : MipsTargetInfoBase(Triple, "n64", "mips64") {
5149    LongWidth = LongAlign = 64;
5150    PointerWidth = PointerAlign = 64;
5151    LongDoubleWidth = LongDoubleAlign = 128;
5152    LongDoubleFormat = &llvm::APFloat::IEEEquad;
5153    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5154      LongDoubleWidth = LongDoubleAlign = 64;
5155      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5156    }
5157    SuitableAlign = 128;
5158    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5159  }
5160  virtual bool setABI(const std::string &Name) {
5161    if (Name == "n32") {
5162      LongWidth = LongAlign = 32;
5163      PointerWidth = PointerAlign = 32;
5164      ABI = Name;
5165      return true;
5166    } else if (Name == "n64") {
5167      ABI = Name;
5168      return true;
5169    } else if (Name == "64") {
5170      ABI = "n64";
5171      return true;
5172    } else
5173      return false;
5174  }
5175  virtual void getTargetDefines(const LangOptions &Opts,
5176                                MacroBuilder &Builder) const {
5177    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5178
5179    Builder.defineMacro("__mips64");
5180    Builder.defineMacro("__mips64__");
5181
5182    if (ABI == "n32") {
5183      Builder.defineMacro("__mips_n32");
5184      Builder.defineMacro("_ABIN32", "2");
5185      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5186    }
5187    else if (ABI == "n64") {
5188      Builder.defineMacro("__mips_n64");
5189      Builder.defineMacro("_ABI64", "3");
5190      Builder.defineMacro("_MIPS_SIM", "_ABI64");
5191    }
5192    else
5193      llvm_unreachable("Invalid ABI for Mips64.");
5194  }
5195  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5196                                unsigned &NumAliases) const {
5197    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5198      { { "at" },  "$1" },
5199      { { "v0" },  "$2" },
5200      { { "v1" },  "$3" },
5201      { { "a0" },  "$4" },
5202      { { "a1" },  "$5" },
5203      { { "a2" },  "$6" },
5204      { { "a3" },  "$7" },
5205      { { "a4" },  "$8" },
5206      { { "a5" },  "$9" },
5207      { { "a6" }, "$10" },
5208      { { "a7" }, "$11" },
5209      { { "t0" }, "$12" },
5210      { { "t1" }, "$13" },
5211      { { "t2" }, "$14" },
5212      { { "t3" }, "$15" },
5213      { { "s0" }, "$16" },
5214      { { "s1" }, "$17" },
5215      { { "s2" }, "$18" },
5216      { { "s3" }, "$19" },
5217      { { "s4" }, "$20" },
5218      { { "s5" }, "$21" },
5219      { { "s6" }, "$22" },
5220      { { "s7" }, "$23" },
5221      { { "t8" }, "$24" },
5222      { { "t9" }, "$25" },
5223      { { "k0" }, "$26" },
5224      { { "k1" }, "$27" },
5225      { { "gp" }, "$28" },
5226      { { "sp","$sp" }, "$29" },
5227      { { "fp","$fp" }, "$30" },
5228      { { "ra" }, "$31" }
5229    };
5230    Aliases = GCCRegAliases;
5231    NumAliases = llvm::array_lengthof(GCCRegAliases);
5232  }
5233};
5234
5235class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5236  virtual void setDescriptionString() {
5237    if (ABI == "n32")
5238      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5239                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5240                          "v64:64:64-n32:64-S128";
5241    else
5242      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5243                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5244                          "v64:64:64-n32:64-S128";
5245
5246  }
5247
5248public:
5249  Mips64EBTargetInfo(const llvm::Triple &Triple)
5250      : Mips64TargetInfoBase(Triple) {}
5251  virtual void getTargetDefines(const LangOptions &Opts,
5252                                MacroBuilder &Builder) const {
5253    DefineStd(Builder, "MIPSEB", Opts);
5254    Builder.defineMacro("_MIPSEB");
5255    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5256  }
5257};
5258
5259class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5260  virtual void setDescriptionString() {
5261    if (ABI == "n32")
5262      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5263                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5264                          "-v64:64:64-n32:64-S128";
5265    else
5266      DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5267                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5268                          "v64:64:64-n32:64-S128";
5269  }
5270public:
5271  Mips64ELTargetInfo(const llvm::Triple &Triple)
5272      : Mips64TargetInfoBase(Triple) {
5273    // Default ABI is n64.
5274    BigEndian = false;
5275  }
5276  virtual void getTargetDefines(const LangOptions &Opts,
5277                                MacroBuilder &Builder) const {
5278    DefineStd(Builder, "MIPSEL", Opts);
5279    Builder.defineMacro("_MIPSEL");
5280    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5281  }
5282};
5283} // end anonymous namespace.
5284
5285namespace {
5286class PNaClTargetInfo : public TargetInfo {
5287public:
5288  PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5289    BigEndian = false;
5290    this->UserLabelPrefix = "";
5291    this->LongAlign = 32;
5292    this->LongWidth = 32;
5293    this->PointerAlign = 32;
5294    this->PointerWidth = 32;
5295    this->IntMaxType = TargetInfo::SignedLongLong;
5296    this->UIntMaxType = TargetInfo::UnsignedLongLong;
5297    this->Int64Type = TargetInfo::SignedLongLong;
5298    this->DoubleAlign = 64;
5299    this->LongDoubleWidth = 64;
5300    this->LongDoubleAlign = 64;
5301    this->SizeType = TargetInfo::UnsignedInt;
5302    this->PtrDiffType = TargetInfo::SignedInt;
5303    this->IntPtrType = TargetInfo::SignedInt;
5304    this->RegParmMax = 0; // Disallow regparm
5305    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5306                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5307  }
5308
5309  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5310  }
5311  virtual void getArchDefines(const LangOptions &Opts,
5312                              MacroBuilder &Builder) const {
5313    Builder.defineMacro("__le32__");
5314    Builder.defineMacro("__pnacl__");
5315  }
5316  virtual void getTargetDefines(const LangOptions &Opts,
5317                                MacroBuilder &Builder) const {
5318    Builder.defineMacro("__LITTLE_ENDIAN__");
5319    getArchDefines(Opts, Builder);
5320  }
5321  virtual bool hasFeature(StringRef Feature) const {
5322    return Feature == "pnacl";
5323  }
5324  virtual void getTargetBuiltins(const Builtin::Info *&Records,
5325                                 unsigned &NumRecords) const {
5326  }
5327  virtual BuiltinVaListKind getBuiltinVaListKind() const {
5328    return TargetInfo::PNaClABIBuiltinVaList;
5329  }
5330  virtual void getGCCRegNames(const char * const *&Names,
5331                              unsigned &NumNames) const;
5332  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5333                                unsigned &NumAliases) const;
5334  virtual bool validateAsmConstraint(const char *&Name,
5335                                     TargetInfo::ConstraintInfo &Info) const {
5336    return false;
5337  }
5338
5339  virtual const char *getClobbers() const {
5340    return "";
5341  }
5342};
5343
5344void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5345                                     unsigned &NumNames) const {
5346  Names = NULL;
5347  NumNames = 0;
5348}
5349
5350void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5351                                       unsigned &NumAliases) const {
5352  Aliases = NULL;
5353  NumAliases = 0;
5354}
5355} // end anonymous namespace.
5356
5357namespace {
5358  static const unsigned SPIRAddrSpaceMap[] = {
5359    1,    // opencl_global
5360    3,    // opencl_local
5361    2,    // opencl_constant
5362    0,    // cuda_device
5363    0,    // cuda_constant
5364    0     // cuda_shared
5365  };
5366  class SPIRTargetInfo : public TargetInfo {
5367  public:
5368    SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5369      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5370        "SPIR target must use unknown OS");
5371      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5372        "SPIR target must use unknown environment type");
5373      BigEndian = false;
5374      TLSSupported = false;
5375      LongWidth = LongAlign = 64;
5376      AddrSpaceMap = &SPIRAddrSpaceMap;
5377      UseAddrSpaceMapMangling = true;
5378      // Define available target features
5379      // These must be defined in sorted order!
5380      NoAsmVariants = true;
5381    }
5382    virtual void getTargetDefines(const LangOptions &Opts,
5383                                  MacroBuilder &Builder) const {
5384      DefineStd(Builder, "SPIR", Opts);
5385    }
5386    virtual bool hasFeature(StringRef Feature) const {
5387      return Feature == "spir";
5388    }
5389
5390    virtual void getTargetBuiltins(const Builtin::Info *&Records,
5391                                   unsigned &NumRecords) const {}
5392    virtual const char *getClobbers() const {
5393      return "";
5394    }
5395    virtual void getGCCRegNames(const char * const *&Names,
5396                                unsigned &NumNames) const {}
5397    virtual bool validateAsmConstraint(const char *&Name,
5398                                       TargetInfo::ConstraintInfo &info) const {
5399      return true;
5400    }
5401    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5402                                  unsigned &NumAliases) const {}
5403    virtual BuiltinVaListKind getBuiltinVaListKind() const {
5404      return TargetInfo::VoidPtrBuiltinVaList;
5405    }
5406  };
5407
5408
5409  class SPIR32TargetInfo : public SPIRTargetInfo {
5410  public:
5411    SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5412      PointerWidth = PointerAlign = 32;
5413      SizeType     = TargetInfo::UnsignedInt;
5414      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5415      DescriptionString
5416        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5417          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5418          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5419          "v512:512:512-v1024:1024:1024";
5420    }
5421    virtual void getTargetDefines(const LangOptions &Opts,
5422                                  MacroBuilder &Builder) const {
5423      DefineStd(Builder, "SPIR32", Opts);
5424    }
5425  };
5426
5427  class SPIR64TargetInfo : public SPIRTargetInfo {
5428  public:
5429    SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5430      PointerWidth = PointerAlign = 64;
5431      SizeType     = TargetInfo::UnsignedLong;
5432      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5433      DescriptionString
5434        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5435          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5436          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5437          "v512:512:512-v1024:1024:1024";
5438    }
5439    virtual void getTargetDefines(const LangOptions &Opts,
5440                                  MacroBuilder &Builder) const {
5441      DefineStd(Builder, "SPIR64", Opts);
5442    }
5443  };
5444}
5445
5446namespace {
5447class XCoreTargetInfo : public TargetInfo {
5448  static const Builtin::Info BuiltinInfo[];
5449public:
5450  XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5451    BigEndian = false;
5452    NoAsmVariants = true;
5453    LongLongAlign = 32;
5454    SuitableAlign = 32;
5455    DoubleAlign = LongDoubleAlign = 32;
5456    UseZeroLengthBitfieldAlignment = true;
5457    DescriptionString = "e-p:32:32:32-a0:0:32-n32"
5458                        "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32"
5459                        "-f16:16:32-f32:32:32-f64:32:32";
5460  }
5461  virtual void getTargetDefines(const LangOptions &Opts,
5462                                MacroBuilder &Builder) const {
5463    Builder.defineMacro("__XS1B__");
5464  }
5465  virtual void getTargetBuiltins(const Builtin::Info *&Records,
5466                                 unsigned &NumRecords) const {
5467    Records = BuiltinInfo;
5468    NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
5469  }
5470  virtual BuiltinVaListKind getBuiltinVaListKind() const {
5471    return TargetInfo::VoidPtrBuiltinVaList;
5472  }
5473  virtual const char *getClobbers() const {
5474    return "";
5475  }
5476  virtual void getGCCRegNames(const char * const *&Names,
5477                              unsigned &NumNames) const {
5478    static const char * const GCCRegNames[] = {
5479      "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
5480      "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
5481    };
5482    Names = GCCRegNames;
5483    NumNames = llvm::array_lengthof(GCCRegNames);
5484  }
5485  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5486                                unsigned &NumAliases) const {
5487    Aliases = NULL;
5488    NumAliases = 0;
5489  }
5490  virtual bool validateAsmConstraint(const char *&Name,
5491                                     TargetInfo::ConstraintInfo &Info) const {
5492    return false;
5493  }
5494};
5495
5496const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
5497#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5498#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5499                                              ALL_LANGUAGES },
5500#include "clang/Basic/BuiltinsXCore.def"
5501};
5502} // end anonymous namespace.
5503
5504
5505//===----------------------------------------------------------------------===//
5506// Driver code
5507//===----------------------------------------------------------------------===//
5508
5509static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5510  llvm::Triple::OSType os = Triple.getOS();
5511
5512  switch (Triple.getArch()) {
5513  default:
5514    return NULL;
5515
5516  case llvm::Triple::xcore:
5517    return new XCoreTargetInfo(Triple);
5518
5519  case llvm::Triple::hexagon:
5520    return new HexagonTargetInfo(Triple);
5521
5522  case llvm::Triple::aarch64:
5523    switch (os) {
5524    case llvm::Triple::Linux:
5525      return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5526    default:
5527      return new AArch64TargetInfo(Triple);
5528    }
5529
5530  case llvm::Triple::arm:
5531  case llvm::Triple::thumb:
5532    if (Triple.isOSDarwin())
5533      return new DarwinARMTargetInfo(Triple);
5534
5535    switch (os) {
5536    case llvm::Triple::Linux:
5537      return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5538    case llvm::Triple::FreeBSD:
5539      return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5540    case llvm::Triple::NetBSD:
5541      return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5542    case llvm::Triple::OpenBSD:
5543      return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5544    case llvm::Triple::Bitrig:
5545      return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5546    case llvm::Triple::RTEMS:
5547      return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5548    case llvm::Triple::NaCl:
5549      return new NaClTargetInfo<ARMTargetInfo>(Triple);
5550    default:
5551      return new ARMTargetInfo(Triple);
5552    }
5553
5554  case llvm::Triple::msp430:
5555    return new MSP430TargetInfo(Triple);
5556
5557  case llvm::Triple::mips:
5558    switch (os) {
5559    case llvm::Triple::Linux:
5560      return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5561    case llvm::Triple::RTEMS:
5562      return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5563    case llvm::Triple::FreeBSD:
5564      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5565    case llvm::Triple::NetBSD:
5566      return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5567    default:
5568      return new Mips32EBTargetInfo(Triple);
5569    }
5570
5571  case llvm::Triple::mipsel:
5572    switch (os) {
5573    case llvm::Triple::Linux:
5574      return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5575    case llvm::Triple::RTEMS:
5576      return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5577    case llvm::Triple::FreeBSD:
5578      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5579    case llvm::Triple::NetBSD:
5580      return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5581    case llvm::Triple::NaCl:
5582      return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
5583    default:
5584      return new Mips32ELTargetInfo(Triple);
5585    }
5586
5587  case llvm::Triple::mips64:
5588    switch (os) {
5589    case llvm::Triple::Linux:
5590      return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5591    case llvm::Triple::RTEMS:
5592      return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5593    case llvm::Triple::FreeBSD:
5594      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5595    case llvm::Triple::NetBSD:
5596      return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5597    case llvm::Triple::OpenBSD:
5598      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5599    default:
5600      return new Mips64EBTargetInfo(Triple);
5601    }
5602
5603  case llvm::Triple::mips64el:
5604    switch (os) {
5605    case llvm::Triple::Linux:
5606      return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5607    case llvm::Triple::RTEMS:
5608      return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5609    case llvm::Triple::FreeBSD:
5610      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5611    case llvm::Triple::NetBSD:
5612      return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5613    case llvm::Triple::OpenBSD:
5614      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5615    default:
5616      return new Mips64ELTargetInfo(Triple);
5617    }
5618
5619  case llvm::Triple::le32:
5620    switch (os) {
5621      case llvm::Triple::NaCl:
5622        return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5623      default:
5624        return NULL;
5625    }
5626
5627  case llvm::Triple::ppc:
5628    if (Triple.isOSDarwin())
5629      return new DarwinPPC32TargetInfo(Triple);
5630    switch (os) {
5631    case llvm::Triple::Linux:
5632      return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5633    case llvm::Triple::FreeBSD:
5634      return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5635    case llvm::Triple::NetBSD:
5636      return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5637    case llvm::Triple::OpenBSD:
5638      return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5639    case llvm::Triple::RTEMS:
5640      return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5641    default:
5642      return new PPC32TargetInfo(Triple);
5643    }
5644
5645  case llvm::Triple::ppc64:
5646    if (Triple.isOSDarwin())
5647      return new DarwinPPC64TargetInfo(Triple);
5648    switch (os) {
5649    case llvm::Triple::Linux:
5650      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5651    case llvm::Triple::Lv2:
5652      return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5653    case llvm::Triple::FreeBSD:
5654      return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5655    case llvm::Triple::NetBSD:
5656      return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5657    default:
5658      return new PPC64TargetInfo(Triple);
5659    }
5660
5661  case llvm::Triple::ppc64le:
5662    switch (os) {
5663    case llvm::Triple::Linux:
5664      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5665    default:
5666      return new PPC64TargetInfo(Triple);
5667    }
5668
5669  case llvm::Triple::nvptx:
5670    return new NVPTX32TargetInfo(Triple);
5671  case llvm::Triple::nvptx64:
5672    return new NVPTX64TargetInfo(Triple);
5673
5674  case llvm::Triple::r600:
5675    return new R600TargetInfo(Triple);
5676
5677  case llvm::Triple::sparc:
5678    switch (os) {
5679    case llvm::Triple::Linux:
5680      return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5681    case llvm::Triple::AuroraUX:
5682      return new AuroraUXSparcV8TargetInfo(Triple);
5683    case llvm::Triple::Solaris:
5684      return new SolarisSparcV8TargetInfo(Triple);
5685    case llvm::Triple::NetBSD:
5686      return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5687    case llvm::Triple::OpenBSD:
5688      return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5689    case llvm::Triple::RTEMS:
5690      return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5691    default:
5692      return new SparcV8TargetInfo(Triple);
5693    }
5694
5695  case llvm::Triple::sparcv9:
5696    switch (os) {
5697    case llvm::Triple::Linux:
5698      return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5699    case llvm::Triple::AuroraUX:
5700      return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5701    case llvm::Triple::Solaris:
5702      return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5703    case llvm::Triple::NetBSD:
5704      return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5705    case llvm::Triple::OpenBSD:
5706      return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5707    case llvm::Triple::FreeBSD:
5708      return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5709    default:
5710      return new SparcV9TargetInfo(Triple);
5711    }
5712
5713  case llvm::Triple::systemz:
5714    switch (os) {
5715    case llvm::Triple::Linux:
5716      return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5717    default:
5718      return new SystemZTargetInfo(Triple);
5719    }
5720
5721  case llvm::Triple::tce:
5722    return new TCETargetInfo(Triple);
5723
5724  case llvm::Triple::x86:
5725    if (Triple.isOSDarwin())
5726      return new DarwinI386TargetInfo(Triple);
5727
5728    switch (os) {
5729    case llvm::Triple::AuroraUX:
5730      return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5731    case llvm::Triple::Linux:
5732      return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5733    case llvm::Triple::DragonFly:
5734      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5735    case llvm::Triple::NetBSD:
5736      return new NetBSDI386TargetInfo(Triple);
5737    case llvm::Triple::OpenBSD:
5738      return new OpenBSDI386TargetInfo(Triple);
5739    case llvm::Triple::Bitrig:
5740      return new BitrigI386TargetInfo(Triple);
5741    case llvm::Triple::FreeBSD:
5742      return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5743    case llvm::Triple::KFreeBSD:
5744      return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5745    case llvm::Triple::Minix:
5746      return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5747    case llvm::Triple::Solaris:
5748      return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5749    case llvm::Triple::Cygwin:
5750      return new CygwinX86_32TargetInfo(Triple);
5751    case llvm::Triple::MinGW32:
5752      return new MinGWX86_32TargetInfo(Triple);
5753    case llvm::Triple::Win32:
5754      return new VisualStudioWindowsX86_32TargetInfo(Triple);
5755    case llvm::Triple::Haiku:
5756      return new HaikuX86_32TargetInfo(Triple);
5757    case llvm::Triple::RTEMS:
5758      return new RTEMSX86_32TargetInfo(Triple);
5759    case llvm::Triple::NaCl:
5760      return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5761    default:
5762      return new X86_32TargetInfo(Triple);
5763    }
5764
5765  case llvm::Triple::x86_64:
5766    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5767      return new DarwinX86_64TargetInfo(Triple);
5768
5769    switch (os) {
5770    case llvm::Triple::AuroraUX:
5771      return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5772    case llvm::Triple::Linux:
5773      return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5774    case llvm::Triple::DragonFly:
5775      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5776    case llvm::Triple::NetBSD:
5777      return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5778    case llvm::Triple::OpenBSD:
5779      return new OpenBSDX86_64TargetInfo(Triple);
5780    case llvm::Triple::Bitrig:
5781      return new BitrigX86_64TargetInfo(Triple);
5782    case llvm::Triple::FreeBSD:
5783      return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5784    case llvm::Triple::KFreeBSD:
5785      return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5786    case llvm::Triple::Solaris:
5787      return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5788    case llvm::Triple::MinGW32:
5789      return new MinGWX86_64TargetInfo(Triple);
5790    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5791      return new VisualStudioWindowsX86_64TargetInfo(Triple);
5792    case llvm::Triple::NaCl:
5793      return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5794    default:
5795      return new X86_64TargetInfo(Triple);
5796    }
5797
5798    case llvm::Triple::spir: {
5799      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5800          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5801        return NULL;
5802      return new SPIR32TargetInfo(Triple);
5803    }
5804    case llvm::Triple::spir64: {
5805      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5806          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5807        return NULL;
5808      return new SPIR64TargetInfo(Triple);
5809    }
5810  }
5811}
5812
5813/// CreateTargetInfo - Return the target info object for the specified target
5814/// triple.
5815TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5816                                         TargetOptions *Opts) {
5817  llvm::Triple Triple(Opts->Triple);
5818
5819  // Construct the target
5820  OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5821  if (!Target) {
5822    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5823    return 0;
5824  }
5825  Target->setTargetOpts(Opts);
5826
5827  // Set the target CPU if specified.
5828  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5829    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5830    return 0;
5831  }
5832
5833  // Set the target ABI if specified.
5834  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5835    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5836    return 0;
5837  }
5838
5839  // Set the target C++ ABI.
5840  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5841    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5842    return 0;
5843  }
5844
5845  // Set the fp math unit.
5846  if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
5847    Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
5848    return 0;
5849  }
5850
5851  // Compute the default target features, we need the target to handle this
5852  // because features may have dependencies on one another.
5853  llvm::StringMap<bool> Features;
5854  Target->getDefaultFeatures(Features);
5855
5856  // Apply the user specified deltas.
5857  for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
5858       I < N; ++I) {
5859    const char *Name = Opts->FeaturesAsWritten[I].c_str();
5860    // Apply the feature via the target.
5861    bool Enabled = Name[0] == '+';
5862    Target->setFeatureEnabled(Features, Name + 1, Enabled);
5863  }
5864
5865  // Add the features to the compile options.
5866  //
5867  // FIXME: If we are completely confident that we have the right set, we only
5868  // need to pass the minuses.
5869  Opts->Features.clear();
5870  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5871         ie = Features.end(); it != ie; ++it)
5872    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5873  if (!Target->handleTargetFeatures(Opts->Features, Diags))
5874    return 0;
5875
5876  return Target.take();
5877}
5878