Targets.cpp revision b2f6f4764e4d7da70b9ed99aa5bbb346018feedc 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
183    this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
184    this->MCountName = "\01mcount";
185  }
186
187  virtual std::string isValidSectionSpecifier(StringRef SR) const {
188    // Let MCSectionMachO validate this.
189    StringRef Segment, Section;
190    unsigned TAA, StubSize;
191    bool HasTAA;
192    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
193                                                       TAA, HasTAA, StubSize);
194  }
195
196  virtual const char *getStaticInitSectionSpecifier() const {
197    // FIXME: We should return 0 when building kexts.
198    return "__TEXT,__StaticInit,regular,pure_instructions";
199  }
200
201  /// Darwin does not support protected visibility.  Darwin's "default"
202  /// is very similar to ELF's "protected";  Darwin requires a "weak"
203  /// attribute on declarations that can be dynamically replaced.
204  virtual bool hasProtectedVisibility() const {
205    return false;
206  }
207};
208
209
210// DragonFlyBSD Target
211template<typename Target>
212class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
213protected:
214  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
215                            MacroBuilder &Builder) const {
216    // DragonFly defines; list based off of gcc output
217    Builder.defineMacro("__DragonFly__");
218    Builder.defineMacro("__DragonFly_cc_version", "100001");
219    Builder.defineMacro("__ELF__");
220    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
221    Builder.defineMacro("__tune_i386__");
222    DefineStd(Builder, "unix", Opts);
223  }
224public:
225  DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
226      : OSTargetInfo<Target>(Triple) {
227    this->UserLabelPrefix = "";
228
229    switch (Triple.getArch()) {
230    default:
231    case llvm::Triple::x86:
232    case llvm::Triple::x86_64:
233      this->MCountName = ".mcount";
234      break;
235    }
236  }
237};
238
239// FreeBSD Target
240template<typename Target>
241class FreeBSDTargetInfo : public OSTargetInfo<Target> {
242protected:
243  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
244                            MacroBuilder &Builder) const {
245    // FreeBSD defines; list based off of gcc output
246
247    unsigned Release = Triple.getOSMajorVersion();
248    if (Release == 0U)
249      Release = 8;
250
251    Builder.defineMacro("__FreeBSD__", Twine(Release));
252    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
253    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
254    DefineStd(Builder, "unix", Opts);
255    Builder.defineMacro("__ELF__");
256  }
257public:
258  FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
259    this->UserLabelPrefix = "";
260
261    switch (Triple.getArch()) {
262    default:
263    case llvm::Triple::x86:
264    case llvm::Triple::x86_64:
265      this->MCountName = ".mcount";
266      break;
267    case llvm::Triple::mips:
268    case llvm::Triple::mipsel:
269    case llvm::Triple::ppc:
270    case llvm::Triple::ppc64:
271      this->MCountName = "_mcount";
272      break;
273    case llvm::Triple::arm:
274      this->MCountName = "__mcount";
275      break;
276    }
277  }
278};
279
280// Minix Target
281template<typename Target>
282class MinixTargetInfo : public OSTargetInfo<Target> {
283protected:
284  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
285                            MacroBuilder &Builder) const {
286    // Minix defines
287
288    Builder.defineMacro("__minix", "3");
289    Builder.defineMacro("_EM_WSIZE", "4");
290    Builder.defineMacro("_EM_PSIZE", "4");
291    Builder.defineMacro("_EM_SSIZE", "2");
292    Builder.defineMacro("_EM_LSIZE", "4");
293    Builder.defineMacro("_EM_FSIZE", "4");
294    Builder.defineMacro("_EM_DSIZE", "8");
295    Builder.defineMacro("__ELF__");
296    DefineStd(Builder, "unix", Opts);
297  }
298public:
299  MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
300    this->UserLabelPrefix = "";
301  }
302};
303
304// Linux target
305template<typename Target>
306class LinuxTargetInfo : public OSTargetInfo<Target> {
307protected:
308  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
309                            MacroBuilder &Builder) const {
310    // Linux defines; list based off of gcc output
311    DefineStd(Builder, "unix", Opts);
312    DefineStd(Builder, "linux", Opts);
313    Builder.defineMacro("__gnu_linux__");
314    Builder.defineMacro("__ELF__");
315    if (Triple.getEnvironment() == llvm::Triple::Android)
316      Builder.defineMacro("__ANDROID__", "1");
317    if (Opts.POSIXThreads)
318      Builder.defineMacro("_REENTRANT");
319    if (Opts.CPlusPlus)
320      Builder.defineMacro("_GNU_SOURCE");
321  }
322public:
323  LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
324    this->UserLabelPrefix = "";
325    this->WIntType = TargetInfo::UnsignedInt;
326  }
327
328  virtual const char *getStaticInitSectionSpecifier() const {
329    return ".text.startup";
330  }
331};
332
333// NetBSD Target
334template<typename Target>
335class NetBSDTargetInfo : public OSTargetInfo<Target> {
336protected:
337  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
338                            MacroBuilder &Builder) const {
339    // NetBSD defines; list based off of gcc output
340    Builder.defineMacro("__NetBSD__");
341    Builder.defineMacro("__unix__");
342    Builder.defineMacro("__ELF__");
343    if (Opts.POSIXThreads)
344      Builder.defineMacro("_POSIX_THREADS");
345  }
346public:
347  NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
348    this->UserLabelPrefix = "";
349  }
350};
351
352// OpenBSD Target
353template<typename Target>
354class OpenBSDTargetInfo : public OSTargetInfo<Target> {
355protected:
356  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
357                            MacroBuilder &Builder) const {
358    // OpenBSD defines; list based off of gcc output
359
360    Builder.defineMacro("__OpenBSD__");
361    DefineStd(Builder, "unix", Opts);
362    Builder.defineMacro("__ELF__");
363    if (Opts.POSIXThreads)
364      Builder.defineMacro("_REENTRANT");
365  }
366public:
367  OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
368    this->UserLabelPrefix = "";
369    this->TLSSupported = false;
370
371      switch (Triple.getArch()) {
372        default:
373        case llvm::Triple::x86:
374        case llvm::Triple::x86_64:
375        case llvm::Triple::arm:
376        case llvm::Triple::sparc:
377          this->MCountName = "__mcount";
378          break;
379        case llvm::Triple::mips64:
380        case llvm::Triple::mips64el:
381        case llvm::Triple::ppc:
382        case llvm::Triple::sparcv9:
383          this->MCountName = "_mcount";
384          break;
385      }
386  }
387};
388
389// Bitrig Target
390template<typename Target>
391class BitrigTargetInfo : public OSTargetInfo<Target> {
392protected:
393  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
394                            MacroBuilder &Builder) const {
395    // Bitrig defines; list based off of gcc output
396
397    Builder.defineMacro("__Bitrig__");
398    DefineStd(Builder, "unix", Opts);
399    Builder.defineMacro("__ELF__");
400    if (Opts.POSIXThreads)
401      Builder.defineMacro("_REENTRANT");
402  }
403public:
404  BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
405    this->UserLabelPrefix = "";
406    this->TLSSupported = false;
407    this->MCountName = "__mcount";
408  }
409};
410
411// PSP Target
412template<typename Target>
413class PSPTargetInfo : public OSTargetInfo<Target> {
414protected:
415  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
416                            MacroBuilder &Builder) const {
417    // PSP defines; list based on the output of the pspdev gcc toolchain.
418    Builder.defineMacro("PSP");
419    Builder.defineMacro("_PSP");
420    Builder.defineMacro("__psp__");
421    Builder.defineMacro("__ELF__");
422  }
423public:
424  PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
425    this->UserLabelPrefix = "";
426  }
427};
428
429// PS3 PPU Target
430template<typename Target>
431class PS3PPUTargetInfo : public OSTargetInfo<Target> {
432protected:
433  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434                            MacroBuilder &Builder) const {
435    // PS3 PPU defines.
436    Builder.defineMacro("__PPC__");
437    Builder.defineMacro("__PPU__");
438    Builder.defineMacro("__CELLOS_LV2__");
439    Builder.defineMacro("__ELF__");
440    Builder.defineMacro("__LP32__");
441    Builder.defineMacro("_ARCH_PPC64");
442    Builder.defineMacro("__powerpc64__");
443  }
444public:
445  PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
446    this->UserLabelPrefix = "";
447    this->LongWidth = this->LongAlign = 32;
448    this->PointerWidth = this->PointerAlign = 32;
449    this->IntMaxType = TargetInfo::SignedLongLong;
450    this->UIntMaxType = TargetInfo::UnsignedLongLong;
451    this->Int64Type = TargetInfo::SignedLongLong;
452    this->SizeType = TargetInfo::UnsignedInt;
453    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
454                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
455  }
456};
457
458// FIXME: Need a real SPU target.
459// PS3 SPU Target
460template<typename Target>
461class PS3SPUTargetInfo : public OSTargetInfo<Target> {
462protected:
463  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
464                            MacroBuilder &Builder) const {
465    // PS3 PPU defines.
466    Builder.defineMacro("__SPU__");
467    Builder.defineMacro("__ELF__");
468  }
469public:
470  PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
471    this->UserLabelPrefix = "";
472  }
473};
474
475// AuroraUX target
476template<typename Target>
477class AuroraUXTargetInfo : public OSTargetInfo<Target> {
478protected:
479  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480                            MacroBuilder &Builder) const {
481    DefineStd(Builder, "sun", Opts);
482    DefineStd(Builder, "unix", Opts);
483    Builder.defineMacro("__ELF__");
484    Builder.defineMacro("__svr4__");
485    Builder.defineMacro("__SVR4");
486  }
487public:
488  AuroraUXTargetInfo(const llvm::Triple &Triple)
489      : OSTargetInfo<Target>(Triple) {
490    this->UserLabelPrefix = "";
491    this->WCharType = this->SignedLong;
492    // FIXME: WIntType should be SignedLong
493  }
494};
495
496// Solaris target
497template<typename Target>
498class SolarisTargetInfo : public OSTargetInfo<Target> {
499protected:
500  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
501                            MacroBuilder &Builder) const {
502    DefineStd(Builder, "sun", Opts);
503    DefineStd(Builder, "unix", Opts);
504    Builder.defineMacro("__ELF__");
505    Builder.defineMacro("__svr4__");
506    Builder.defineMacro("__SVR4");
507    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
508    // newer, but to 500 for everything else.  feature_test.h has a check to
509    // ensure that you are not using C99 with an old version of X/Open or C89
510    // with a new version.
511    if (Opts.C99 || Opts.C11)
512      Builder.defineMacro("_XOPEN_SOURCE", "600");
513    else
514      Builder.defineMacro("_XOPEN_SOURCE", "500");
515    if (Opts.CPlusPlus)
516      Builder.defineMacro("__C99FEATURES__");
517    Builder.defineMacro("_LARGEFILE_SOURCE");
518    Builder.defineMacro("_LARGEFILE64_SOURCE");
519    Builder.defineMacro("__EXTENSIONS__");
520    Builder.defineMacro("_REENTRANT");
521  }
522public:
523  SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
524    this->UserLabelPrefix = "";
525    this->WCharType = this->SignedInt;
526    // FIXME: WIntType should be SignedLong
527  }
528};
529
530// Windows target
531template<typename Target>
532class WindowsTargetInfo : public OSTargetInfo<Target> {
533protected:
534  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
535                            MacroBuilder &Builder) const {
536    Builder.defineMacro("_WIN32");
537  }
538  void getVisualStudioDefines(const LangOptions &Opts,
539                              MacroBuilder &Builder) const {
540    if (Opts.CPlusPlus) {
541      if (Opts.RTTI)
542        Builder.defineMacro("_CPPRTTI");
543
544      if (Opts.Exceptions)
545        Builder.defineMacro("_CPPUNWIND");
546    }
547
548    if (!Opts.CharIsSigned)
549      Builder.defineMacro("_CHAR_UNSIGNED");
550
551    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
552    //        but it works for now.
553    if (Opts.POSIXThreads)
554      Builder.defineMacro("_MT");
555
556    if (Opts.MSCVersion != 0)
557      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
558
559    if (Opts.MicrosoftExt) {
560      Builder.defineMacro("_MSC_EXTENSIONS");
561
562      if (Opts.CPlusPlus11) {
563        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
564        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
565        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
566      }
567    }
568
569    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
570  }
571
572public:
573  WindowsTargetInfo(const llvm::Triple &Triple)
574      : OSTargetInfo<Target>(Triple) {}
575};
576
577template <typename Target>
578class NaClTargetInfo : public OSTargetInfo<Target> {
579protected:
580  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
581                            MacroBuilder &Builder) const {
582    if (Opts.POSIXThreads)
583      Builder.defineMacro("_REENTRANT");
584    if (Opts.CPlusPlus)
585      Builder.defineMacro("_GNU_SOURCE");
586
587    DefineStd(Builder, "unix", Opts);
588    Builder.defineMacro("__ELF__");
589    Builder.defineMacro("__native_client__");
590  }
591
592public:
593  NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
594    this->UserLabelPrefix = "";
595    this->LongAlign = 32;
596    this->LongWidth = 32;
597    this->PointerAlign = 32;
598    this->PointerWidth = 32;
599    this->IntMaxType = TargetInfo::SignedLongLong;
600    this->UIntMaxType = TargetInfo::UnsignedLongLong;
601    this->Int64Type = TargetInfo::SignedLongLong;
602    this->DoubleAlign = 64;
603    this->LongDoubleWidth = 64;
604    this->LongDoubleAlign = 64;
605    this->SizeType = TargetInfo::UnsignedInt;
606    this->PtrDiffType = TargetInfo::SignedInt;
607    this->IntPtrType = TargetInfo::SignedInt;
608    // RegParmMax is inherited from the underlying architecture
609    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
610    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
611                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
612  }
613  virtual typename Target::CallingConvCheckResult checkCallingConvention(
614      CallingConv CC) const {
615    return CC == CC_PnaclCall ? Target::CCCR_OK :
616        Target::checkCallingConvention(CC);
617  }
618};
619} // end anonymous namespace.
620
621//===----------------------------------------------------------------------===//
622// Specific target implementations.
623//===----------------------------------------------------------------------===//
624
625namespace {
626// PPC abstract base class
627class PPCTargetInfo : public TargetInfo {
628  static const Builtin::Info BuiltinInfo[];
629  static const char * const GCCRegNames[];
630  static const TargetInfo::GCCRegAlias GCCRegAliases[];
631  std::string CPU;
632public:
633  PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
634    LongDoubleWidth = LongDoubleAlign = 128;
635    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
636  }
637
638  /// \brief Flags for architecture specific defines.
639  typedef enum {
640    ArchDefineNone  = 0,
641    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
642    ArchDefinePpcgr = 1 << 1,
643    ArchDefinePpcsq = 1 << 2,
644    ArchDefine440   = 1 << 3,
645    ArchDefine603   = 1 << 4,
646    ArchDefine604   = 1 << 5,
647    ArchDefinePwr4  = 1 << 6,
648    ArchDefinePwr5  = 1 << 7,
649    ArchDefinePwr5x = 1 << 8,
650    ArchDefinePwr6  = 1 << 9,
651    ArchDefinePwr6x = 1 << 10,
652    ArchDefinePwr7  = 1 << 11,
653    ArchDefineA2    = 1 << 12,
654    ArchDefineA2q   = 1 << 13
655  } ArchDefineTypes;
656
657  // Note: GCC recognizes the following additional cpus:
658  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
659  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
660  //  titan, rs64.
661  virtual bool setCPU(const std::string &Name) {
662    bool CPUKnown = llvm::StringSwitch<bool>(Name)
663      .Case("generic", true)
664      .Case("440", true)
665      .Case("450", true)
666      .Case("601", true)
667      .Case("602", true)
668      .Case("603", true)
669      .Case("603e", true)
670      .Case("603ev", true)
671      .Case("604", true)
672      .Case("604e", true)
673      .Case("620", true)
674      .Case("630", true)
675      .Case("g3", true)
676      .Case("7400", true)
677      .Case("g4", true)
678      .Case("7450", true)
679      .Case("g4+", true)
680      .Case("750", true)
681      .Case("970", true)
682      .Case("g5", true)
683      .Case("a2", true)
684      .Case("a2q", true)
685      .Case("e500mc", true)
686      .Case("e5500", true)
687      .Case("power3", true)
688      .Case("pwr3", true)
689      .Case("power4", true)
690      .Case("pwr4", true)
691      .Case("power5", true)
692      .Case("pwr5", true)
693      .Case("power5x", true)
694      .Case("pwr5x", true)
695      .Case("power6", true)
696      .Case("pwr6", true)
697      .Case("power6x", true)
698      .Case("pwr6x", true)
699      .Case("power7", true)
700      .Case("pwr7", true)
701      .Case("powerpc", true)
702      .Case("ppc", true)
703      .Case("powerpc64", true)
704      .Case("ppc64", true)
705      .Default(false);
706
707    if (CPUKnown)
708      CPU = Name;
709
710    return CPUKnown;
711  }
712
713  virtual void getTargetBuiltins(const Builtin::Info *&Records,
714                                 unsigned &NumRecords) const {
715    Records = BuiltinInfo;
716    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
717  }
718
719  virtual bool isCLZForZeroUndef() const { return false; }
720
721  virtual void getTargetDefines(const LangOptions &Opts,
722                                MacroBuilder &Builder) const;
723
724  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
725
726  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
727                                 StringRef Name,
728                                 bool Enabled) const;
729
730  virtual bool hasFeature(StringRef Feature) const;
731
732  virtual void getGCCRegNames(const char * const *&Names,
733                              unsigned &NumNames) const;
734  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
735                                unsigned &NumAliases) const;
736  virtual bool validateAsmConstraint(const char *&Name,
737                                     TargetInfo::ConstraintInfo &Info) const {
738    switch (*Name) {
739    default: return false;
740    case 'O': // Zero
741      break;
742    case 'b': // Base register
743    case 'f': // Floating point register
744      Info.setAllowsRegister();
745      break;
746    // FIXME: The following are added to allow parsing.
747    // I just took a guess at what the actions should be.
748    // Also, is more specific checking needed?  I.e. specific registers?
749    case 'd': // Floating point register (containing 64-bit value)
750    case 'v': // Altivec vector register
751      Info.setAllowsRegister();
752      break;
753    case 'w':
754      switch (Name[1]) {
755        case 'd':// VSX vector register to hold vector double data
756        case 'f':// VSX vector register to hold vector float data
757        case 's':// VSX vector register to hold scalar float data
758        case 'a':// Any VSX register
759          break;
760        default:
761          return false;
762      }
763      Info.setAllowsRegister();
764      Name++; // Skip over 'w'.
765      break;
766    case 'h': // `MQ', `CTR', or `LINK' register
767    case 'q': // `MQ' register
768    case 'c': // `CTR' register
769    case 'l': // `LINK' register
770    case 'x': // `CR' register (condition register) number 0
771    case 'y': // `CR' register (condition register)
772    case 'z': // `XER[CA]' carry bit (part of the XER register)
773      Info.setAllowsRegister();
774      break;
775    case 'I': // Signed 16-bit constant
776    case 'J': // Unsigned 16-bit constant shifted left 16 bits
777              //  (use `L' instead for SImode constants)
778    case 'K': // Unsigned 16-bit constant
779    case 'L': // Signed 16-bit constant shifted left 16 bits
780    case 'M': // Constant larger than 31
781    case 'N': // Exact power of 2
782    case 'P': // Constant whose negation is a signed 16-bit constant
783    case 'G': // Floating point constant that can be loaded into a
784              // register with one instruction per word
785    case 'H': // Integer/Floating point constant that can be loaded
786              // into a register using three instructions
787      break;
788    case 'm': // Memory operand. Note that on PowerPC targets, m can
789              // include addresses that update the base register. It
790              // is therefore only safe to use `m' in an asm statement
791              // if that asm statement accesses the operand exactly once.
792              // The asm statement must also use `%U<opno>' as a
793              // placeholder for the "update" flag in the corresponding
794              // load or store instruction. For example:
795              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
796              // is correct but:
797              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
798              // is not. Use es rather than m if you don't want the base
799              // register to be updated.
800    case 'e':
801      if (Name[1] != 's')
802          return false;
803              // es: A "stable" memory operand; that is, one which does not
804              // include any automodification of the base register. Unlike
805              // `m', this constraint can be used in asm statements that
806              // might access the operand several times, or that might not
807              // access it at all.
808      Info.setAllowsMemory();
809      Name++; // Skip over 'e'.
810      break;
811    case 'Q': // Memory operand that is an offset from a register (it is
812              // usually better to use `m' or `es' in asm statements)
813    case 'Z': // Memory operand that is an indexed or indirect from a
814              // register (it is usually better to use `m' or `es' in
815              // asm statements)
816      Info.setAllowsMemory();
817      Info.setAllowsRegister();
818      break;
819    case 'R': // AIX TOC entry
820    case 'a': // Address operand that is an indexed or indirect from a
821              // register (`p' is preferable for asm statements)
822    case 'S': // Constant suitable as a 64-bit mask operand
823    case 'T': // Constant suitable as a 32-bit mask operand
824    case 'U': // System V Release 4 small data area reference
825    case 't': // AND masks that can be performed by two rldic{l, r}
826              // instructions
827    case 'W': // Vector constant that does not require memory
828    case 'j': // Vector constant that is all zeros.
829      break;
830    // End FIXME.
831    }
832    return true;
833  }
834  virtual const char *getClobbers() const {
835    return "";
836  }
837  int getEHDataRegisterNumber(unsigned RegNo) const {
838    if (RegNo == 0) return 3;
839    if (RegNo == 1) return 4;
840    return -1;
841  }
842};
843
844const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
845#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
846#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
847                                              ALL_LANGUAGES },
848#include "clang/Basic/BuiltinsPPC.def"
849};
850
851
852/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
853/// #defines that are not tied to a specific subtarget.
854void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
855                                     MacroBuilder &Builder) const {
856  // Target identification.
857  Builder.defineMacro("__ppc__");
858  Builder.defineMacro("__PPC__");
859  Builder.defineMacro("_ARCH_PPC");
860  Builder.defineMacro("__powerpc__");
861  Builder.defineMacro("__POWERPC__");
862  if (PointerWidth == 64) {
863    Builder.defineMacro("_ARCH_PPC64");
864    Builder.defineMacro("__powerpc64__");
865    Builder.defineMacro("__ppc64__");
866    Builder.defineMacro("__PPC64__");
867  }
868
869  // Target properties.
870  if (getTriple().getOS() != llvm::Triple::NetBSD &&
871      getTriple().getOS() != llvm::Triple::OpenBSD)
872    Builder.defineMacro("_BIG_ENDIAN");
873  Builder.defineMacro("__BIG_ENDIAN__");
874
875  // Subtarget options.
876  Builder.defineMacro("__NATURAL_ALIGNMENT__");
877  Builder.defineMacro("__REGISTER_PREFIX__", "");
878
879  // FIXME: Should be controlled by command line option.
880  if (LongDoubleWidth == 128)
881    Builder.defineMacro("__LONG_DOUBLE_128__");
882
883  if (Opts.AltiVec) {
884    Builder.defineMacro("__VEC__", "10206");
885    Builder.defineMacro("__ALTIVEC__");
886  }
887
888  // CPU identification.
889  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
890    .Case("440",   ArchDefineName)
891    .Case("450",   ArchDefineName | ArchDefine440)
892    .Case("601",   ArchDefineName)
893    .Case("602",   ArchDefineName | ArchDefinePpcgr)
894    .Case("603",   ArchDefineName | ArchDefinePpcgr)
895    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
896    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
897    .Case("604",   ArchDefineName | ArchDefinePpcgr)
898    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
899    .Case("620",   ArchDefineName | ArchDefinePpcgr)
900    .Case("630",   ArchDefineName | ArchDefinePpcgr)
901    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
902    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
903    .Case("750",   ArchDefineName | ArchDefinePpcgr)
904    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
905                     | ArchDefinePpcsq)
906    .Case("a2",    ArchDefineA2)
907    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
908    .Case("pwr3",  ArchDefinePpcgr)
909    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
910    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
911                     | ArchDefinePpcsq)
912    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
913                     | ArchDefinePpcgr | ArchDefinePpcsq)
914    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
915                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
916    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
917                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
918                     | ArchDefinePpcsq)
919    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
920                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
921                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
922    .Case("power3",  ArchDefinePpcgr)
923    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
924    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
925                       | ArchDefinePpcsq)
926    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
927                       | ArchDefinePpcgr | ArchDefinePpcsq)
928    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
929                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
930    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
931                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
932                       | ArchDefinePpcsq)
933    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
934                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
935                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
936    .Default(ArchDefineNone);
937
938  if (defs & ArchDefineName)
939    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
940  if (defs & ArchDefinePpcgr)
941    Builder.defineMacro("_ARCH_PPCGR");
942  if (defs & ArchDefinePpcsq)
943    Builder.defineMacro("_ARCH_PPCSQ");
944  if (defs & ArchDefine440)
945    Builder.defineMacro("_ARCH_440");
946  if (defs & ArchDefine603)
947    Builder.defineMacro("_ARCH_603");
948  if (defs & ArchDefine604)
949    Builder.defineMacro("_ARCH_604");
950  if (defs & ArchDefinePwr4)
951    Builder.defineMacro("_ARCH_PWR4");
952  if (defs & ArchDefinePwr5)
953    Builder.defineMacro("_ARCH_PWR5");
954  if (defs & ArchDefinePwr5x)
955    Builder.defineMacro("_ARCH_PWR5X");
956  if (defs & ArchDefinePwr6)
957    Builder.defineMacro("_ARCH_PWR6");
958  if (defs & ArchDefinePwr6x)
959    Builder.defineMacro("_ARCH_PWR6X");
960  if (defs & ArchDefinePwr7)
961    Builder.defineMacro("_ARCH_PWR7");
962  if (defs & ArchDefineA2)
963    Builder.defineMacro("_ARCH_A2");
964  if (defs & ArchDefineA2q) {
965    Builder.defineMacro("_ARCH_A2Q");
966    Builder.defineMacro("_ARCH_QP");
967  }
968
969  if (getTriple().getVendor() == llvm::Triple::BGQ) {
970    Builder.defineMacro("__bg__");
971    Builder.defineMacro("__THW_BLUEGENE__");
972    Builder.defineMacro("__bgq__");
973    Builder.defineMacro("__TOS_BGQ__");
974  }
975
976  // FIXME: The following are not yet generated here by Clang, but are
977  //        generated by GCC:
978  //
979  //   _SOFT_FLOAT_
980  //   __RECIP_PRECISION__
981  //   __APPLE_ALTIVEC__
982  //   __VSX__
983  //   __RECIP__
984  //   __RECIPF__
985  //   __RSQRTE__
986  //   __RSQRTEF__
987  //   _SOFT_DOUBLE_
988  //   __NO_LWSYNC__
989  //   __HAVE_BSWAP__
990  //   __LONGDOUBLE128
991  //   __CMODEL_MEDIUM__
992  //   __CMODEL_LARGE__
993  //   _CALL_SYSV
994  //   _CALL_DARWIN
995  //   __NO_FPRS__
996}
997
998void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
999  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1000    .Case("7400", true)
1001    .Case("g4", true)
1002    .Case("7450", true)
1003    .Case("g4+", true)
1004    .Case("970", true)
1005    .Case("g5", true)
1006    .Case("pwr6", true)
1007    .Case("pwr7", true)
1008    .Case("ppc64", true)
1009    .Default(false);
1010
1011  Features["qpx"] = (CPU == "a2q");
1012}
1013
1014bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1015                                         StringRef Name,
1016                                         bool Enabled) const {
1017  if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1018      Name == "popcntd" || Name == "qpx") {
1019    Features[Name] = Enabled;
1020    return true;
1021  }
1022
1023  return false;
1024}
1025
1026bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1027  return Feature == "powerpc";
1028}
1029
1030
1031const char * const PPCTargetInfo::GCCRegNames[] = {
1032  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1033  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1034  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1035  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1036  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1037  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1038  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1039  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1040  "mq", "lr", "ctr", "ap",
1041  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1042  "xer",
1043  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1044  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1045  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1046  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1047  "vrsave", "vscr",
1048  "spe_acc", "spefscr",
1049  "sfp"
1050};
1051
1052void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1053                                   unsigned &NumNames) const {
1054  Names = GCCRegNames;
1055  NumNames = llvm::array_lengthof(GCCRegNames);
1056}
1057
1058const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1059  // While some of these aliases do map to different registers
1060  // they still share the same register name.
1061  { { "0" }, "r0" },
1062  { { "1"}, "r1" },
1063  { { "2" }, "r2" },
1064  { { "3" }, "r3" },
1065  { { "4" }, "r4" },
1066  { { "5" }, "r5" },
1067  { { "6" }, "r6" },
1068  { { "7" }, "r7" },
1069  { { "8" }, "r8" },
1070  { { "9" }, "r9" },
1071  { { "10" }, "r10" },
1072  { { "11" }, "r11" },
1073  { { "12" }, "r12" },
1074  { { "13" }, "r13" },
1075  { { "14" }, "r14" },
1076  { { "15" }, "r15" },
1077  { { "16" }, "r16" },
1078  { { "17" }, "r17" },
1079  { { "18" }, "r18" },
1080  { { "19" }, "r19" },
1081  { { "20" }, "r20" },
1082  { { "21" }, "r21" },
1083  { { "22" }, "r22" },
1084  { { "23" }, "r23" },
1085  { { "24" }, "r24" },
1086  { { "25" }, "r25" },
1087  { { "26" }, "r26" },
1088  { { "27" }, "r27" },
1089  { { "28" }, "r28" },
1090  { { "29" }, "r29" },
1091  { { "30" }, "r30" },
1092  { { "31" }, "r31" },
1093  { { "fr0" }, "f0" },
1094  { { "fr1" }, "f1" },
1095  { { "fr2" }, "f2" },
1096  { { "fr3" }, "f3" },
1097  { { "fr4" }, "f4" },
1098  { { "fr5" }, "f5" },
1099  { { "fr6" }, "f6" },
1100  { { "fr7" }, "f7" },
1101  { { "fr8" }, "f8" },
1102  { { "fr9" }, "f9" },
1103  { { "fr10" }, "f10" },
1104  { { "fr11" }, "f11" },
1105  { { "fr12" }, "f12" },
1106  { { "fr13" }, "f13" },
1107  { { "fr14" }, "f14" },
1108  { { "fr15" }, "f15" },
1109  { { "fr16" }, "f16" },
1110  { { "fr17" }, "f17" },
1111  { { "fr18" }, "f18" },
1112  { { "fr19" }, "f19" },
1113  { { "fr20" }, "f20" },
1114  { { "fr21" }, "f21" },
1115  { { "fr22" }, "f22" },
1116  { { "fr23" }, "f23" },
1117  { { "fr24" }, "f24" },
1118  { { "fr25" }, "f25" },
1119  { { "fr26" }, "f26" },
1120  { { "fr27" }, "f27" },
1121  { { "fr28" }, "f28" },
1122  { { "fr29" }, "f29" },
1123  { { "fr30" }, "f30" },
1124  { { "fr31" }, "f31" },
1125  { { "cc" }, "cr0" },
1126};
1127
1128void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1129                                     unsigned &NumAliases) const {
1130  Aliases = GCCRegAliases;
1131  NumAliases = llvm::array_lengthof(GCCRegAliases);
1132}
1133} // end anonymous namespace.
1134
1135namespace {
1136class PPC32TargetInfo : public PPCTargetInfo {
1137public:
1138  PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1139    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1140                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1141
1142    switch (getTriple().getOS()) {
1143    case llvm::Triple::Linux:
1144    case llvm::Triple::FreeBSD:
1145    case llvm::Triple::NetBSD:
1146      SizeType = UnsignedInt;
1147      PtrDiffType = SignedInt;
1148      IntPtrType = SignedInt;
1149      break;
1150    default:
1151      break;
1152    }
1153
1154    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1155      LongDoubleWidth = LongDoubleAlign = 64;
1156      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1157    }
1158
1159    // PPC32 supports atomics up to 4 bytes.
1160    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1161  }
1162
1163  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1164    // This is the ELF definition, and is overridden by the Darwin sub-target
1165    return TargetInfo::PowerABIBuiltinVaList;
1166  }
1167};
1168} // end anonymous namespace.
1169
1170namespace {
1171class PPC64TargetInfo : public PPCTargetInfo {
1172public:
1173  PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1174    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1175    IntMaxType = SignedLong;
1176    UIntMaxType = UnsignedLong;
1177    Int64Type = SignedLong;
1178
1179    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1180      LongDoubleWidth = LongDoubleAlign = 64;
1181      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1182      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1183                          "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1184                          "v128:128:128-n32:64";
1185    } else
1186      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1187                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1188                          "v128:128:128-n32:64";
1189
1190    // PPC64 supports atomics up to 8 bytes.
1191    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1192  }
1193  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1194    return TargetInfo::CharPtrBuiltinVaList;
1195  }
1196};
1197} // end anonymous namespace.
1198
1199
1200namespace {
1201class DarwinPPC32TargetInfo :
1202  public DarwinTargetInfo<PPC32TargetInfo> {
1203public:
1204  DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1205      : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1206    HasAlignMac68kSupport = true;
1207    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1208    PtrDiffType = SignedInt;	// for http://llvm.org/bugs/show_bug.cgi?id=15726
1209    LongLongAlign = 32;
1210    SuitableAlign = 128;
1211    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1212                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1213  }
1214  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1215    return TargetInfo::CharPtrBuiltinVaList;
1216  }
1217};
1218
1219class DarwinPPC64TargetInfo :
1220  public DarwinTargetInfo<PPC64TargetInfo> {
1221public:
1222  DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1223      : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1224    HasAlignMac68kSupport = true;
1225    SuitableAlign = 128;
1226    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1227                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1228  }
1229};
1230} // end anonymous namespace.
1231
1232namespace {
1233  static const unsigned NVPTXAddrSpaceMap[] = {
1234    1,    // opencl_global
1235    3,    // opencl_local
1236    4,    // opencl_constant
1237    1,    // cuda_device
1238    4,    // cuda_constant
1239    3,    // cuda_shared
1240  };
1241  class NVPTXTargetInfo : public TargetInfo {
1242    static const char * const GCCRegNames[];
1243    static const Builtin::Info BuiltinInfo[];
1244    std::vector<StringRef> AvailableFeatures;
1245  public:
1246    NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1247      BigEndian = false;
1248      TLSSupported = false;
1249      LongWidth = LongAlign = 64;
1250      AddrSpaceMap = &NVPTXAddrSpaceMap;
1251      // Define available target features
1252      // These must be defined in sorted order!
1253      NoAsmVariants = true;
1254    }
1255    virtual void getTargetDefines(const LangOptions &Opts,
1256                                  MacroBuilder &Builder) const {
1257      Builder.defineMacro("__PTX__");
1258      Builder.defineMacro("__NVPTX__");
1259    }
1260    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1261                                   unsigned &NumRecords) const {
1262      Records = BuiltinInfo;
1263      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1264    }
1265    virtual bool hasFeature(StringRef Feature) const {
1266      return Feature == "ptx" || Feature == "nvptx";
1267    }
1268
1269    virtual void getGCCRegNames(const char * const *&Names,
1270                                unsigned &NumNames) const;
1271    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1272                                  unsigned &NumAliases) const {
1273      // No aliases.
1274      Aliases = 0;
1275      NumAliases = 0;
1276    }
1277    virtual bool validateAsmConstraint(const char *&Name,
1278                                       TargetInfo::ConstraintInfo &Info) const {
1279      switch (*Name) {
1280      default: return false;
1281      case 'c':
1282      case 'h':
1283      case 'r':
1284      case 'l':
1285      case 'f':
1286      case 'd':
1287        Info.setAllowsRegister();
1288        return true;
1289      }
1290    }
1291    virtual const char *getClobbers() const {
1292      // FIXME: Is this really right?
1293      return "";
1294    }
1295    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1296      // FIXME: implement
1297      return TargetInfo::CharPtrBuiltinVaList;
1298    }
1299    virtual bool setCPU(const std::string &Name) {
1300      bool Valid = llvm::StringSwitch<bool>(Name)
1301        .Case("sm_20", true)
1302        .Case("sm_21", true)
1303        .Case("sm_30", true)
1304        .Case("sm_35", true)
1305        .Default(false);
1306
1307      return Valid;
1308    }
1309    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1310                                   StringRef Name,
1311                                   bool Enabled) const;
1312  };
1313
1314  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1315#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1316#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1317                                              ALL_LANGUAGES },
1318#include "clang/Basic/BuiltinsNVPTX.def"
1319  };
1320
1321  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1322    "r0"
1323  };
1324
1325  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1326                                     unsigned &NumNames) const {
1327    Names = GCCRegNames;
1328    NumNames = llvm::array_lengthof(GCCRegNames);
1329  }
1330
1331  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1332                                          StringRef Name,
1333                                          bool Enabled) const {
1334    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1335                          Name)) {
1336      Features[Name] = Enabled;
1337      return true;
1338    } else {
1339      return false;
1340    }
1341  }
1342
1343  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1344  public:
1345    NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1346      PointerWidth = PointerAlign = 32;
1347      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1348      DescriptionString
1349        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1350          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1351          "n16:32:64";
1352  }
1353  };
1354
1355  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1356  public:
1357    NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1358      PointerWidth = PointerAlign = 64;
1359      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1360      DescriptionString
1361        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1362          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1363          "n16:32:64";
1364  }
1365  };
1366}
1367
1368namespace {
1369
1370static const unsigned R600AddrSpaceMap[] = {
1371  1,    // opencl_global
1372  3,    // opencl_local
1373  2,    // opencl_constant
1374  1,    // cuda_device
1375  2,    // cuda_constant
1376  3     // cuda_shared
1377};
1378
1379static const char *DescriptionStringR600 =
1380  "e"
1381  "-p:32:32:32"
1382  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1383  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1384  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1385  "-n32:64";
1386
1387static const char *DescriptionStringR600DoubleOps =
1388  "e"
1389  "-p:32:32:32"
1390  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1391  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1392  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1393  "-n32:64";
1394
1395static const char *DescriptionStringSI =
1396  "e"
1397  "-p:64:64:64"
1398  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1399  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1400  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1401  "-n32:64";
1402
1403class R600TargetInfo : public TargetInfo {
1404  /// \brief The GPU profiles supported by the R600 target.
1405  enum GPUKind {
1406    GK_NONE,
1407    GK_R600,
1408    GK_R600_DOUBLE_OPS,
1409    GK_R700,
1410    GK_R700_DOUBLE_OPS,
1411    GK_EVERGREEN,
1412    GK_EVERGREEN_DOUBLE_OPS,
1413    GK_NORTHERN_ISLANDS,
1414    GK_CAYMAN,
1415    GK_SOUTHERN_ISLANDS
1416  } GPU;
1417
1418public:
1419  R600TargetInfo(const llvm::Triple &Triple)
1420      : TargetInfo(Triple), GPU(GK_R600) {
1421    DescriptionString = DescriptionStringR600;
1422    AddrSpaceMap = &R600AddrSpaceMap;
1423  }
1424
1425  virtual const char * getClobbers() const {
1426    return "";
1427  }
1428
1429  virtual void getGCCRegNames(const char * const *&Names,
1430                              unsigned &numNames) const  {
1431    Names = NULL;
1432    numNames = 0;
1433  }
1434
1435  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1436                                unsigned &NumAliases) const {
1437    Aliases = NULL;
1438    NumAliases = 0;
1439  }
1440
1441  virtual bool validateAsmConstraint(const char *&Name,
1442                                     TargetInfo::ConstraintInfo &info) const {
1443    return true;
1444  }
1445
1446  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1447                                 unsigned &NumRecords) const {
1448    Records = NULL;
1449    NumRecords = 0;
1450  }
1451
1452
1453  virtual void getTargetDefines(const LangOptions &Opts,
1454                                MacroBuilder &Builder) const {
1455    Builder.defineMacro("__R600__");
1456  }
1457
1458  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1459    return TargetInfo::CharPtrBuiltinVaList;
1460  }
1461
1462  virtual bool setCPU(const std::string &Name) {
1463    GPU = llvm::StringSwitch<GPUKind>(Name)
1464      .Case("r600" ,    GK_R600)
1465      .Case("rv610",    GK_R600)
1466      .Case("rv620",    GK_R600)
1467      .Case("rv630",    GK_R600)
1468      .Case("rv635",    GK_R600)
1469      .Case("rs780",    GK_R600)
1470      .Case("rs880",    GK_R600)
1471      .Case("rv670",    GK_R600_DOUBLE_OPS)
1472      .Case("rv710",    GK_R700)
1473      .Case("rv730",    GK_R700)
1474      .Case("rv740",    GK_R700_DOUBLE_OPS)
1475      .Case("rv770",    GK_R700_DOUBLE_OPS)
1476      .Case("palm",     GK_EVERGREEN)
1477      .Case("cedar",    GK_EVERGREEN)
1478      .Case("sumo",     GK_EVERGREEN)
1479      .Case("sumo2",    GK_EVERGREEN)
1480      .Case("redwood",  GK_EVERGREEN)
1481      .Case("juniper",  GK_EVERGREEN)
1482      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1483      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1484      .Case("barts",    GK_NORTHERN_ISLANDS)
1485      .Case("turks",    GK_NORTHERN_ISLANDS)
1486      .Case("caicos",   GK_NORTHERN_ISLANDS)
1487      .Case("cayman",   GK_CAYMAN)
1488      .Case("aruba",    GK_CAYMAN)
1489      .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1490      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1491      .Case("verde",    GK_SOUTHERN_ISLANDS)
1492      .Case("oland",    GK_SOUTHERN_ISLANDS)
1493      .Default(GK_NONE);
1494
1495    if (GPU == GK_NONE) {
1496      return false;
1497    }
1498
1499    // Set the correct data layout
1500    switch (GPU) {
1501    case GK_NONE:
1502    case GK_R600:
1503    case GK_R700:
1504    case GK_EVERGREEN:
1505    case GK_NORTHERN_ISLANDS:
1506      DescriptionString = DescriptionStringR600;
1507      break;
1508    case GK_R600_DOUBLE_OPS:
1509    case GK_R700_DOUBLE_OPS:
1510    case GK_EVERGREEN_DOUBLE_OPS:
1511    case GK_CAYMAN:
1512      DescriptionString = DescriptionStringR600DoubleOps;
1513      break;
1514    case GK_SOUTHERN_ISLANDS:
1515      DescriptionString = DescriptionStringSI;
1516      break;
1517    }
1518
1519    return true;
1520  }
1521};
1522
1523} // end anonymous namespace
1524
1525namespace {
1526// MBlaze abstract base class
1527class MBlazeTargetInfo : public TargetInfo {
1528  static const char * const GCCRegNames[];
1529  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1530
1531public:
1532  MBlazeTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1533    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1534  }
1535
1536  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1537                                 unsigned &NumRecords) const {
1538    // FIXME: Implement.
1539    Records = 0;
1540    NumRecords = 0;
1541  }
1542
1543  virtual void getTargetDefines(const LangOptions &Opts,
1544                                MacroBuilder &Builder) const;
1545
1546  virtual bool hasFeature(StringRef Feature) const {
1547    return Feature == "mblaze";
1548  }
1549
1550  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1551    return TargetInfo::CharPtrBuiltinVaList;
1552  }
1553  virtual const char *getTargetPrefix() const {
1554    return "mblaze";
1555  }
1556  virtual void getGCCRegNames(const char * const *&Names,
1557                              unsigned &NumNames) const;
1558  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1559                                unsigned &NumAliases) const;
1560  virtual bool validateAsmConstraint(const char *&Name,
1561                                     TargetInfo::ConstraintInfo &Info) const {
1562    switch (*Name) {
1563    default: return false;
1564    case 'O': // Zero
1565      return true;
1566    case 'b': // Base register
1567    case 'f': // Floating point register
1568      Info.setAllowsRegister();
1569      return true;
1570    }
1571  }
1572  virtual const char *getClobbers() const {
1573    return "";
1574  }
1575};
1576
1577/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1578/// #defines that are not tied to a specific subtarget.
1579void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1580                                     MacroBuilder &Builder) const {
1581  // Target identification.
1582  Builder.defineMacro("__microblaze__");
1583  Builder.defineMacro("_ARCH_MICROBLAZE");
1584  Builder.defineMacro("__MICROBLAZE__");
1585
1586  // Target properties.
1587  Builder.defineMacro("_BIG_ENDIAN");
1588  Builder.defineMacro("__BIG_ENDIAN__");
1589
1590  // Subtarget options.
1591  Builder.defineMacro("__REGISTER_PREFIX__", "");
1592}
1593
1594
1595const char * const MBlazeTargetInfo::GCCRegNames[] = {
1596  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1597  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1598  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1599  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1600  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1601  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1602  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1603  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1604  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1605  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1606};
1607
1608void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1609                                   unsigned &NumNames) const {
1610  Names = GCCRegNames;
1611  NumNames = llvm::array_lengthof(GCCRegNames);
1612}
1613
1614const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1615  { {"f0"},  "r0" },
1616  { {"f1"},  "r1" },
1617  { {"f2"},  "r2" },
1618  { {"f3"},  "r3" },
1619  { {"f4"},  "r4" },
1620  { {"f5"},  "r5" },
1621  { {"f6"},  "r6" },
1622  { {"f7"},  "r7" },
1623  { {"f8"},  "r8" },
1624  { {"f9"},  "r9" },
1625  { {"f10"}, "r10" },
1626  { {"f11"}, "r11" },
1627  { {"f12"}, "r12" },
1628  { {"f13"}, "r13" },
1629  { {"f14"}, "r14" },
1630  { {"f15"}, "r15" },
1631  { {"f16"}, "r16" },
1632  { {"f17"}, "r17" },
1633  { {"f18"}, "r18" },
1634  { {"f19"}, "r19" },
1635  { {"f20"}, "r20" },
1636  { {"f21"}, "r21" },
1637  { {"f22"}, "r22" },
1638  { {"f23"}, "r23" },
1639  { {"f24"}, "r24" },
1640  { {"f25"}, "r25" },
1641  { {"f26"}, "r26" },
1642  { {"f27"}, "r27" },
1643  { {"f28"}, "r28" },
1644  { {"f29"}, "r29" },
1645  { {"f30"}, "r30" },
1646  { {"f31"}, "r31" },
1647};
1648
1649void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1650                                     unsigned &NumAliases) const {
1651  Aliases = GCCRegAliases;
1652  NumAliases = llvm::array_lengthof(GCCRegAliases);
1653}
1654} // end anonymous namespace.
1655
1656namespace {
1657// Namespace for x86 abstract base class
1658const Builtin::Info BuiltinInfo[] = {
1659#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1660#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1661                                              ALL_LANGUAGES },
1662#include "clang/Basic/BuiltinsX86.def"
1663};
1664
1665static const char* const GCCRegNames[] = {
1666  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1667  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1668  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1669  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1670  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1671  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1672  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1673  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1674  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1675};
1676
1677const TargetInfo::AddlRegName AddlRegNames[] = {
1678  { { "al", "ah", "eax", "rax" }, 0 },
1679  { { "bl", "bh", "ebx", "rbx" }, 3 },
1680  { { "cl", "ch", "ecx", "rcx" }, 2 },
1681  { { "dl", "dh", "edx", "rdx" }, 1 },
1682  { { "esi", "rsi" }, 4 },
1683  { { "edi", "rdi" }, 5 },
1684  { { "esp", "rsp" }, 7 },
1685  { { "ebp", "rbp" }, 6 },
1686};
1687
1688// X86 target abstract base class; x86-32 and x86-64 are very close, so
1689// most of the implementation can be shared.
1690class X86TargetInfo : public TargetInfo {
1691  enum X86SSEEnum {
1692    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1693  } SSELevel;
1694  enum MMX3DNowEnum {
1695    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1696  } MMX3DNowLevel;
1697
1698  bool HasAES;
1699  bool HasPCLMUL;
1700  bool HasLZCNT;
1701  bool HasRDRND;
1702  bool HasBMI;
1703  bool HasBMI2;
1704  bool HasPOPCNT;
1705  bool HasRTM;
1706  bool HasPRFCHW;
1707  bool HasRDSEED;
1708  bool HasSSE4a;
1709  bool HasFMA4;
1710  bool HasFMA;
1711  bool HasXOP;
1712  bool HasF16C;
1713
1714  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1715  ///
1716  /// Each enumeration represents a particular CPU supported by Clang. These
1717  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1718  enum CPUKind {
1719    CK_Generic,
1720
1721    /// \name i386
1722    /// i386-generation processors.
1723    //@{
1724    CK_i386,
1725    //@}
1726
1727    /// \name i486
1728    /// i486-generation processors.
1729    //@{
1730    CK_i486,
1731    CK_WinChipC6,
1732    CK_WinChip2,
1733    CK_C3,
1734    //@}
1735
1736    /// \name i586
1737    /// i586-generation processors, P5 microarchitecture based.
1738    //@{
1739    CK_i586,
1740    CK_Pentium,
1741    CK_PentiumMMX,
1742    //@}
1743
1744    /// \name i686
1745    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1746    //@{
1747    CK_i686,
1748    CK_PentiumPro,
1749    CK_Pentium2,
1750    CK_Pentium3,
1751    CK_Pentium3M,
1752    CK_PentiumM,
1753    CK_C3_2,
1754
1755    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1756    /// Clang however has some logic to suport this.
1757    // FIXME: Warn, deprecate, and potentially remove this.
1758    CK_Yonah,
1759    //@}
1760
1761    /// \name Netburst
1762    /// Netburst microarchitecture based processors.
1763    //@{
1764    CK_Pentium4,
1765    CK_Pentium4M,
1766    CK_Prescott,
1767    CK_Nocona,
1768    //@}
1769
1770    /// \name Core
1771    /// Core microarchitecture based processors.
1772    //@{
1773    CK_Core2,
1774
1775    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1776    /// codename which GCC no longer accepts as an option to -march, but Clang
1777    /// has some logic for recognizing it.
1778    // FIXME: Warn, deprecate, and potentially remove this.
1779    CK_Penryn,
1780    //@}
1781
1782    /// \name Atom
1783    /// Atom processors
1784    //@{
1785    CK_Atom,
1786    //@}
1787
1788    /// \name Nehalem
1789    /// Nehalem microarchitecture based processors.
1790    //@{
1791    CK_Corei7,
1792    CK_Corei7AVX,
1793    CK_CoreAVXi,
1794    CK_CoreAVX2,
1795    //@}
1796
1797    /// \name K6
1798    /// K6 architecture processors.
1799    //@{
1800    CK_K6,
1801    CK_K6_2,
1802    CK_K6_3,
1803    //@}
1804
1805    /// \name K7
1806    /// K7 architecture processors.
1807    //@{
1808    CK_Athlon,
1809    CK_AthlonThunderbird,
1810    CK_Athlon4,
1811    CK_AthlonXP,
1812    CK_AthlonMP,
1813    //@}
1814
1815    /// \name K8
1816    /// K8 architecture processors.
1817    //@{
1818    CK_Athlon64,
1819    CK_Athlon64SSE3,
1820    CK_AthlonFX,
1821    CK_K8,
1822    CK_K8SSE3,
1823    CK_Opteron,
1824    CK_OpteronSSE3,
1825    CK_AMDFAM10,
1826    //@}
1827
1828    /// \name Bobcat
1829    /// Bobcat architecture processors.
1830    //@{
1831    CK_BTVER1,
1832    CK_BTVER2,
1833    //@}
1834
1835    /// \name Bulldozer
1836    /// Bulldozer architecture processors.
1837    //@{
1838    CK_BDVER1,
1839    CK_BDVER2,
1840    //@}
1841
1842    /// This specification is deprecated and will be removed in the future.
1843    /// Users should prefer \see CK_K8.
1844    // FIXME: Warn on this when the CPU is set to it.
1845    CK_x86_64,
1846    //@}
1847
1848    /// \name Geode
1849    /// Geode processors.
1850    //@{
1851    CK_Geode
1852    //@}
1853  } CPU;
1854
1855public:
1856  X86TargetInfo(const llvm::Triple &Triple)
1857      : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1858        HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1859        HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1860        HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1861        HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1862    BigEndian = false;
1863    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1864  }
1865  virtual unsigned getFloatEvalMethod() const {
1866    // X87 evaluates with 80 bits "long double" precision.
1867    return SSELevel == NoSSE ? 2 : 0;
1868  }
1869  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1870                                 unsigned &NumRecords) const {
1871    Records = BuiltinInfo;
1872    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1873  }
1874  virtual void getGCCRegNames(const char * const *&Names,
1875                              unsigned &NumNames) const {
1876    Names = GCCRegNames;
1877    NumNames = llvm::array_lengthof(GCCRegNames);
1878  }
1879  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1880                                unsigned &NumAliases) const {
1881    Aliases = 0;
1882    NumAliases = 0;
1883  }
1884  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1885                                  unsigned &NumNames) const {
1886    Names = AddlRegNames;
1887    NumNames = llvm::array_lengthof(AddlRegNames);
1888  }
1889  virtual bool validateAsmConstraint(const char *&Name,
1890                                     TargetInfo::ConstraintInfo &info) const;
1891  virtual std::string convertConstraint(const char *&Constraint) const;
1892  virtual const char *getClobbers() const {
1893    return "~{dirflag},~{fpsr},~{flags}";
1894  }
1895  virtual void getTargetDefines(const LangOptions &Opts,
1896                                MacroBuilder &Builder) const;
1897  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1898                                 StringRef Name,
1899                                 bool Enabled) const;
1900  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1901  virtual bool hasFeature(StringRef Feature) const;
1902  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1903  virtual const char* getABI() const {
1904    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1905      return "avx";
1906    else if (getTriple().getArch() == llvm::Triple::x86 &&
1907             MMX3DNowLevel == NoMMX3DNow)
1908      return "no-mmx";
1909    return "";
1910  }
1911  virtual bool setCPU(const std::string &Name) {
1912    CPU = llvm::StringSwitch<CPUKind>(Name)
1913      .Case("i386", CK_i386)
1914      .Case("i486", CK_i486)
1915      .Case("winchip-c6", CK_WinChipC6)
1916      .Case("winchip2", CK_WinChip2)
1917      .Case("c3", CK_C3)
1918      .Case("i586", CK_i586)
1919      .Case("pentium", CK_Pentium)
1920      .Case("pentium-mmx", CK_PentiumMMX)
1921      .Case("i686", CK_i686)
1922      .Case("pentiumpro", CK_PentiumPro)
1923      .Case("pentium2", CK_Pentium2)
1924      .Case("pentium3", CK_Pentium3)
1925      .Case("pentium3m", CK_Pentium3M)
1926      .Case("pentium-m", CK_PentiumM)
1927      .Case("c3-2", CK_C3_2)
1928      .Case("yonah", CK_Yonah)
1929      .Case("pentium4", CK_Pentium4)
1930      .Case("pentium4m", CK_Pentium4M)
1931      .Case("prescott", CK_Prescott)
1932      .Case("nocona", CK_Nocona)
1933      .Case("core2", CK_Core2)
1934      .Case("penryn", CK_Penryn)
1935      .Case("atom", CK_Atom)
1936      .Case("corei7", CK_Corei7)
1937      .Case("corei7-avx", CK_Corei7AVX)
1938      .Case("core-avx-i", CK_CoreAVXi)
1939      .Case("core-avx2", CK_CoreAVX2)
1940      .Case("k6", CK_K6)
1941      .Case("k6-2", CK_K6_2)
1942      .Case("k6-3", CK_K6_3)
1943      .Case("athlon", CK_Athlon)
1944      .Case("athlon-tbird", CK_AthlonThunderbird)
1945      .Case("athlon-4", CK_Athlon4)
1946      .Case("athlon-xp", CK_AthlonXP)
1947      .Case("athlon-mp", CK_AthlonMP)
1948      .Case("athlon64", CK_Athlon64)
1949      .Case("athlon64-sse3", CK_Athlon64SSE3)
1950      .Case("athlon-fx", CK_AthlonFX)
1951      .Case("k8", CK_K8)
1952      .Case("k8-sse3", CK_K8SSE3)
1953      .Case("opteron", CK_Opteron)
1954      .Case("opteron-sse3", CK_OpteronSSE3)
1955      .Case("amdfam10", CK_AMDFAM10)
1956      .Case("btver1", CK_BTVER1)
1957      .Case("btver2", CK_BTVER2)
1958      .Case("bdver1", CK_BDVER1)
1959      .Case("bdver2", CK_BDVER2)
1960      .Case("x86-64", CK_x86_64)
1961      .Case("geode", CK_Geode)
1962      .Default(CK_Generic);
1963
1964    // Perform any per-CPU checks necessary to determine if this CPU is
1965    // acceptable.
1966    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1967    // invalid without explaining *why*.
1968    switch (CPU) {
1969    case CK_Generic:
1970      // No processor selected!
1971      return false;
1972
1973    case CK_i386:
1974    case CK_i486:
1975    case CK_WinChipC6:
1976    case CK_WinChip2:
1977    case CK_C3:
1978    case CK_i586:
1979    case CK_Pentium:
1980    case CK_PentiumMMX:
1981    case CK_i686:
1982    case CK_PentiumPro:
1983    case CK_Pentium2:
1984    case CK_Pentium3:
1985    case CK_Pentium3M:
1986    case CK_PentiumM:
1987    case CK_Yonah:
1988    case CK_C3_2:
1989    case CK_Pentium4:
1990    case CK_Pentium4M:
1991    case CK_Prescott:
1992    case CK_K6:
1993    case CK_K6_2:
1994    case CK_K6_3:
1995    case CK_Athlon:
1996    case CK_AthlonThunderbird:
1997    case CK_Athlon4:
1998    case CK_AthlonXP:
1999    case CK_AthlonMP:
2000    case CK_Geode:
2001      // Only accept certain architectures when compiling in 32-bit mode.
2002      if (getTriple().getArch() != llvm::Triple::x86)
2003        return false;
2004
2005      // Fallthrough
2006    case CK_Nocona:
2007    case CK_Core2:
2008    case CK_Penryn:
2009    case CK_Atom:
2010    case CK_Corei7:
2011    case CK_Corei7AVX:
2012    case CK_CoreAVXi:
2013    case CK_CoreAVX2:
2014    case CK_Athlon64:
2015    case CK_Athlon64SSE3:
2016    case CK_AthlonFX:
2017    case CK_K8:
2018    case CK_K8SSE3:
2019    case CK_Opteron:
2020    case CK_OpteronSSE3:
2021    case CK_AMDFAM10:
2022    case CK_BTVER1:
2023    case CK_BTVER2:
2024    case CK_BDVER1:
2025    case CK_BDVER2:
2026    case CK_x86_64:
2027      return true;
2028    }
2029    llvm_unreachable("Unhandled CPU kind");
2030  }
2031
2032  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2033    // We accept all non-ARM calling conventions
2034    return (CC == CC_X86ThisCall ||
2035            CC == CC_X86FastCall ||
2036            CC == CC_X86StdCall ||
2037            CC == CC_C ||
2038            CC == CC_X86Pascal ||
2039            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2040  }
2041
2042  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2043    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2044  }
2045};
2046
2047void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2048  // FIXME: This should not be here.
2049  Features["3dnow"] = false;
2050  Features["3dnowa"] = false;
2051  Features["mmx"] = false;
2052  Features["sse"] = false;
2053  Features["sse2"] = false;
2054  Features["sse3"] = false;
2055  Features["ssse3"] = false;
2056  Features["sse41"] = false;
2057  Features["sse42"] = false;
2058  Features["sse4a"] = false;
2059  Features["aes"] = false;
2060  Features["pclmul"] = false;
2061  Features["avx"] = false;
2062  Features["avx2"] = false;
2063  Features["lzcnt"] = false;
2064  Features["rdrand"] = false;
2065  Features["bmi"] = false;
2066  Features["bmi2"] = false;
2067  Features["popcnt"] = false;
2068  Features["rtm"] = false;
2069  Features["prfchw"] = false;
2070  Features["rdseed"] = false;
2071  Features["fma4"] = false;
2072  Features["fma"] = false;
2073  Features["xop"] = false;
2074  Features["f16c"] = false;
2075
2076  // FIXME: This *really* should not be here.
2077
2078  // X86_64 always has SSE2.
2079  if (getTriple().getArch() == llvm::Triple::x86_64)
2080    setFeatureEnabled(Features, "sse2", true);
2081
2082  switch (CPU) {
2083  case CK_Generic:
2084  case CK_i386:
2085  case CK_i486:
2086  case CK_i586:
2087  case CK_Pentium:
2088  case CK_i686:
2089  case CK_PentiumPro:
2090    break;
2091  case CK_PentiumMMX:
2092  case CK_Pentium2:
2093    setFeatureEnabled(Features, "mmx", true);
2094    break;
2095  case CK_Pentium3:
2096  case CK_Pentium3M:
2097    setFeatureEnabled(Features, "sse", true);
2098    break;
2099  case CK_PentiumM:
2100  case CK_Pentium4:
2101  case CK_Pentium4M:
2102  case CK_x86_64:
2103    setFeatureEnabled(Features, "sse2", true);
2104    break;
2105  case CK_Yonah:
2106  case CK_Prescott:
2107  case CK_Nocona:
2108    setFeatureEnabled(Features, "sse3", true);
2109    break;
2110  case CK_Core2:
2111    setFeatureEnabled(Features, "ssse3", true);
2112    break;
2113  case CK_Penryn:
2114    setFeatureEnabled(Features, "sse4.1", true);
2115    break;
2116  case CK_Atom:
2117    setFeatureEnabled(Features, "ssse3", true);
2118    break;
2119  case CK_Corei7:
2120    setFeatureEnabled(Features, "sse4", true);
2121    break;
2122  case CK_Corei7AVX:
2123    setFeatureEnabled(Features, "avx", true);
2124    setFeatureEnabled(Features, "aes", true);
2125    setFeatureEnabled(Features, "pclmul", true);
2126    break;
2127  case CK_CoreAVXi:
2128    setFeatureEnabled(Features, "avx", true);
2129    setFeatureEnabled(Features, "aes", true);
2130    setFeatureEnabled(Features, "pclmul", true);
2131    setFeatureEnabled(Features, "rdrnd", true);
2132    setFeatureEnabled(Features, "f16c", true);
2133    break;
2134  case CK_CoreAVX2:
2135    setFeatureEnabled(Features, "avx2", true);
2136    setFeatureEnabled(Features, "aes", true);
2137    setFeatureEnabled(Features, "pclmul", true);
2138    setFeatureEnabled(Features, "lzcnt", true);
2139    setFeatureEnabled(Features, "rdrnd", true);
2140    setFeatureEnabled(Features, "f16c", true);
2141    setFeatureEnabled(Features, "bmi", true);
2142    setFeatureEnabled(Features, "bmi2", true);
2143    setFeatureEnabled(Features, "rtm", true);
2144    setFeatureEnabled(Features, "fma", true);
2145    break;
2146  case CK_K6:
2147  case CK_WinChipC6:
2148    setFeatureEnabled(Features, "mmx", true);
2149    break;
2150  case CK_K6_2:
2151  case CK_K6_3:
2152  case CK_WinChip2:
2153  case CK_C3:
2154    setFeatureEnabled(Features, "3dnow", true);
2155    break;
2156  case CK_Athlon:
2157  case CK_AthlonThunderbird:
2158  case CK_Geode:
2159    setFeatureEnabled(Features, "3dnowa", true);
2160    break;
2161  case CK_Athlon4:
2162  case CK_AthlonXP:
2163  case CK_AthlonMP:
2164    setFeatureEnabled(Features, "sse", true);
2165    setFeatureEnabled(Features, "3dnowa", true);
2166    break;
2167  case CK_K8:
2168  case CK_Opteron:
2169  case CK_Athlon64:
2170  case CK_AthlonFX:
2171    setFeatureEnabled(Features, "sse2", true);
2172    setFeatureEnabled(Features, "3dnowa", true);
2173    break;
2174  case CK_K8SSE3:
2175  case CK_OpteronSSE3:
2176  case CK_Athlon64SSE3:
2177    setFeatureEnabled(Features, "sse3", true);
2178    setFeatureEnabled(Features, "3dnowa", true);
2179    break;
2180  case CK_AMDFAM10:
2181    setFeatureEnabled(Features, "sse3", true);
2182    setFeatureEnabled(Features, "sse4a", true);
2183    setFeatureEnabled(Features, "3dnowa", true);
2184    setFeatureEnabled(Features, "lzcnt", true);
2185    setFeatureEnabled(Features, "popcnt", true);
2186    break;
2187  case CK_BTVER1:
2188    setFeatureEnabled(Features, "ssse3", true);
2189    setFeatureEnabled(Features, "sse4a", true);
2190    setFeatureEnabled(Features, "lzcnt", true);
2191    setFeatureEnabled(Features, "popcnt", true);
2192    break;
2193  case CK_BTVER2:
2194    setFeatureEnabled(Features, "avx", true);
2195    setFeatureEnabled(Features, "sse4a", true);
2196    setFeatureEnabled(Features, "lzcnt", true);
2197    setFeatureEnabled(Features, "aes", true);
2198    setFeatureEnabled(Features, "pclmul", true);
2199    setFeatureEnabled(Features, "bmi", true);
2200    setFeatureEnabled(Features, "f16c", true);
2201    break;
2202  case CK_BDVER1:
2203    setFeatureEnabled(Features, "xop", true);
2204    setFeatureEnabled(Features, "lzcnt", true);
2205    setFeatureEnabled(Features, "aes", true);
2206    setFeatureEnabled(Features, "pclmul", true);
2207    break;
2208  case CK_BDVER2:
2209    setFeatureEnabled(Features, "xop", true);
2210    setFeatureEnabled(Features, "lzcnt", true);
2211    setFeatureEnabled(Features, "aes", true);
2212    setFeatureEnabled(Features, "pclmul", true);
2213    setFeatureEnabled(Features, "bmi", true);
2214    setFeatureEnabled(Features, "fma", true);
2215    setFeatureEnabled(Features, "f16c", true);
2216    break;
2217  case CK_C3_2:
2218    setFeatureEnabled(Features, "sse", true);
2219    break;
2220  }
2221}
2222
2223bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2224                                      StringRef Name,
2225                                      bool Enabled) const {
2226  // FIXME: This *really* should not be here.  We need some way of translating
2227  // options into llvm subtarget features.
2228  if (!Features.count(Name) &&
2229      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2230       Name != "rdrnd"))
2231    return false;
2232
2233  // FIXME: this should probably use a switch with fall through.
2234
2235  if (Enabled) {
2236    if (Name == "mmx")
2237      Features["mmx"] = true;
2238    else if (Name == "sse")
2239      Features["mmx"] = Features["sse"] = true;
2240    else if (Name == "sse2")
2241      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2242    else if (Name == "sse3")
2243      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2244        true;
2245    else if (Name == "ssse3")
2246      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2247        Features["ssse3"] = true;
2248    else if (Name == "sse4" || Name == "sse4.2")
2249      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2250        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2251        Features["popcnt"] = true;
2252    else if (Name == "sse4.1")
2253      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2254        Features["ssse3"] = Features["sse41"] = true;
2255    else if (Name == "3dnow")
2256      Features["mmx"] = Features["3dnow"] = true;
2257    else if (Name == "3dnowa")
2258      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2259    else if (Name == "aes")
2260      Features["sse"] = Features["sse2"] = Features["aes"] = true;
2261    else if (Name == "pclmul")
2262      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2263    else if (Name == "avx")
2264      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2265        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2266        Features["popcnt"] = Features["avx"] = true;
2267    else if (Name == "avx2")
2268      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2269        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2270        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2271    else if (Name == "fma")
2272      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2273        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2274        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2275    else if (Name == "fma4")
2276      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2277        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2278        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2279        Features["fma4"] = true;
2280    else if (Name == "xop")
2281      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2282        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2283        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2284        Features["fma4"] = Features["xop"] = true;
2285    else if (Name == "sse4a")
2286      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2287        Features["sse4a"] = true;
2288    else if (Name == "lzcnt")
2289      Features["lzcnt"] = true;
2290    else if (Name == "rdrnd")
2291      Features["rdrand"] = true;
2292    else if (Name == "bmi")
2293      Features["bmi"] = true;
2294    else if (Name == "bmi2")
2295      Features["bmi2"] = true;
2296    else if (Name == "popcnt")
2297      Features["popcnt"] = true;
2298    else if (Name == "f16c")
2299      Features["f16c"] = true;
2300    else if (Name == "rtm")
2301      Features["rtm"] = true;
2302    else if (Name == "prfchw")
2303      Features["prfchw"] = true;
2304    else if (Name == "rdseed")
2305      Features["rdseed"] = true;
2306  } else {
2307    if (Name == "mmx")
2308      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2309    else if (Name == "sse")
2310      Features["sse"] = Features["sse2"] = Features["sse3"] =
2311        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2312        Features["sse4a"] = Features["avx"] = Features["avx2"] =
2313        Features["fma"] = Features["fma4"] = Features["aes"] =
2314        Features["pclmul"] = Features["xop"] = false;
2315    else if (Name == "sse2")
2316      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2317        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2318        Features["avx"] = Features["avx2"] = Features["fma"] =
2319        Features["fma4"] = Features["aes"] = Features["pclmul"] =
2320        Features["xop"] = false;
2321    else if (Name == "sse3")
2322      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2323        Features["sse42"] = Features["sse4a"] = Features["avx"] =
2324        Features["avx2"] = Features["fma"] = Features["fma4"] =
2325        Features["xop"] = false;
2326    else if (Name == "ssse3")
2327      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2328        Features["avx"] = Features["avx2"] = Features["fma"] = false;
2329    else if (Name == "sse4" || Name == "sse4.1")
2330      Features["sse41"] = Features["sse42"] = Features["avx"] =
2331        Features["avx2"] = Features["fma"] = false;
2332    else if (Name == "sse4.2")
2333      Features["sse42"] = Features["avx"] = Features["avx2"] =
2334        Features["fma"] = false;
2335    else if (Name == "3dnow")
2336      Features["3dnow"] = Features["3dnowa"] = false;
2337    else if (Name == "3dnowa")
2338      Features["3dnowa"] = false;
2339    else if (Name == "aes")
2340      Features["aes"] = false;
2341    else if (Name == "pclmul")
2342      Features["pclmul"] = false;
2343    else if (Name == "avx")
2344      Features["avx"] = Features["avx2"] = Features["fma"] =
2345        Features["fma4"] = Features["xop"] = false;
2346    else if (Name == "avx2")
2347      Features["avx2"] = false;
2348    else if (Name == "fma")
2349      Features["fma"] = false;
2350    else if (Name == "sse4a")
2351      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2352    else if (Name == "lzcnt")
2353      Features["lzcnt"] = false;
2354    else if (Name == "rdrnd")
2355      Features["rdrand"] = false;
2356    else if (Name == "bmi")
2357      Features["bmi"] = false;
2358    else if (Name == "bmi2")
2359      Features["bmi2"] = false;
2360    else if (Name == "popcnt")
2361      Features["popcnt"] = false;
2362    else if (Name == "fma4")
2363      Features["fma4"] = Features["xop"] = false;
2364    else if (Name == "xop")
2365      Features["xop"] = false;
2366    else if (Name == "f16c")
2367      Features["f16c"] = false;
2368    else if (Name == "rtm")
2369      Features["rtm"] = false;
2370    else if (Name == "prfchw")
2371      Features["prfchw"] = false;
2372    else if (Name == "rdseed")
2373      Features["rdseed"] = false;
2374  }
2375
2376  return true;
2377}
2378
2379/// HandleTargetOptions - Perform initialization based on the user
2380/// configured set of features.
2381void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2382  // Remember the maximum enabled sselevel.
2383  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2384    // Ignore disabled features.
2385    if (Features[i][0] == '-')
2386      continue;
2387
2388    StringRef Feature = StringRef(Features[i]).substr(1);
2389
2390    if (Feature == "aes") {
2391      HasAES = true;
2392      continue;
2393    }
2394
2395    if (Feature == "pclmul") {
2396      HasPCLMUL = true;
2397      continue;
2398    }
2399
2400    if (Feature == "lzcnt") {
2401      HasLZCNT = true;
2402      continue;
2403    }
2404
2405    if (Feature == "rdrand") {
2406      HasRDRND = true;
2407      continue;
2408    }
2409
2410    if (Feature == "bmi") {
2411      HasBMI = true;
2412      continue;
2413    }
2414
2415    if (Feature == "bmi2") {
2416      HasBMI2 = true;
2417      continue;
2418    }
2419
2420    if (Feature == "popcnt") {
2421      HasPOPCNT = true;
2422      continue;
2423    }
2424
2425    if (Feature == "rtm") {
2426      HasRTM = true;
2427      continue;
2428    }
2429
2430    if (Feature == "prfchw") {
2431      HasPRFCHW = true;
2432      continue;
2433    }
2434
2435    if (Feature == "rdseed") {
2436      HasRDSEED = true;
2437      continue;
2438    }
2439
2440    if (Feature == "sse4a") {
2441      HasSSE4a = true;
2442      continue;
2443    }
2444
2445    if (Feature == "fma4") {
2446      HasFMA4 = true;
2447      continue;
2448    }
2449
2450    if (Feature == "fma") {
2451      HasFMA = true;
2452      continue;
2453    }
2454
2455    if (Feature == "xop") {
2456      HasXOP = true;
2457      continue;
2458    }
2459
2460    if (Feature == "f16c") {
2461      HasF16C = true;
2462      continue;
2463    }
2464
2465    assert(Features[i][0] == '+' && "Invalid target feature!");
2466    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2467      .Case("avx2", AVX2)
2468      .Case("avx", AVX)
2469      .Case("sse42", SSE42)
2470      .Case("sse41", SSE41)
2471      .Case("ssse3", SSSE3)
2472      .Case("sse3", SSE3)
2473      .Case("sse2", SSE2)
2474      .Case("sse", SSE1)
2475      .Default(NoSSE);
2476    SSELevel = std::max(SSELevel, Level);
2477
2478    MMX3DNowEnum ThreeDNowLevel =
2479      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2480        .Case("3dnowa", AMD3DNowAthlon)
2481        .Case("3dnow", AMD3DNow)
2482        .Case("mmx", MMX)
2483        .Default(NoMMX3DNow);
2484
2485    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2486  }
2487
2488  // Don't tell the backend if we're turning off mmx; it will end up disabling
2489  // SSE, which we don't want.
2490  std::vector<std::string>::iterator it;
2491  it = std::find(Features.begin(), Features.end(), "-mmx");
2492  if (it != Features.end())
2493    Features.erase(it);
2494}
2495
2496/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2497/// definitions for this particular subtarget.
2498void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2499                                     MacroBuilder &Builder) const {
2500  // Target identification.
2501  if (getTriple().getArch() == llvm::Triple::x86_64) {
2502    Builder.defineMacro("__amd64__");
2503    Builder.defineMacro("__amd64");
2504    Builder.defineMacro("__x86_64");
2505    Builder.defineMacro("__x86_64__");
2506  } else {
2507    DefineStd(Builder, "i386", Opts);
2508  }
2509
2510  // Subtarget options.
2511  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2512  // truly should be based on -mtune options.
2513  switch (CPU) {
2514  case CK_Generic:
2515    break;
2516  case CK_i386:
2517    // The rest are coming from the i386 define above.
2518    Builder.defineMacro("__tune_i386__");
2519    break;
2520  case CK_i486:
2521  case CK_WinChipC6:
2522  case CK_WinChip2:
2523  case CK_C3:
2524    defineCPUMacros(Builder, "i486");
2525    break;
2526  case CK_PentiumMMX:
2527    Builder.defineMacro("__pentium_mmx__");
2528    Builder.defineMacro("__tune_pentium_mmx__");
2529    // Fallthrough
2530  case CK_i586:
2531  case CK_Pentium:
2532    defineCPUMacros(Builder, "i586");
2533    defineCPUMacros(Builder, "pentium");
2534    break;
2535  case CK_Pentium3:
2536  case CK_Pentium3M:
2537  case CK_PentiumM:
2538    Builder.defineMacro("__tune_pentium3__");
2539    // Fallthrough
2540  case CK_Pentium2:
2541  case CK_C3_2:
2542    Builder.defineMacro("__tune_pentium2__");
2543    // Fallthrough
2544  case CK_PentiumPro:
2545    Builder.defineMacro("__tune_i686__");
2546    Builder.defineMacro("__tune_pentiumpro__");
2547    // Fallthrough
2548  case CK_i686:
2549    Builder.defineMacro("__i686");
2550    Builder.defineMacro("__i686__");
2551    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2552    Builder.defineMacro("__pentiumpro");
2553    Builder.defineMacro("__pentiumpro__");
2554    break;
2555  case CK_Pentium4:
2556  case CK_Pentium4M:
2557    defineCPUMacros(Builder, "pentium4");
2558    break;
2559  case CK_Yonah:
2560  case CK_Prescott:
2561  case CK_Nocona:
2562    defineCPUMacros(Builder, "nocona");
2563    break;
2564  case CK_Core2:
2565  case CK_Penryn:
2566    defineCPUMacros(Builder, "core2");
2567    break;
2568  case CK_Atom:
2569    defineCPUMacros(Builder, "atom");
2570    break;
2571  case CK_Corei7:
2572  case CK_Corei7AVX:
2573  case CK_CoreAVXi:
2574  case CK_CoreAVX2:
2575    defineCPUMacros(Builder, "corei7");
2576    break;
2577  case CK_K6_2:
2578    Builder.defineMacro("__k6_2__");
2579    Builder.defineMacro("__tune_k6_2__");
2580    // Fallthrough
2581  case CK_K6_3:
2582    if (CPU != CK_K6_2) {  // In case of fallthrough
2583      // FIXME: GCC may be enabling these in cases where some other k6
2584      // architecture is specified but -m3dnow is explicitly provided. The
2585      // exact semantics need to be determined and emulated here.
2586      Builder.defineMacro("__k6_3__");
2587      Builder.defineMacro("__tune_k6_3__");
2588    }
2589    // Fallthrough
2590  case CK_K6:
2591    defineCPUMacros(Builder, "k6");
2592    break;
2593  case CK_Athlon:
2594  case CK_AthlonThunderbird:
2595  case CK_Athlon4:
2596  case CK_AthlonXP:
2597  case CK_AthlonMP:
2598    defineCPUMacros(Builder, "athlon");
2599    if (SSELevel != NoSSE) {
2600      Builder.defineMacro("__athlon_sse__");
2601      Builder.defineMacro("__tune_athlon_sse__");
2602    }
2603    break;
2604  case CK_K8:
2605  case CK_K8SSE3:
2606  case CK_x86_64:
2607  case CK_Opteron:
2608  case CK_OpteronSSE3:
2609  case CK_Athlon64:
2610  case CK_Athlon64SSE3:
2611  case CK_AthlonFX:
2612    defineCPUMacros(Builder, "k8");
2613    break;
2614  case CK_AMDFAM10:
2615    defineCPUMacros(Builder, "amdfam10");
2616    break;
2617  case CK_BTVER1:
2618    defineCPUMacros(Builder, "btver1");
2619    break;
2620  case CK_BTVER2:
2621    defineCPUMacros(Builder, "btver2");
2622    break;
2623  case CK_BDVER1:
2624    defineCPUMacros(Builder, "bdver1");
2625    break;
2626  case CK_BDVER2:
2627    defineCPUMacros(Builder, "bdver2");
2628    break;
2629  case CK_Geode:
2630    defineCPUMacros(Builder, "geode");
2631    break;
2632  }
2633
2634  // Target properties.
2635  Builder.defineMacro("__LITTLE_ENDIAN__");
2636  Builder.defineMacro("__REGISTER_PREFIX__", "");
2637
2638  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2639  // functions in glibc header files that use FP Stack inline asm which the
2640  // backend can't deal with (PR879).
2641  Builder.defineMacro("__NO_MATH_INLINES");
2642
2643  if (HasAES)
2644    Builder.defineMacro("__AES__");
2645
2646  if (HasPCLMUL)
2647    Builder.defineMacro("__PCLMUL__");
2648
2649  if (HasLZCNT)
2650    Builder.defineMacro("__LZCNT__");
2651
2652  if (HasRDRND)
2653    Builder.defineMacro("__RDRND__");
2654
2655  if (HasBMI)
2656    Builder.defineMacro("__BMI__");
2657
2658  if (HasBMI2)
2659    Builder.defineMacro("__BMI2__");
2660
2661  if (HasPOPCNT)
2662    Builder.defineMacro("__POPCNT__");
2663
2664  if (HasRTM)
2665    Builder.defineMacro("__RTM__");
2666
2667  if (HasPRFCHW)
2668    Builder.defineMacro("__PRFCHW__");
2669
2670  if (HasRDSEED)
2671    Builder.defineMacro("__RDSEED__");
2672
2673  if (HasSSE4a)
2674    Builder.defineMacro("__SSE4A__");
2675
2676  if (HasFMA4)
2677    Builder.defineMacro("__FMA4__");
2678
2679  if (HasFMA)
2680    Builder.defineMacro("__FMA__");
2681
2682  if (HasXOP)
2683    Builder.defineMacro("__XOP__");
2684
2685  if (HasF16C)
2686    Builder.defineMacro("__F16C__");
2687
2688  // Each case falls through to the previous one here.
2689  switch (SSELevel) {
2690  case AVX2:
2691    Builder.defineMacro("__AVX2__");
2692  case AVX:
2693    Builder.defineMacro("__AVX__");
2694  case SSE42:
2695    Builder.defineMacro("__SSE4_2__");
2696  case SSE41:
2697    Builder.defineMacro("__SSE4_1__");
2698  case SSSE3:
2699    Builder.defineMacro("__SSSE3__");
2700  case SSE3:
2701    Builder.defineMacro("__SSE3__");
2702  case SSE2:
2703    Builder.defineMacro("__SSE2__");
2704    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2705  case SSE1:
2706    Builder.defineMacro("__SSE__");
2707    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2708  case NoSSE:
2709    break;
2710  }
2711
2712  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2713    switch (SSELevel) {
2714    case AVX2:
2715    case AVX:
2716    case SSE42:
2717    case SSE41:
2718    case SSSE3:
2719    case SSE3:
2720    case SSE2:
2721      Builder.defineMacro("_M_IX86_FP", Twine(2));
2722      break;
2723    case SSE1:
2724      Builder.defineMacro("_M_IX86_FP", Twine(1));
2725      break;
2726    default:
2727      Builder.defineMacro("_M_IX86_FP", Twine(0));
2728    }
2729  }
2730
2731  // Each case falls through to the previous one here.
2732  switch (MMX3DNowLevel) {
2733  case AMD3DNowAthlon:
2734    Builder.defineMacro("__3dNOW_A__");
2735  case AMD3DNow:
2736    Builder.defineMacro("__3dNOW__");
2737  case MMX:
2738    Builder.defineMacro("__MMX__");
2739  case NoMMX3DNow:
2740    break;
2741  }
2742
2743  if (CPU >= CK_i486) {
2744    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2745    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2746    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2747  }
2748  if (CPU >= CK_i586)
2749    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2750}
2751
2752bool X86TargetInfo::hasFeature(StringRef Feature) const {
2753  return llvm::StringSwitch<bool>(Feature)
2754      .Case("aes", HasAES)
2755      .Case("avx", SSELevel >= AVX)
2756      .Case("avx2", SSELevel >= AVX2)
2757      .Case("bmi", HasBMI)
2758      .Case("bmi2", HasBMI2)
2759      .Case("fma", HasFMA)
2760      .Case("fma4", HasFMA4)
2761      .Case("lzcnt", HasLZCNT)
2762      .Case("rdrnd", HasRDRND)
2763      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2764      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2765      .Case("mmx", MMX3DNowLevel >= MMX)
2766      .Case("pclmul", HasPCLMUL)
2767      .Case("popcnt", HasPOPCNT)
2768      .Case("rtm", HasRTM)
2769      .Case("prfchw", HasPRFCHW)
2770      .Case("rdseed", HasRDSEED)
2771      .Case("sse", SSELevel >= SSE1)
2772      .Case("sse2", SSELevel >= SSE2)
2773      .Case("sse3", SSELevel >= SSE3)
2774      .Case("ssse3", SSELevel >= SSSE3)
2775      .Case("sse41", SSELevel >= SSE41)
2776      .Case("sse42", SSELevel >= SSE42)
2777      .Case("sse4a", HasSSE4a)
2778      .Case("x86", true)
2779      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2780      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2781      .Case("xop", HasXOP)
2782      .Case("f16c", HasF16C)
2783      .Default(false);
2784}
2785
2786bool
2787X86TargetInfo::validateAsmConstraint(const char *&Name,
2788                                     TargetInfo::ConstraintInfo &Info) const {
2789  switch (*Name) {
2790  default: return false;
2791  case 'Y': // first letter of a pair:
2792    switch (*(Name+1)) {
2793    default: return false;
2794    case '0':  // First SSE register.
2795    case 't':  // Any SSE register, when SSE2 is enabled.
2796    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2797    case 'm':  // any MMX register, when inter-unit moves enabled.
2798      break;   // falls through to setAllowsRegister.
2799  }
2800  case 'a': // eax.
2801  case 'b': // ebx.
2802  case 'c': // ecx.
2803  case 'd': // edx.
2804  case 'S': // esi.
2805  case 'D': // edi.
2806  case 'A': // edx:eax.
2807  case 'f': // any x87 floating point stack register.
2808  case 't': // top of floating point stack.
2809  case 'u': // second from top of floating point stack.
2810  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2811  case 'y': // Any MMX register.
2812  case 'x': // Any SSE register.
2813  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2814  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2815  case 'l': // "Index" registers: any general register that can be used as an
2816            // index in a base+index memory access.
2817    Info.setAllowsRegister();
2818    return true;
2819  case 'C': // SSE floating point constant.
2820  case 'G': // x87 floating point constant.
2821  case 'e': // 32-bit signed integer constant for use with zero-extending
2822            // x86_64 instructions.
2823  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2824            // x86_64 instructions.
2825    return true;
2826  }
2827}
2828
2829
2830std::string
2831X86TargetInfo::convertConstraint(const char *&Constraint) const {
2832  switch (*Constraint) {
2833  case 'a': return std::string("{ax}");
2834  case 'b': return std::string("{bx}");
2835  case 'c': return std::string("{cx}");
2836  case 'd': return std::string("{dx}");
2837  case 'S': return std::string("{si}");
2838  case 'D': return std::string("{di}");
2839  case 'p': // address
2840    return std::string("im");
2841  case 't': // top of floating point stack.
2842    return std::string("{st}");
2843  case 'u': // second from top of floating point stack.
2844    return std::string("{st(1)}"); // second from top of floating point stack.
2845  default:
2846    return std::string(1, *Constraint);
2847  }
2848}
2849} // end anonymous namespace
2850
2851namespace {
2852// X86-32 generic target
2853class X86_32TargetInfo : public X86TargetInfo {
2854public:
2855  X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2856    DoubleAlign = LongLongAlign = 32;
2857    LongDoubleWidth = 96;
2858    LongDoubleAlign = 32;
2859    SuitableAlign = 128;
2860    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2861                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2862                        "a0:0:64-f80:32:32-n8:16:32-S128";
2863    SizeType = UnsignedInt;
2864    PtrDiffType = SignedInt;
2865    IntPtrType = SignedInt;
2866    RegParmMax = 3;
2867
2868    // Use fpret for all types.
2869    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2870                             (1 << TargetInfo::Double) |
2871                             (1 << TargetInfo::LongDouble));
2872
2873    // x86-32 has atomics up to 8 bytes
2874    // FIXME: Check that we actually have cmpxchg8b before setting
2875    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2876    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2877  }
2878  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2879    return TargetInfo::CharPtrBuiltinVaList;
2880  }
2881
2882  int getEHDataRegisterNumber(unsigned RegNo) const {
2883    if (RegNo == 0) return 0;
2884    if (RegNo == 1) return 2;
2885    return -1;
2886  }
2887  virtual bool validateInputSize(StringRef Constraint,
2888                                 unsigned Size) const {
2889    switch (Constraint[0]) {
2890    default: break;
2891    case 'a':
2892    case 'b':
2893    case 'c':
2894    case 'd':
2895      return Size <= 32;
2896    }
2897
2898    return true;
2899  }
2900};
2901} // end anonymous namespace
2902
2903namespace {
2904class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2905public:
2906  NetBSDI386TargetInfo(const llvm::Triple &Triple)
2907      : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
2908
2909  virtual unsigned getFloatEvalMethod() const {
2910    // NetBSD defaults to "double" rounding
2911    return 1;
2912  }
2913};
2914} // end anonymous namespace
2915
2916namespace {
2917class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2918public:
2919  OpenBSDI386TargetInfo(const llvm::Triple &Triple)
2920      : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
2921    SizeType = UnsignedLong;
2922    IntPtrType = SignedLong;
2923    PtrDiffType = SignedLong;
2924  }
2925};
2926} // end anonymous namespace
2927
2928namespace {
2929class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2930public:
2931  BitrigI386TargetInfo(const llvm::Triple &Triple)
2932      : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
2933    SizeType = UnsignedLong;
2934    IntPtrType = SignedLong;
2935    PtrDiffType = SignedLong;
2936  }
2937};
2938} // end anonymous namespace
2939
2940namespace {
2941class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2942public:
2943  DarwinI386TargetInfo(const llvm::Triple &Triple)
2944      : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
2945    LongDoubleWidth = 128;
2946    LongDoubleAlign = 128;
2947    SuitableAlign = 128;
2948    MaxVectorAlign = 256;
2949    SizeType = UnsignedLong;
2950    IntPtrType = SignedLong;
2951    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2952                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2953                        "a0:0:64-f80:128:128-n8:16:32-S128";
2954    HasAlignMac68kSupport = true;
2955  }
2956
2957};
2958} // end anonymous namespace
2959
2960namespace {
2961// x86-32 Windows target
2962class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2963public:
2964  WindowsX86_32TargetInfo(const llvm::Triple &Triple)
2965      : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
2966    TLSSupported = false;
2967    WCharType = UnsignedShort;
2968    DoubleAlign = LongLongAlign = 64;
2969    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2970                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2971                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2972  }
2973  virtual void getTargetDefines(const LangOptions &Opts,
2974                                MacroBuilder &Builder) const {
2975    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2976  }
2977};
2978} // end anonymous namespace
2979
2980namespace {
2981
2982// x86-32 Windows Visual Studio target
2983class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2984public:
2985  VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
2986      : WindowsX86_32TargetInfo(Triple) {
2987    LongDoubleWidth = LongDoubleAlign = 64;
2988    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2989  }
2990  virtual void getTargetDefines(const LangOptions &Opts,
2991                                MacroBuilder &Builder) const {
2992    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2993    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2994    // The value of the following reflects processor type.
2995    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2996    // We lost the original triple, so we use the default.
2997    Builder.defineMacro("_M_IX86", "600");
2998  }
2999};
3000} // end anonymous namespace
3001
3002namespace {
3003// x86-32 MinGW target
3004class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3005public:
3006  MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3007      : WindowsX86_32TargetInfo(Triple) {}
3008  virtual void getTargetDefines(const LangOptions &Opts,
3009                                MacroBuilder &Builder) const {
3010    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3011    DefineStd(Builder, "WIN32", Opts);
3012    DefineStd(Builder, "WINNT", Opts);
3013    Builder.defineMacro("_X86_");
3014    Builder.defineMacro("__MSVCRT__");
3015    Builder.defineMacro("__MINGW32__");
3016
3017    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3018    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3019    if (Opts.MicrosoftExt)
3020      // Provide "as-is" __declspec.
3021      Builder.defineMacro("__declspec", "__declspec");
3022    else
3023      // Provide alias of __attribute__ like mingw32-gcc.
3024      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3025  }
3026};
3027} // end anonymous namespace
3028
3029namespace {
3030// x86-32 Cygwin target
3031class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3032public:
3033  CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3034      : X86_32TargetInfo(Triple) {
3035    TLSSupported = false;
3036    WCharType = UnsignedShort;
3037    DoubleAlign = LongLongAlign = 64;
3038    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3039                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3040                        "a0:0:64-f80:32:32-n8:16:32-S32";
3041  }
3042  virtual void getTargetDefines(const LangOptions &Opts,
3043                                MacroBuilder &Builder) const {
3044    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3045    Builder.defineMacro("_X86_");
3046    Builder.defineMacro("__CYGWIN__");
3047    Builder.defineMacro("__CYGWIN32__");
3048    DefineStd(Builder, "unix", Opts);
3049    if (Opts.CPlusPlus)
3050      Builder.defineMacro("_GNU_SOURCE");
3051  }
3052};
3053} // end anonymous namespace
3054
3055namespace {
3056// x86-32 Haiku target
3057class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3058public:
3059  HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3060    SizeType = UnsignedLong;
3061    IntPtrType = SignedLong;
3062    PtrDiffType = SignedLong;
3063    ProcessIDType = SignedLong;
3064    this->UserLabelPrefix = "";
3065    this->TLSSupported = false;
3066  }
3067  virtual void getTargetDefines(const LangOptions &Opts,
3068                                MacroBuilder &Builder) const {
3069    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3070    Builder.defineMacro("__INTEL__");
3071    Builder.defineMacro("__HAIKU__");
3072  }
3073};
3074} // end anonymous namespace
3075
3076// RTEMS Target
3077template<typename Target>
3078class RTEMSTargetInfo : public OSTargetInfo<Target> {
3079protected:
3080  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3081                            MacroBuilder &Builder) const {
3082    // RTEMS defines; list based off of gcc output
3083
3084    Builder.defineMacro("__rtems__");
3085    Builder.defineMacro("__ELF__");
3086  }
3087
3088public:
3089  RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3090    this->UserLabelPrefix = "";
3091
3092    switch (Triple.getArch()) {
3093    default:
3094    case llvm::Triple::x86:
3095      // this->MCountName = ".mcount";
3096      break;
3097    case llvm::Triple::mips:
3098    case llvm::Triple::mipsel:
3099    case llvm::Triple::ppc:
3100    case llvm::Triple::ppc64:
3101      // this->MCountName = "_mcount";
3102      break;
3103    case llvm::Triple::arm:
3104      // this->MCountName = "__mcount";
3105      break;
3106    }
3107  }
3108};
3109
3110namespace {
3111// x86-32 RTEMS target
3112class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3113public:
3114  RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3115    SizeType = UnsignedLong;
3116    IntPtrType = SignedLong;
3117    PtrDiffType = SignedLong;
3118    this->UserLabelPrefix = "";
3119  }
3120  virtual void getTargetDefines(const LangOptions &Opts,
3121                                MacroBuilder &Builder) const {
3122    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3123    Builder.defineMacro("__INTEL__");
3124    Builder.defineMacro("__rtems__");
3125  }
3126};
3127} // end anonymous namespace
3128
3129namespace {
3130// x86-64 generic target
3131class X86_64TargetInfo : public X86TargetInfo {
3132public:
3133  X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3134    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3135    LongDoubleWidth = 128;
3136    LongDoubleAlign = 128;
3137    LargeArrayMinWidth = 128;
3138    LargeArrayAlign = 128;
3139    SuitableAlign = 128;
3140    IntMaxType = SignedLong;
3141    UIntMaxType = UnsignedLong;
3142    Int64Type = SignedLong;
3143    RegParmMax = 6;
3144
3145    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3146                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3147                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3148
3149    // Use fpret only for long double.
3150    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3151
3152    // Use fp2ret for _Complex long double.
3153    ComplexLongDoubleUsesFP2Ret = true;
3154
3155    // x86-64 has atomics up to 16 bytes.
3156    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3157    // on CPUs with cmpxchg16b
3158    MaxAtomicPromoteWidth = 128;
3159    MaxAtomicInlineWidth = 64;
3160  }
3161  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3162    return TargetInfo::X86_64ABIBuiltinVaList;
3163  }
3164
3165  int getEHDataRegisterNumber(unsigned RegNo) const {
3166    if (RegNo == 0) return 0;
3167    if (RegNo == 1) return 1;
3168    return -1;
3169  }
3170
3171  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3172    return (CC == CC_Default ||
3173            CC == CC_C ||
3174            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3175  }
3176
3177  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3178    return CC_C;
3179  }
3180
3181};
3182} // end anonymous namespace
3183
3184namespace {
3185// x86-64 Windows target
3186class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3187public:
3188  WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3189      : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3190    TLSSupported = false;
3191    WCharType = UnsignedShort;
3192    LongWidth = LongAlign = 32;
3193    DoubleAlign = LongLongAlign = 64;
3194    IntMaxType = SignedLongLong;
3195    UIntMaxType = UnsignedLongLong;
3196    Int64Type = SignedLongLong;
3197    SizeType = UnsignedLongLong;
3198    PtrDiffType = SignedLongLong;
3199    IntPtrType = SignedLongLong;
3200    this->UserLabelPrefix = "";
3201  }
3202  virtual void getTargetDefines(const LangOptions &Opts,
3203                                MacroBuilder &Builder) const {
3204    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3205    Builder.defineMacro("_WIN64");
3206  }
3207  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3208    return TargetInfo::CharPtrBuiltinVaList;
3209  }
3210};
3211} // end anonymous namespace
3212
3213namespace {
3214// x86-64 Windows Visual Studio target
3215class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3216public:
3217  VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3218      : WindowsX86_64TargetInfo(Triple) {
3219    LongDoubleWidth = LongDoubleAlign = 64;
3220    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3221  }
3222  virtual void getTargetDefines(const LangOptions &Opts,
3223                                MacroBuilder &Builder) const {
3224    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3225    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3226    Builder.defineMacro("_M_X64");
3227    Builder.defineMacro("_M_AMD64");
3228  }
3229};
3230} // end anonymous namespace
3231
3232namespace {
3233// x86-64 MinGW target
3234class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3235public:
3236  MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3237      : WindowsX86_64TargetInfo(Triple) {}
3238  virtual void getTargetDefines(const LangOptions &Opts,
3239                                MacroBuilder &Builder) const {
3240    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3241    DefineStd(Builder, "WIN64", Opts);
3242    Builder.defineMacro("__MSVCRT__");
3243    Builder.defineMacro("__MINGW32__");
3244    Builder.defineMacro("__MINGW64__");
3245
3246    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3247    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3248    if (Opts.MicrosoftExt)
3249      // Provide "as-is" __declspec.
3250      Builder.defineMacro("__declspec", "__declspec");
3251    else
3252      // Provide alias of __attribute__ like mingw32-gcc.
3253      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3254  }
3255};
3256} // end anonymous namespace
3257
3258namespace {
3259class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3260public:
3261  DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3262      : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3263    Int64Type = SignedLongLong;
3264    MaxVectorAlign = 256;
3265  }
3266};
3267} // end anonymous namespace
3268
3269namespace {
3270class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3271public:
3272  OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3273      : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3274    IntMaxType = SignedLongLong;
3275    UIntMaxType = UnsignedLongLong;
3276    Int64Type = SignedLongLong;
3277  }
3278};
3279} // end anonymous namespace
3280
3281namespace {
3282class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3283public:
3284  BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3285      : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3286    IntMaxType = SignedLongLong;
3287    UIntMaxType = UnsignedLongLong;
3288    Int64Type = SignedLongLong;
3289  }
3290};
3291}
3292
3293namespace {
3294class AArch64TargetInfo : public TargetInfo {
3295  static const char * const GCCRegNames[];
3296  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3297
3298  static const Builtin::Info BuiltinInfo[];
3299public:
3300  AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3301    BigEndian = false;
3302    LongWidth = LongAlign = 64;
3303    LongDoubleWidth = LongDoubleAlign = 128;
3304    PointerWidth = PointerAlign = 64;
3305    SuitableAlign = 128;
3306    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3307                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3308                        "f128:128:128-n32:64-S128";
3309
3310    WCharType = UnsignedInt;
3311    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3312
3313    // AArch64 backend supports 64-bit operations at the moment. In principle
3314    // 128-bit is possible if register-pairs are used.
3315    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3316
3317    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3318  }
3319  virtual void getTargetDefines(const LangOptions &Opts,
3320                                MacroBuilder &Builder) const {
3321    // GCC defines theses currently
3322    Builder.defineMacro("__aarch64__");
3323    Builder.defineMacro("__AARCH64EL__");
3324
3325    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3326
3327    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3328    // which was intended to be compatible with a 64-bit implementation. They
3329    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3330    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3331    Builder.defineMacro("__ARM_ACLE",         "101");
3332    Builder.defineMacro("__ARM_ARCH",         "8");
3333    Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3334
3335    Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3336    Builder.defineMacro("__ARM_FEATURE_CLZ");
3337    Builder.defineMacro("__ARM_FEATURE_FMA");
3338
3339    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3340    // 128-bit LDXP present, at which point this becomes 0x1f.
3341    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3342
3343    // 0xe implies support for half, single and double precision operations.
3344    Builder.defineMacro("__ARM_FP", "0xe");
3345
3346    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3347    // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3348    Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3349
3350    if (Opts.FastMath || Opts.FiniteMathOnly)
3351      Builder.defineMacro("__ARM_FP_FAST");
3352
3353    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3354      Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3355
3356    Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3357                        Opts.ShortWChar ? "2" : "4");
3358
3359    Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3360                        Opts.ShortEnums ? "1" : "4");
3361
3362    if (BigEndian)
3363      Builder.defineMacro("__ARM_BIG_ENDIAN");
3364  }
3365  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3366                                 unsigned &NumRecords) const {
3367    Records = BuiltinInfo;
3368    NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3369  }
3370  virtual bool hasFeature(StringRef Feature) const {
3371    return Feature == "aarch64";
3372  }
3373  virtual void getGCCRegNames(const char * const *&Names,
3374                              unsigned &NumNames) const;
3375  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3376                                unsigned &NumAliases) const;
3377
3378  virtual bool isCLZForZeroUndef() const { return false; }
3379
3380  virtual bool validateAsmConstraint(const char *&Name,
3381                                     TargetInfo::ConstraintInfo &Info) const {
3382    switch (*Name) {
3383    default: return false;
3384    case 'w': // An FP/SIMD vector register
3385      Info.setAllowsRegister();
3386      return true;
3387    case 'I': // Constant that can be used with an ADD instruction
3388    case 'J': // Constant that can be used with a SUB instruction
3389    case 'K': // Constant that can be used with a 32-bit logical instruction
3390    case 'L': // Constant that can be used with a 64-bit logical instruction
3391    case 'M': // Constant that can be used as a 32-bit MOV immediate
3392    case 'N': // Constant that can be used as a 64-bit MOV immediate
3393    case 'Y': // Floating point constant zero
3394    case 'Z': // Integer constant zero
3395      return true;
3396    case 'Q': // A memory reference with base register and no offset
3397      Info.setAllowsMemory();
3398      return true;
3399    case 'S': // A symbolic address
3400      Info.setAllowsRegister();
3401      return true;
3402    case 'U':
3403      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3404      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3405      // Usa: An absolute symbolic address
3406      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3407      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3408    }
3409  }
3410
3411  virtual const char *getClobbers() const {
3412    // There are no AArch64 clobbers shared by all asm statements.
3413    return "";
3414  }
3415
3416  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3417    return TargetInfo::AArch64ABIBuiltinVaList;
3418  }
3419};
3420
3421const char * const AArch64TargetInfo::GCCRegNames[] = {
3422  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3423  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3424  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3425  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3426
3427  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3428  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3429  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3430  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3431
3432  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3433  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3434  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3435  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3436
3437  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3438  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3439  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3440  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3441
3442  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3443  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3444  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3445  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3446
3447  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3448  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3449  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3450  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3451
3452  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3453  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3454  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3455  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3456};
3457
3458void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3459                                       unsigned &NumNames) const {
3460  Names = GCCRegNames;
3461  NumNames = llvm::array_lengthof(GCCRegNames);
3462}
3463
3464const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3465  { { "x16" }, "ip0"},
3466  { { "x17" }, "ip1"},
3467  { { "x29" }, "fp" },
3468  { { "x30" }, "lr" }
3469};
3470
3471void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3472                                         unsigned &NumAliases) const {
3473  Aliases = GCCRegAliases;
3474  NumAliases = llvm::array_lengthof(GCCRegAliases);
3475
3476}
3477
3478const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3479#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3480#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3481                                              ALL_LANGUAGES },
3482#include "clang/Basic/BuiltinsAArch64.def"
3483};
3484
3485} // end anonymous namespace
3486
3487namespace {
3488class ARMTargetInfo : public TargetInfo {
3489  // Possible FPU choices.
3490  enum FPUMode {
3491    VFP2FPU = (1 << 0),
3492    VFP3FPU = (1 << 1),
3493    VFP4FPU = (1 << 2),
3494    NeonFPU = (1 << 3)
3495  };
3496
3497  static bool FPUModeIsVFP(FPUMode Mode) {
3498    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3499  }
3500
3501  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3502  static const char * const GCCRegNames[];
3503
3504  std::string ABI, CPU;
3505
3506  unsigned FPU : 4;
3507
3508  unsigned IsAAPCS : 1;
3509  unsigned IsThumb : 1;
3510
3511  // Initialized via features.
3512  unsigned SoftFloat : 1;
3513  unsigned SoftFloatABI : 1;
3514
3515  static const Builtin::Info BuiltinInfo[];
3516
3517  static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3518    // On linux, binaries targeting old cpus call functions in libgcc to
3519    // perform atomic operations. The implementation in libgcc then calls into
3520    // the kernel which on armv6 and newer uses ldrex and strex. The net result
3521    // is that if we assume the kernel is at least as recent as the hardware,
3522    // it is safe to use atomic instructions on armv6 and newer.
3523    if (T.getOS() != llvm::Triple::Linux &&
3524        T.getOS() != llvm::Triple::FreeBSD &&
3525        T.getOS() != llvm::Triple::Bitrig)
3526      return false;
3527    StringRef ArchName = T.getArchName();
3528    if (T.getArch() == llvm::Triple::arm) {
3529      if (!ArchName.startswith("armv"))
3530        return false;
3531      StringRef VersionStr = ArchName.substr(4);
3532      unsigned Version;
3533      if (VersionStr.getAsInteger(10, Version))
3534        return false;
3535      return Version >= 6;
3536    }
3537    assert(T.getArch() == llvm::Triple::thumb);
3538    if (!ArchName.startswith("thumbv"))
3539      return false;
3540    StringRef VersionStr = ArchName.substr(6);
3541    unsigned Version;
3542    if (VersionStr.getAsInteger(10, Version))
3543      return false;
3544    return Version >= 7;
3545  }
3546
3547public:
3548  ARMTargetInfo(const llvm::Triple &Triple)
3549      : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3550        IsAAPCS(true) {
3551    BigEndian = false;
3552    SizeType = UnsignedInt;
3553    PtrDiffType = SignedInt;
3554    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3555    WCharType = UnsignedInt;
3556
3557    // {} in inline assembly are neon specifiers, not assembly variant
3558    // specifiers.
3559    NoAsmVariants = true;
3560
3561    // FIXME: Should we just treat this as a feature?
3562    IsThumb = getTriple().getArchName().startswith("thumb");
3563    if (IsThumb) {
3564      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3565      // so set preferred for small types to 32.
3566      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3567                           "i64:64:64-f32:32:32-f64:64:64-"
3568                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3569    } else {
3570      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3571                           "i64:64:64-f32:32:32-f64:64:64-"
3572                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3573    }
3574
3575    // ARM targets default to using the ARM C++ ABI.
3576    TheCXXABI.set(TargetCXXABI::GenericARM);
3577
3578    // ARM has atomics up to 8 bytes
3579    MaxAtomicPromoteWidth = 64;
3580    if (shouldUseInlineAtomic(getTriple()))
3581      MaxAtomicInlineWidth = 64;
3582
3583    // Do force alignment of members that follow zero length bitfields.  If
3584    // the alignment of the zero-length bitfield is greater than the member
3585    // that follows it, `bar', `bar' will be aligned as the  type of the
3586    // zero length bitfield.
3587    UseZeroLengthBitfieldAlignment = true;
3588  }
3589  virtual const char *getABI() const { return ABI.c_str(); }
3590  virtual bool setABI(const std::string &Name) {
3591    ABI = Name;
3592
3593    // The defaults (above) are for AAPCS, check if we need to change them.
3594    //
3595    // FIXME: We need support for -meabi... we could just mangle it into the
3596    // name.
3597    if (Name == "apcs-gnu") {
3598      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3599      // size_t is unsigned int on FreeBSD.
3600      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3601        SizeType = UnsignedLong;
3602
3603      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3604      WCharType = SignedInt;
3605
3606      // Do not respect the alignment of bit-field types when laying out
3607      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3608      UseBitFieldTypeAlignment = false;
3609
3610      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3611      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3612      /// gcc.
3613      ZeroLengthBitfieldBoundary = 32;
3614
3615      IsAAPCS = false;
3616
3617      if (IsThumb) {
3618        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3619        // so set preferred for small types to 32.
3620        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3621                             "i64:32:64-f32:32:32-f64:32:64-"
3622                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3623      } else {
3624        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3625                             "i64:32:64-f32:32:32-f64:32:64-"
3626                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3627      }
3628
3629      // FIXME: Override "preferred align" for double and long long.
3630    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3631      // size_t is unsigned long on Darwin.
3632      if (getTriple().isOSDarwin())
3633        SizeType = UnsignedLong;
3634      IsAAPCS = true;
3635      // FIXME: Enumerated types are variable width in straight AAPCS.
3636    } else if (Name == "aapcs-linux") {
3637      IsAAPCS = true;
3638    } else
3639      return false;
3640
3641    return true;
3642  }
3643
3644  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3645    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3646      Features["vfp2"] = true;
3647    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3648             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3649      Features["neon"] = true;
3650    else if (CPU == "swift" || CPU == "cortex-a7") {
3651      Features["vfp4"] = true;
3652      Features["neon"] = true;
3653    }
3654  }
3655
3656  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3657                                 StringRef Name,
3658                                 bool Enabled) const {
3659    if (Name == "soft-float" || Name == "soft-float-abi" ||
3660        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3661        Name == "d16" || Name == "neonfp" || Name == "v8fp") {
3662      Features[Name] = Enabled;
3663    } else
3664      return false;
3665
3666    return true;
3667  }
3668
3669  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3670    FPU = 0;
3671    SoftFloat = SoftFloatABI = false;
3672    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3673      if (Features[i] == "+soft-float")
3674        SoftFloat = true;
3675      else if (Features[i] == "+soft-float-abi")
3676        SoftFloatABI = true;
3677      else if (Features[i] == "+vfp2")
3678        FPU |= VFP2FPU;
3679      else if (Features[i] == "+vfp3")
3680        FPU |= VFP3FPU;
3681      else if (Features[i] == "+vfp4")
3682        FPU |= VFP4FPU;
3683      else if (Features[i] == "+neon")
3684        FPU |= NeonFPU;
3685    }
3686
3687    // Remove front-end specific options which the backend handles differently.
3688    std::vector<std::string>::iterator it;
3689    it = std::find(Features.begin(), Features.end(), "+soft-float");
3690    if (it != Features.end())
3691      Features.erase(it);
3692    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3693    if (it != Features.end())
3694      Features.erase(it);
3695  }
3696
3697  virtual bool hasFeature(StringRef Feature) const {
3698    return llvm::StringSwitch<bool>(Feature)
3699        .Case("arm", true)
3700        .Case("softfloat", SoftFloat)
3701        .Case("thumb", IsThumb)
3702        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3703              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3704        .Default(false);
3705  }
3706  // FIXME: Should we actually have some table instead of these switches?
3707  static const char *getCPUDefineSuffix(StringRef Name) {
3708    return llvm::StringSwitch<const char*>(Name)
3709      .Cases("arm8", "arm810", "4")
3710      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3711      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3712      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3713      .Case("ep9312", "4T")
3714      .Cases("arm10tdmi", "arm1020t", "5T")
3715      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3716      .Case("arm926ej-s", "5TEJ")
3717      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3718      .Cases("xscale", "iwmmxt", "5TE")
3719      .Case("arm1136j-s", "6J")
3720      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3721      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3722      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3723      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3724      .Cases("cortex-a9", "cortex-a15", "7A")
3725      .Case("cortex-r5", "7R")
3726      .Case("cortex-a9-mp", "7F")
3727      .Case("swift", "7S")
3728      .Cases("cortex-m3", "cortex-m4", "7M")
3729      .Case("cortex-m0", "6M")
3730      .Case("cortex-a53", "8A")
3731      .Default(0);
3732  }
3733  static const char *getCPUProfile(StringRef Name) {
3734    return llvm::StringSwitch<const char*>(Name)
3735      .Cases("cortex-a8", "cortex-a9", "A")
3736      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3737      .Case("cortex-r5", "R")
3738      .Default("");
3739  }
3740  virtual bool setCPU(const std::string &Name) {
3741    if (!getCPUDefineSuffix(Name))
3742      return false;
3743
3744    CPU = Name;
3745    return true;
3746  }
3747  virtual void getTargetDefines(const LangOptions &Opts,
3748                                MacroBuilder &Builder) const {
3749    // Target identification.
3750    Builder.defineMacro("__arm");
3751    Builder.defineMacro("__arm__");
3752
3753    // Target properties.
3754    Builder.defineMacro("__ARMEL__");
3755    Builder.defineMacro("__LITTLE_ENDIAN__");
3756    Builder.defineMacro("__REGISTER_PREFIX__", "");
3757
3758    StringRef CPUArch = getCPUDefineSuffix(CPU);
3759    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3760    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3761    StringRef CPUProfile = getCPUProfile(CPU);
3762    if (!CPUProfile.empty())
3763      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3764
3765    // Subtarget options.
3766
3767    // FIXME: It's more complicated than this and we don't really support
3768    // interworking.
3769    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3770      Builder.defineMacro("__THUMB_INTERWORK__");
3771
3772    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3773      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3774      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3775        Builder.defineMacro("__ARM_EABI__");
3776      Builder.defineMacro("__ARM_PCS", "1");
3777
3778      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3779        Builder.defineMacro("__ARM_PCS_VFP", "1");
3780    }
3781
3782    if (SoftFloat)
3783      Builder.defineMacro("__SOFTFP__");
3784
3785    if (CPU == "xscale")
3786      Builder.defineMacro("__XSCALE__");
3787
3788    bool IsARMv7 = CPUArch.startswith("7");
3789    if (IsThumb) {
3790      Builder.defineMacro("__THUMBEL__");
3791      Builder.defineMacro("__thumb__");
3792      if (CPUArch == "6T2" || IsARMv7)
3793        Builder.defineMacro("__thumb2__");
3794    }
3795
3796    // Note, this is always on in gcc, even though it doesn't make sense.
3797    Builder.defineMacro("__APCS_32__");
3798
3799    if (FPUModeIsVFP((FPUMode) FPU)) {
3800      Builder.defineMacro("__VFP_FP__");
3801      if (FPU & VFP2FPU)
3802        Builder.defineMacro("__ARM_VFPV2__");
3803      if (FPU & VFP3FPU)
3804        Builder.defineMacro("__ARM_VFPV3__");
3805      if (FPU & VFP4FPU)
3806        Builder.defineMacro("__ARM_VFPV4__");
3807    }
3808
3809    // This only gets set when Neon instructions are actually available, unlike
3810    // the VFP define, hence the soft float and arch check. This is subtly
3811    // different from gcc, we follow the intent which was that it should be set
3812    // when Neon instructions are actually available.
3813    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3814      Builder.defineMacro("__ARM_NEON__");
3815  }
3816  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3817                                 unsigned &NumRecords) const {
3818    Records = BuiltinInfo;
3819    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3820  }
3821  virtual bool isCLZForZeroUndef() const { return false; }
3822  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3823    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3824  }
3825  virtual void getGCCRegNames(const char * const *&Names,
3826                              unsigned &NumNames) const;
3827  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3828                                unsigned &NumAliases) const;
3829  virtual bool validateAsmConstraint(const char *&Name,
3830                                     TargetInfo::ConstraintInfo &Info) const {
3831    switch (*Name) {
3832    default: break;
3833    case 'l': // r0-r7
3834    case 'h': // r8-r15
3835    case 'w': // VFP Floating point register single precision
3836    case 'P': // VFP Floating point register double precision
3837      Info.setAllowsRegister();
3838      return true;
3839    case 'Q': // A memory address that is a single base register.
3840      Info.setAllowsMemory();
3841      return true;
3842    case 'U': // a memory reference...
3843      switch (Name[1]) {
3844      case 'q': // ...ARMV4 ldrsb
3845      case 'v': // ...VFP load/store (reg+constant offset)
3846      case 'y': // ...iWMMXt load/store
3847      case 't': // address valid for load/store opaque types wider
3848                // than 128-bits
3849      case 'n': // valid address for Neon doubleword vector load/store
3850      case 'm': // valid address for Neon element and structure load/store
3851      case 's': // valid address for non-offset loads/stores of quad-word
3852                // values in four ARM registers
3853        Info.setAllowsMemory();
3854        Name++;
3855        return true;
3856      }
3857    }
3858    return false;
3859  }
3860  virtual std::string convertConstraint(const char *&Constraint) const {
3861    std::string R;
3862    switch (*Constraint) {
3863    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3864      R = std::string("^") + std::string(Constraint, 2);
3865      Constraint++;
3866      break;
3867    case 'p': // 'p' should be translated to 'r' by default.
3868      R = std::string("r");
3869      break;
3870    default:
3871      return std::string(1, *Constraint);
3872    }
3873    return R;
3874  }
3875  virtual bool validateConstraintModifier(StringRef Constraint,
3876                                          const char Modifier,
3877                                          unsigned Size) const {
3878    bool isOutput = (Constraint[0] == '=');
3879    bool isInOut = (Constraint[0] == '+');
3880
3881    // Strip off constraint modifiers.
3882    while (Constraint[0] == '=' ||
3883           Constraint[0] == '+' ||
3884           Constraint[0] == '&')
3885      Constraint = Constraint.substr(1);
3886
3887    switch (Constraint[0]) {
3888    default: break;
3889    case 'r': {
3890      switch (Modifier) {
3891      default:
3892        return (isInOut || isOutput || Size <= 32);
3893      case 'q':
3894        // A register of size 32 cannot fit a vector type.
3895        return false;
3896      }
3897    }
3898    }
3899
3900    return true;
3901  }
3902  virtual const char *getClobbers() const {
3903    // FIXME: Is this really right?
3904    return "";
3905  }
3906
3907  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3908    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3909  }
3910
3911  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3912    if (RegNo == 0) return 0;
3913    if (RegNo == 1) return 1;
3914    return -1;
3915  }
3916};
3917
3918const char * const ARMTargetInfo::GCCRegNames[] = {
3919  // Integer registers
3920  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3921  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3922
3923  // Float registers
3924  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3925  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3926  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3927  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3928
3929  // Double registers
3930  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3931  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3932  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3933  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3934
3935  // Quad registers
3936  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3937  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3938};
3939
3940void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3941                                   unsigned &NumNames) const {
3942  Names = GCCRegNames;
3943  NumNames = llvm::array_lengthof(GCCRegNames);
3944}
3945
3946const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3947  { { "a1" }, "r0" },
3948  { { "a2" }, "r1" },
3949  { { "a3" }, "r2" },
3950  { { "a4" }, "r3" },
3951  { { "v1" }, "r4" },
3952  { { "v2" }, "r5" },
3953  { { "v3" }, "r6" },
3954  { { "v4" }, "r7" },
3955  { { "v5" }, "r8" },
3956  { { "v6", "rfp" }, "r9" },
3957  { { "sl" }, "r10" },
3958  { { "fp" }, "r11" },
3959  { { "ip" }, "r12" },
3960  { { "r13" }, "sp" },
3961  { { "r14" }, "lr" },
3962  { { "r15" }, "pc" },
3963  // The S, D and Q registers overlap, but aren't really aliases; we
3964  // don't want to substitute one of these for a different-sized one.
3965};
3966
3967void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3968                                       unsigned &NumAliases) const {
3969  Aliases = GCCRegAliases;
3970  NumAliases = llvm::array_lengthof(GCCRegAliases);
3971}
3972
3973const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3974#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3975#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3976                                              ALL_LANGUAGES },
3977#include "clang/Basic/BuiltinsARM.def"
3978};
3979} // end anonymous namespace.
3980
3981namespace {
3982class DarwinARMTargetInfo :
3983  public DarwinTargetInfo<ARMTargetInfo> {
3984protected:
3985  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3986                            MacroBuilder &Builder) const {
3987    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3988  }
3989
3990public:
3991  DarwinARMTargetInfo(const llvm::Triple &Triple)
3992      : DarwinTargetInfo<ARMTargetInfo>(Triple) {
3993    HasAlignMac68kSupport = true;
3994    // iOS always has 64-bit atomic instructions.
3995    // FIXME: This should be based off of the target features in ARMTargetInfo.
3996    MaxAtomicInlineWidth = 64;
3997
3998    // Darwin on iOS uses a variant of the ARM C++ ABI.
3999    TheCXXABI.set(TargetCXXABI::iOS);
4000  }
4001};
4002} // end anonymous namespace.
4003
4004
4005namespace {
4006// Hexagon abstract base class
4007class HexagonTargetInfo : public TargetInfo {
4008  static const Builtin::Info BuiltinInfo[];
4009  static const char * const GCCRegNames[];
4010  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4011  std::string CPU;
4012public:
4013  HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4014    BigEndian = false;
4015    DescriptionString = ("e-p:32:32:32-"
4016                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4017                         "f64:64:64-f32:32:32-a0:0-n32");
4018
4019    // {} in inline assembly are packet specifiers, not assembly variant
4020    // specifiers.
4021    NoAsmVariants = true;
4022  }
4023
4024  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4025                                 unsigned &NumRecords) const {
4026    Records = BuiltinInfo;
4027    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4028  }
4029
4030  virtual bool validateAsmConstraint(const char *&Name,
4031                                     TargetInfo::ConstraintInfo &Info) const {
4032    return true;
4033  }
4034
4035  virtual void getTargetDefines(const LangOptions &Opts,
4036                                MacroBuilder &Builder) const;
4037
4038  virtual bool hasFeature(StringRef Feature) const {
4039    return Feature == "hexagon";
4040  }
4041
4042  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4043    return TargetInfo::CharPtrBuiltinVaList;
4044  }
4045  virtual void getGCCRegNames(const char * const *&Names,
4046                              unsigned &NumNames) const;
4047  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4048                                unsigned &NumAliases) const;
4049  virtual const char *getClobbers() const {
4050    return "";
4051  }
4052
4053  static const char *getHexagonCPUSuffix(StringRef Name) {
4054    return llvm::StringSwitch<const char*>(Name)
4055      .Case("hexagonv4", "4")
4056      .Case("hexagonv5", "5")
4057      .Default(0);
4058  }
4059
4060  virtual bool setCPU(const std::string &Name) {
4061    if (!getHexagonCPUSuffix(Name))
4062      return false;
4063
4064    CPU = Name;
4065    return true;
4066  }
4067};
4068
4069void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4070                                MacroBuilder &Builder) const {
4071  Builder.defineMacro("qdsp6");
4072  Builder.defineMacro("__qdsp6", "1");
4073  Builder.defineMacro("__qdsp6__", "1");
4074
4075  Builder.defineMacro("hexagon");
4076  Builder.defineMacro("__hexagon", "1");
4077  Builder.defineMacro("__hexagon__", "1");
4078
4079  if(CPU == "hexagonv1") {
4080    Builder.defineMacro("__HEXAGON_V1__");
4081    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4082    if(Opts.HexagonQdsp6Compat) {
4083      Builder.defineMacro("__QDSP6_V1__");
4084      Builder.defineMacro("__QDSP6_ARCH__", "1");
4085    }
4086  }
4087  else if(CPU == "hexagonv2") {
4088    Builder.defineMacro("__HEXAGON_V2__");
4089    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4090    if(Opts.HexagonQdsp6Compat) {
4091      Builder.defineMacro("__QDSP6_V2__");
4092      Builder.defineMacro("__QDSP6_ARCH__", "2");
4093    }
4094  }
4095  else if(CPU == "hexagonv3") {
4096    Builder.defineMacro("__HEXAGON_V3__");
4097    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4098    if(Opts.HexagonQdsp6Compat) {
4099      Builder.defineMacro("__QDSP6_V3__");
4100      Builder.defineMacro("__QDSP6_ARCH__", "3");
4101    }
4102  }
4103  else if(CPU == "hexagonv4") {
4104    Builder.defineMacro("__HEXAGON_V4__");
4105    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4106    if(Opts.HexagonQdsp6Compat) {
4107      Builder.defineMacro("__QDSP6_V4__");
4108      Builder.defineMacro("__QDSP6_ARCH__", "4");
4109    }
4110  }
4111  else if(CPU == "hexagonv5") {
4112    Builder.defineMacro("__HEXAGON_V5__");
4113    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4114    if(Opts.HexagonQdsp6Compat) {
4115      Builder.defineMacro("__QDSP6_V5__");
4116      Builder.defineMacro("__QDSP6_ARCH__", "5");
4117    }
4118  }
4119}
4120
4121const char * const HexagonTargetInfo::GCCRegNames[] = {
4122  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4123  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4124  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4125  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4126  "p0", "p1", "p2", "p3",
4127  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4128};
4129
4130void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4131                                   unsigned &NumNames) const {
4132  Names = GCCRegNames;
4133  NumNames = llvm::array_lengthof(GCCRegNames);
4134}
4135
4136
4137const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4138  { { "sp" }, "r29" },
4139  { { "fp" }, "r30" },
4140  { { "lr" }, "r31" },
4141 };
4142
4143void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4144                                     unsigned &NumAliases) const {
4145  Aliases = GCCRegAliases;
4146  NumAliases = llvm::array_lengthof(GCCRegAliases);
4147}
4148
4149
4150const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4151#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4152#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4153                                              ALL_LANGUAGES },
4154#include "clang/Basic/BuiltinsHexagon.def"
4155};
4156}
4157
4158
4159namespace {
4160// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4161class SparcTargetInfo : public TargetInfo {
4162  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4163  static const char * const GCCRegNames[];
4164  bool SoftFloat;
4165public:
4166  SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4167
4168  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4169                                 StringRef Name,
4170                                 bool Enabled) const {
4171    if (Name == "soft-float")
4172      Features[Name] = Enabled;
4173    else
4174      return false;
4175
4176    return true;
4177  }
4178  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4179    SoftFloat = false;
4180    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4181      if (Features[i] == "+soft-float")
4182        SoftFloat = true;
4183  }
4184  virtual void getTargetDefines(const LangOptions &Opts,
4185                                MacroBuilder &Builder) const {
4186    DefineStd(Builder, "sparc", Opts);
4187    Builder.defineMacro("__REGISTER_PREFIX__", "");
4188
4189    if (SoftFloat)
4190      Builder.defineMacro("SOFT_FLOAT", "1");
4191  }
4192
4193  virtual bool hasFeature(StringRef Feature) const {
4194    return llvm::StringSwitch<bool>(Feature)
4195             .Case("softfloat", SoftFloat)
4196             .Case("sparc", true)
4197             .Default(false);
4198  }
4199
4200  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4201                                 unsigned &NumRecords) const {
4202    // FIXME: Implement!
4203  }
4204  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4205    return TargetInfo::VoidPtrBuiltinVaList;
4206  }
4207  virtual void getGCCRegNames(const char * const *&Names,
4208                              unsigned &NumNames) const;
4209  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4210                                unsigned &NumAliases) const;
4211  virtual bool validateAsmConstraint(const char *&Name,
4212                                     TargetInfo::ConstraintInfo &info) const {
4213    // FIXME: Implement!
4214    return false;
4215  }
4216  virtual const char *getClobbers() const {
4217    // FIXME: Implement!
4218    return "";
4219  }
4220};
4221
4222const char * const SparcTargetInfo::GCCRegNames[] = {
4223  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4224  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4225  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4226  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4227};
4228
4229void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4230                                     unsigned &NumNames) const {
4231  Names = GCCRegNames;
4232  NumNames = llvm::array_lengthof(GCCRegNames);
4233}
4234
4235const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4236  { { "g0" }, "r0" },
4237  { { "g1" }, "r1" },
4238  { { "g2" }, "r2" },
4239  { { "g3" }, "r3" },
4240  { { "g4" }, "r4" },
4241  { { "g5" }, "r5" },
4242  { { "g6" }, "r6" },
4243  { { "g7" }, "r7" },
4244  { { "o0" }, "r8" },
4245  { { "o1" }, "r9" },
4246  { { "o2" }, "r10" },
4247  { { "o3" }, "r11" },
4248  { { "o4" }, "r12" },
4249  { { "o5" }, "r13" },
4250  { { "o6", "sp" }, "r14" },
4251  { { "o7" }, "r15" },
4252  { { "l0" }, "r16" },
4253  { { "l1" }, "r17" },
4254  { { "l2" }, "r18" },
4255  { { "l3" }, "r19" },
4256  { { "l4" }, "r20" },
4257  { { "l5" }, "r21" },
4258  { { "l6" }, "r22" },
4259  { { "l7" }, "r23" },
4260  { { "i0" }, "r24" },
4261  { { "i1" }, "r25" },
4262  { { "i2" }, "r26" },
4263  { { "i3" }, "r27" },
4264  { { "i4" }, "r28" },
4265  { { "i5" }, "r29" },
4266  { { "i6", "fp" }, "r30" },
4267  { { "i7" }, "r31" },
4268};
4269
4270void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4271                                       unsigned &NumAliases) const {
4272  Aliases = GCCRegAliases;
4273  NumAliases = llvm::array_lengthof(GCCRegAliases);
4274}
4275
4276// SPARC v8 is the 32-bit mode selected by Triple::sparc.
4277class SparcV8TargetInfo : public SparcTargetInfo {
4278public:
4279  SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4280    // FIXME: Support Sparc quad-precision long double?
4281    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4282                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4283  }
4284
4285  virtual void getTargetDefines(const LangOptions &Opts,
4286                                MacroBuilder &Builder) const {
4287    SparcTargetInfo::getTargetDefines(Opts, Builder);
4288    Builder.defineMacro("__sparcv8");
4289  }
4290};
4291
4292// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4293class SparcV9TargetInfo : public SparcTargetInfo {
4294public:
4295  SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4296    // FIXME: Support Sparc quad-precision long double?
4297    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4298                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4299    // This is an LP64 platform.
4300    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4301
4302    // OpenBSD uses long long for int64_t and intmax_t.
4303    if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4304      IntMaxType = SignedLongLong;
4305      UIntMaxType = UnsignedLongLong;
4306    } else {
4307      IntMaxType = SignedLong;
4308      UIntMaxType = UnsignedLong;
4309    }
4310    Int64Type = IntMaxType;
4311  }
4312
4313  virtual void getTargetDefines(const LangOptions &Opts,
4314                                MacroBuilder &Builder) const {
4315    SparcTargetInfo::getTargetDefines(Opts, Builder);
4316    Builder.defineMacro("__sparcv9");
4317    Builder.defineMacro("__arch64__");
4318    // Solaris and its derivative AuroraUX don't need these variants, but the
4319    // BSDs do.
4320    if (getTriple().getOS() != llvm::Triple::Solaris &&
4321        getTriple().getOS() != llvm::Triple::AuroraUX) {
4322      Builder.defineMacro("__sparc64__");
4323      Builder.defineMacro("__sparc_v9__");
4324      Builder.defineMacro("__sparcv9__");
4325    }
4326  }
4327};
4328
4329} // end anonymous namespace.
4330
4331namespace {
4332class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4333public:
4334  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4335      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4336    SizeType = UnsignedInt;
4337    PtrDiffType = SignedInt;
4338  }
4339};
4340class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4341public:
4342  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4343      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4344    SizeType = UnsignedInt;
4345    PtrDiffType = SignedInt;
4346  }
4347};
4348} // end anonymous namespace.
4349
4350namespace {
4351  class SystemZTargetInfo : public TargetInfo {
4352    static const char *const GCCRegNames[];
4353
4354  public:
4355    SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4356      TLSSupported = true;
4357      IntWidth = IntAlign = 32;
4358      LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4359      PointerWidth = PointerAlign = 64;
4360      LongDoubleWidth = 128;
4361      LongDoubleAlign = 64;
4362      LongDoubleFormat = &llvm::APFloat::IEEEquad;
4363      MinGlobalAlign = 16;
4364      DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4365       "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4366      MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4367    }
4368    virtual void getTargetDefines(const LangOptions &Opts,
4369                                  MacroBuilder &Builder) const {
4370      Builder.defineMacro("__s390__");
4371      Builder.defineMacro("__s390x__");
4372      Builder.defineMacro("__zarch__");
4373      Builder.defineMacro("__LONG_DOUBLE_128__");
4374    }
4375    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4376                                   unsigned &NumRecords) const {
4377      // FIXME: Implement.
4378      Records = 0;
4379      NumRecords = 0;
4380    }
4381
4382    virtual void getGCCRegNames(const char *const *&Names,
4383                                unsigned &NumNames) const;
4384    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4385                                  unsigned &NumAliases) const {
4386      // No aliases.
4387      Aliases = 0;
4388      NumAliases = 0;
4389    }
4390    virtual bool validateAsmConstraint(const char *&Name,
4391                                       TargetInfo::ConstraintInfo &info) const;
4392    virtual const char *getClobbers() const {
4393      // FIXME: Is this really right?
4394      return "";
4395    }
4396    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4397      return TargetInfo::SystemZBuiltinVaList;
4398    }
4399  };
4400
4401  const char *const SystemZTargetInfo::GCCRegNames[] = {
4402    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4403    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4404    "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4405    "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4406  };
4407
4408  void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4409                                         unsigned &NumNames) const {
4410    Names = GCCRegNames;
4411    NumNames = llvm::array_lengthof(GCCRegNames);
4412  }
4413
4414  bool SystemZTargetInfo::
4415  validateAsmConstraint(const char *&Name,
4416                        TargetInfo::ConstraintInfo &Info) const {
4417    switch (*Name) {
4418    default:
4419      return false;
4420
4421    case 'a': // Address register
4422    case 'd': // Data register (equivalent to 'r')
4423    case 'f': // Floating-point register
4424      Info.setAllowsRegister();
4425      return true;
4426
4427    case 'I': // Unsigned 8-bit constant
4428    case 'J': // Unsigned 12-bit constant
4429    case 'K': // Signed 16-bit constant
4430    case 'L': // Signed 20-bit displacement (on all targets we support)
4431    case 'M': // 0x7fffffff
4432      return true;
4433
4434    case 'Q': // Memory with base and unsigned 12-bit displacement
4435    case 'R': // Likewise, plus an index
4436    case 'S': // Memory with base and signed 20-bit displacement
4437    case 'T': // Likewise, plus an index
4438      Info.setAllowsMemory();
4439      return true;
4440    }
4441  }
4442}
4443
4444namespace {
4445  class MSP430TargetInfo : public TargetInfo {
4446    static const char * const GCCRegNames[];
4447  public:
4448    MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4449      BigEndian = false;
4450      TLSSupported = false;
4451      IntWidth = 16; IntAlign = 16;
4452      LongWidth = 32; LongLongWidth = 64;
4453      LongAlign = LongLongAlign = 16;
4454      PointerWidth = 16; PointerAlign = 16;
4455      SuitableAlign = 16;
4456      SizeType = UnsignedInt;
4457      IntMaxType = SignedLongLong;
4458      UIntMaxType = UnsignedLongLong;
4459      IntPtrType = SignedInt;
4460      PtrDiffType = SignedInt;
4461      SigAtomicType = SignedLong;
4462      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4463   }
4464    virtual void getTargetDefines(const LangOptions &Opts,
4465                                  MacroBuilder &Builder) const {
4466      Builder.defineMacro("MSP430");
4467      Builder.defineMacro("__MSP430__");
4468      // FIXME: defines for different 'flavours' of MCU
4469    }
4470    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4471                                   unsigned &NumRecords) const {
4472     // FIXME: Implement.
4473      Records = 0;
4474      NumRecords = 0;
4475    }
4476    virtual bool hasFeature(StringRef Feature) const {
4477      return Feature == "msp430";
4478    }
4479    virtual void getGCCRegNames(const char * const *&Names,
4480                                unsigned &NumNames) const;
4481    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4482                                  unsigned &NumAliases) const {
4483      // No aliases.
4484      Aliases = 0;
4485      NumAliases = 0;
4486    }
4487    virtual bool validateAsmConstraint(const char *&Name,
4488                                       TargetInfo::ConstraintInfo &info) const {
4489      // No target constraints for now.
4490      return false;
4491    }
4492    virtual const char *getClobbers() const {
4493      // FIXME: Is this really right?
4494      return "";
4495    }
4496    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4497      // FIXME: implement
4498      return TargetInfo::CharPtrBuiltinVaList;
4499   }
4500  };
4501
4502  const char * const MSP430TargetInfo::GCCRegNames[] = {
4503    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4504    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4505  };
4506
4507  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4508                                        unsigned &NumNames) const {
4509    Names = GCCRegNames;
4510    NumNames = llvm::array_lengthof(GCCRegNames);
4511  }
4512}
4513
4514namespace {
4515
4516  // LLVM and Clang cannot be used directly to output native binaries for
4517  // target, but is used to compile C code to llvm bitcode with correct
4518  // type and alignment information.
4519  //
4520  // TCE uses the llvm bitcode as input and uses it for generating customized
4521  // target processor and program binary. TCE co-design environment is
4522  // publicly available in http://tce.cs.tut.fi
4523
4524  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4525      3, // opencl_global
4526      4, // opencl_local
4527      5, // opencl_constant
4528      0, // cuda_device
4529      0, // cuda_constant
4530      0  // cuda_shared
4531  };
4532
4533  class TCETargetInfo : public TargetInfo{
4534  public:
4535    TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4536      TLSSupported = false;
4537      IntWidth = 32;
4538      LongWidth = LongLongWidth = 32;
4539      PointerWidth = 32;
4540      IntAlign = 32;
4541      LongAlign = LongLongAlign = 32;
4542      PointerAlign = 32;
4543      SuitableAlign = 32;
4544      SizeType = UnsignedInt;
4545      IntMaxType = SignedLong;
4546      UIntMaxType = UnsignedLong;
4547      IntPtrType = SignedInt;
4548      PtrDiffType = SignedInt;
4549      FloatWidth = 32;
4550      FloatAlign = 32;
4551      DoubleWidth = 32;
4552      DoubleAlign = 32;
4553      LongDoubleWidth = 32;
4554      LongDoubleAlign = 32;
4555      FloatFormat = &llvm::APFloat::IEEEsingle;
4556      DoubleFormat = &llvm::APFloat::IEEEsingle;
4557      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4558      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4559                          "i16:16:32-i32:32:32-i64:32:32-"
4560                          "f32:32:32-f64:32:32-v64:32:32-"
4561                          "v128:32:32-a0:0:32-n32";
4562      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4563    }
4564
4565    virtual void getTargetDefines(const LangOptions &Opts,
4566                                  MacroBuilder &Builder) const {
4567      DefineStd(Builder, "tce", Opts);
4568      Builder.defineMacro("__TCE__");
4569      Builder.defineMacro("__TCE_V1__");
4570    }
4571    virtual bool hasFeature(StringRef Feature) const {
4572      return Feature == "tce";
4573    }
4574
4575    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4576                                   unsigned &NumRecords) const {}
4577    virtual const char *getClobbers() const {
4578      return "";
4579    }
4580    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4581      return TargetInfo::VoidPtrBuiltinVaList;
4582    }
4583    virtual void getGCCRegNames(const char * const *&Names,
4584                                unsigned &NumNames) const {}
4585    virtual bool validateAsmConstraint(const char *&Name,
4586                                       TargetInfo::ConstraintInfo &info) const {
4587      return true;
4588    }
4589    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4590                                  unsigned &NumAliases) const {}
4591  };
4592}
4593
4594namespace {
4595class MipsTargetInfoBase : public TargetInfo {
4596  static const Builtin::Info BuiltinInfo[];
4597  std::string CPU;
4598  bool IsMips16;
4599  bool IsMicromips;
4600  bool IsSingleFloat;
4601  enum MipsFloatABI {
4602    HardFloat, SoftFloat
4603  } FloatABI;
4604  enum DspRevEnum {
4605    NoDSP, DSP1, DSP2
4606  } DspRev;
4607
4608protected:
4609  std::string ABI;
4610
4611public:
4612  MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4613                     const std::string &CPUStr)
4614      : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4615        IsSingleFloat(false), FloatABI(HardFloat), DspRev(NoDSP), ABI(ABIStr) {}
4616
4617  virtual const char *getABI() const { return ABI.c_str(); }
4618  virtual bool setABI(const std::string &Name) = 0;
4619  virtual bool setCPU(const std::string &Name) {
4620    CPU = Name;
4621    return true;
4622  }
4623  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4624    Features[ABI] = true;
4625    Features[CPU] = true;
4626  }
4627
4628  virtual void getTargetDefines(const LangOptions &Opts,
4629                                MacroBuilder &Builder) const {
4630    DefineStd(Builder, "mips", Opts);
4631    Builder.defineMacro("_mips");
4632    Builder.defineMacro("__REGISTER_PREFIX__", "");
4633
4634    switch (FloatABI) {
4635    case HardFloat:
4636      Builder.defineMacro("__mips_hard_float", Twine(1));
4637      break;
4638    case SoftFloat:
4639      Builder.defineMacro("__mips_soft_float", Twine(1));
4640      break;
4641    }
4642
4643    if (IsSingleFloat)
4644      Builder.defineMacro("__mips_single_float", Twine(1));
4645
4646    if (IsMips16)
4647      Builder.defineMacro("__mips16", Twine(1));
4648
4649    if (IsMicromips)
4650      Builder.defineMacro("__mips_micromips", Twine(1));
4651
4652    switch (DspRev) {
4653    default:
4654      break;
4655    case DSP1:
4656      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4657      Builder.defineMacro("__mips_dsp", Twine(1));
4658      break;
4659    case DSP2:
4660      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4661      Builder.defineMacro("__mips_dspr2", Twine(1));
4662      Builder.defineMacro("__mips_dsp", Twine(1));
4663      break;
4664    }
4665
4666    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4667    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4668    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4669
4670    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4671    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4672  }
4673
4674  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4675                                 unsigned &NumRecords) const {
4676    Records = BuiltinInfo;
4677    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4678  }
4679  virtual bool hasFeature(StringRef Feature) const {
4680    return Feature == "mips";
4681  }
4682  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4683    return TargetInfo::VoidPtrBuiltinVaList;
4684  }
4685  virtual void getGCCRegNames(const char * const *&Names,
4686                              unsigned &NumNames) const {
4687    static const char * const GCCRegNames[] = {
4688      // CPU register names
4689      // Must match second column of GCCRegAliases
4690      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4691      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4692      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4693      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4694      // Floating point register names
4695      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4696      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4697      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4698      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4699      // Hi/lo and condition register names
4700      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4701      "$fcc5","$fcc6","$fcc7"
4702    };
4703    Names = GCCRegNames;
4704    NumNames = llvm::array_lengthof(GCCRegNames);
4705  }
4706  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4707                                unsigned &NumAliases) const = 0;
4708  virtual bool validateAsmConstraint(const char *&Name,
4709                                     TargetInfo::ConstraintInfo &Info) const {
4710    switch (*Name) {
4711    default:
4712      return false;
4713
4714    case 'r': // CPU registers.
4715    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4716    case 'y': // Equivalent to "r", backwards compatibility only.
4717    case 'f': // floating-point registers.
4718    case 'c': // $25 for indirect jumps
4719    case 'l': // lo register
4720    case 'x': // hilo register pair
4721      Info.setAllowsRegister();
4722      return true;
4723    case 'R': // An address that can be used in a non-macro load or store
4724      Info.setAllowsMemory();
4725      return true;
4726    }
4727  }
4728
4729  virtual const char *getClobbers() const {
4730    // FIXME: Implement!
4731    return "";
4732  }
4733
4734  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4735                                 StringRef Name,
4736                                 bool Enabled) const {
4737    if (Name == "soft-float" || Name == "single-float" ||
4738        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4739        Name == "mips32" || Name == "mips32r2" ||
4740        Name == "mips64" || Name == "mips64r2" ||
4741        Name == "mips16" || Name == "micromips" ||
4742        Name == "dsp" || Name == "dspr2") {
4743      Features[Name] = Enabled;
4744      return true;
4745    } else if (Name == "32") {
4746      Features["o32"] = Enabled;
4747      return true;
4748    } else if (Name == "64") {
4749      Features["n64"] = Enabled;
4750      return true;
4751    }
4752    return false;
4753  }
4754
4755  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4756    IsMips16 = false;
4757    IsMicromips = false;
4758    IsSingleFloat = false;
4759    FloatABI = HardFloat;
4760    DspRev = NoDSP;
4761
4762    for (std::vector<std::string>::iterator it = Features.begin(),
4763         ie = Features.end(); it != ie; ++it) {
4764      if (*it == "+single-float")
4765        IsSingleFloat = true;
4766      else if (*it == "+soft-float")
4767        FloatABI = SoftFloat;
4768      else if (*it == "+mips16")
4769        IsMips16 = true;
4770      else if (*it == "+micromips")
4771        IsMicromips = true;
4772      else if (*it == "+dsp")
4773        DspRev = std::max(DspRev, DSP1);
4774      else if (*it == "+dspr2")
4775        DspRev = std::max(DspRev, DSP2);
4776    }
4777
4778    // Remove front-end specific option.
4779    std::vector<std::string>::iterator it =
4780      std::find(Features.begin(), Features.end(), "+soft-float");
4781    if (it != Features.end())
4782      Features.erase(it);
4783  }
4784
4785  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4786    if (RegNo == 0) return 4;
4787    if (RegNo == 1) return 5;
4788    return -1;
4789  }
4790};
4791
4792const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4793#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4794#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4795                                              ALL_LANGUAGES },
4796#include "clang/Basic/BuiltinsMips.def"
4797};
4798
4799class Mips32TargetInfoBase : public MipsTargetInfoBase {
4800public:
4801  Mips32TargetInfoBase(const llvm::Triple &Triple)
4802      : MipsTargetInfoBase(Triple, "o32", "mips32") {
4803    SizeType = UnsignedInt;
4804    PtrDiffType = SignedInt;
4805    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4806  }
4807  virtual bool setABI(const std::string &Name) {
4808    if ((Name == "o32") || (Name == "eabi")) {
4809      ABI = Name;
4810      return true;
4811    } else if (Name == "32") {
4812      ABI = "o32";
4813      return true;
4814    } else
4815      return false;
4816  }
4817  virtual void getTargetDefines(const LangOptions &Opts,
4818                                MacroBuilder &Builder) const {
4819    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4820
4821    if (ABI == "o32") {
4822      Builder.defineMacro("__mips_o32");
4823      Builder.defineMacro("_ABIO32", "1");
4824      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4825    }
4826    else if (ABI == "eabi")
4827      Builder.defineMacro("__mips_eabi");
4828    else
4829      llvm_unreachable("Invalid ABI for Mips32.");
4830  }
4831  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4832                                unsigned &NumAliases) const {
4833    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4834      { { "at" },  "$1" },
4835      { { "v0" },  "$2" },
4836      { { "v1" },  "$3" },
4837      { { "a0" },  "$4" },
4838      { { "a1" },  "$5" },
4839      { { "a2" },  "$6" },
4840      { { "a3" },  "$7" },
4841      { { "t0" },  "$8" },
4842      { { "t1" },  "$9" },
4843      { { "t2" }, "$10" },
4844      { { "t3" }, "$11" },
4845      { { "t4" }, "$12" },
4846      { { "t5" }, "$13" },
4847      { { "t6" }, "$14" },
4848      { { "t7" }, "$15" },
4849      { { "s0" }, "$16" },
4850      { { "s1" }, "$17" },
4851      { { "s2" }, "$18" },
4852      { { "s3" }, "$19" },
4853      { { "s4" }, "$20" },
4854      { { "s5" }, "$21" },
4855      { { "s6" }, "$22" },
4856      { { "s7" }, "$23" },
4857      { { "t8" }, "$24" },
4858      { { "t9" }, "$25" },
4859      { { "k0" }, "$26" },
4860      { { "k1" }, "$27" },
4861      { { "gp" }, "$28" },
4862      { { "sp","$sp" }, "$29" },
4863      { { "fp","$fp" }, "$30" },
4864      { { "ra" }, "$31" }
4865    };
4866    Aliases = GCCRegAliases;
4867    NumAliases = llvm::array_lengthof(GCCRegAliases);
4868  }
4869};
4870
4871class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4872public:
4873  Mips32EBTargetInfo(const llvm::Triple &Triple)
4874      : Mips32TargetInfoBase(Triple) {
4875    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4876                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4877  }
4878  virtual void getTargetDefines(const LangOptions &Opts,
4879                                MacroBuilder &Builder) const {
4880    DefineStd(Builder, "MIPSEB", Opts);
4881    Builder.defineMacro("_MIPSEB");
4882    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4883  }
4884};
4885
4886class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4887public:
4888  Mips32ELTargetInfo(const llvm::Triple &Triple)
4889      : Mips32TargetInfoBase(Triple) {
4890    BigEndian = false;
4891    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4892                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4893  }
4894  virtual void getTargetDefines(const LangOptions &Opts,
4895                                MacroBuilder &Builder) const {
4896    DefineStd(Builder, "MIPSEL", Opts);
4897    Builder.defineMacro("_MIPSEL");
4898    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4899  }
4900};
4901
4902class Mips64TargetInfoBase : public MipsTargetInfoBase {
4903  virtual void SetDescriptionString(const std::string &Name) = 0;
4904public:
4905  Mips64TargetInfoBase(const llvm::Triple &Triple)
4906      : MipsTargetInfoBase(Triple, "n64", "mips64") {
4907    LongWidth = LongAlign = 64;
4908    PointerWidth = PointerAlign = 64;
4909    LongDoubleWidth = LongDoubleAlign = 128;
4910    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4911    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4912      LongDoubleWidth = LongDoubleAlign = 64;
4913      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4914    }
4915    SuitableAlign = 128;
4916    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4917  }
4918  virtual bool setABI(const std::string &Name) {
4919    SetDescriptionString(Name);
4920    if (Name == "n32") {
4921      LongWidth = LongAlign = 32;
4922      PointerWidth = PointerAlign = 32;
4923      ABI = Name;
4924      return true;
4925    } else if (Name == "n64") {
4926      ABI = Name;
4927      return true;
4928    } else if (Name == "64") {
4929      ABI = "n64";
4930      return true;
4931    } else
4932      return false;
4933  }
4934  virtual void getTargetDefines(const LangOptions &Opts,
4935                                MacroBuilder &Builder) const {
4936    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4937
4938    Builder.defineMacro("__mips64");
4939    Builder.defineMacro("__mips64__");
4940
4941    if (ABI == "n32") {
4942      Builder.defineMacro("__mips_n32");
4943      Builder.defineMacro("_ABIN32", "2");
4944      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4945    }
4946    else if (ABI == "n64") {
4947      Builder.defineMacro("__mips_n64");
4948      Builder.defineMacro("_ABI64", "3");
4949      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4950    }
4951    else
4952      llvm_unreachable("Invalid ABI for Mips64.");
4953  }
4954  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4955                                unsigned &NumAliases) const {
4956    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4957      { { "at" },  "$1" },
4958      { { "v0" },  "$2" },
4959      { { "v1" },  "$3" },
4960      { { "a0" },  "$4" },
4961      { { "a1" },  "$5" },
4962      { { "a2" },  "$6" },
4963      { { "a3" },  "$7" },
4964      { { "a4" },  "$8" },
4965      { { "a5" },  "$9" },
4966      { { "a6" }, "$10" },
4967      { { "a7" }, "$11" },
4968      { { "t0" }, "$12" },
4969      { { "t1" }, "$13" },
4970      { { "t2" }, "$14" },
4971      { { "t3" }, "$15" },
4972      { { "s0" }, "$16" },
4973      { { "s1" }, "$17" },
4974      { { "s2" }, "$18" },
4975      { { "s3" }, "$19" },
4976      { { "s4" }, "$20" },
4977      { { "s5" }, "$21" },
4978      { { "s6" }, "$22" },
4979      { { "s7" }, "$23" },
4980      { { "t8" }, "$24" },
4981      { { "t9" }, "$25" },
4982      { { "k0" }, "$26" },
4983      { { "k1" }, "$27" },
4984      { { "gp" }, "$28" },
4985      { { "sp","$sp" }, "$29" },
4986      { { "fp","$fp" }, "$30" },
4987      { { "ra" }, "$31" }
4988    };
4989    Aliases = GCCRegAliases;
4990    NumAliases = llvm::array_lengthof(GCCRegAliases);
4991  }
4992};
4993
4994class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4995  virtual void SetDescriptionString(const std::string &Name) {
4996    // Change DescriptionString only if ABI is n32.
4997    if (Name == "n32")
4998      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4999                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5000                          "v64:64:64-n32:64-S128";
5001  }
5002public:
5003  Mips64EBTargetInfo(const llvm::Triple &Triple)
5004      : Mips64TargetInfoBase(Triple) {
5005    // Default ABI is n64.
5006    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5007                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5008                        "v64:64:64-n32:64-S128";
5009  }
5010  virtual void getTargetDefines(const LangOptions &Opts,
5011                                MacroBuilder &Builder) const {
5012    DefineStd(Builder, "MIPSEB", Opts);
5013    Builder.defineMacro("_MIPSEB");
5014    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5015  }
5016};
5017
5018class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5019  virtual void SetDescriptionString(const std::string &Name) {
5020    // Change DescriptionString only if ABI is n32.
5021    if (Name == "n32")
5022      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5023                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5024                          "-v64:64:64-n32:64-S128";
5025  }
5026public:
5027  Mips64ELTargetInfo(const llvm::Triple &Triple)
5028      : Mips64TargetInfoBase(Triple) {
5029    // Default ABI is n64.
5030    BigEndian = false;
5031    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5032                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5033                        "v64:64:64-n32:64-S128";
5034  }
5035  virtual void getTargetDefines(const LangOptions &Opts,
5036                                MacroBuilder &Builder) const {
5037    DefineStd(Builder, "MIPSEL", Opts);
5038    Builder.defineMacro("_MIPSEL");
5039    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5040  }
5041};
5042} // end anonymous namespace.
5043
5044namespace {
5045class PNaClTargetInfo : public TargetInfo {
5046public:
5047  PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5048    BigEndian = false;
5049    this->UserLabelPrefix = "";
5050    this->LongAlign = 32;
5051    this->LongWidth = 32;
5052    this->PointerAlign = 32;
5053    this->PointerWidth = 32;
5054    this->IntMaxType = TargetInfo::SignedLongLong;
5055    this->UIntMaxType = TargetInfo::UnsignedLongLong;
5056    this->Int64Type = TargetInfo::SignedLongLong;
5057    this->DoubleAlign = 64;
5058    this->LongDoubleWidth = 64;
5059    this->LongDoubleAlign = 64;
5060    this->SizeType = TargetInfo::UnsignedInt;
5061    this->PtrDiffType = TargetInfo::SignedInt;
5062    this->IntPtrType = TargetInfo::SignedInt;
5063    this->RegParmMax = 0; // Disallow regparm
5064    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5065                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5066  }
5067
5068  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5069  }
5070  virtual void getArchDefines(const LangOptions &Opts,
5071                              MacroBuilder &Builder) const {
5072    Builder.defineMacro("__le32__");
5073    Builder.defineMacro("__pnacl__");
5074  }
5075  virtual void getTargetDefines(const LangOptions &Opts,
5076                                MacroBuilder &Builder) const {
5077    Builder.defineMacro("__LITTLE_ENDIAN__");
5078    getArchDefines(Opts, Builder);
5079  }
5080  virtual bool hasFeature(StringRef Feature) const {
5081    return Feature == "pnacl";
5082  }
5083  virtual void getTargetBuiltins(const Builtin::Info *&Records,
5084                                 unsigned &NumRecords) const {
5085  }
5086  virtual BuiltinVaListKind getBuiltinVaListKind() const {
5087    return TargetInfo::PNaClABIBuiltinVaList;
5088  }
5089  virtual void getGCCRegNames(const char * const *&Names,
5090                              unsigned &NumNames) const;
5091  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5092                                unsigned &NumAliases) const;
5093  virtual bool validateAsmConstraint(const char *&Name,
5094                                     TargetInfo::ConstraintInfo &Info) const {
5095    return false;
5096  }
5097
5098  virtual const char *getClobbers() const {
5099    return "";
5100  }
5101};
5102
5103void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5104                                     unsigned &NumNames) const {
5105  Names = NULL;
5106  NumNames = 0;
5107}
5108
5109void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5110                                       unsigned &NumAliases) const {
5111  Aliases = NULL;
5112  NumAliases = 0;
5113}
5114} // end anonymous namespace.
5115
5116namespace {
5117  static const unsigned SPIRAddrSpaceMap[] = {
5118    1,    // opencl_global
5119    3,    // opencl_local
5120    2,    // opencl_constant
5121    0,    // cuda_device
5122    0,    // cuda_constant
5123    0     // cuda_shared
5124  };
5125  class SPIRTargetInfo : public TargetInfo {
5126    static const char * const GCCRegNames[];
5127    static const Builtin::Info BuiltinInfo[];
5128    std::vector<StringRef> AvailableFeatures;
5129  public:
5130    SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5131      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5132        "SPIR target must use unknown OS");
5133      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5134        "SPIR target must use unknown environment type");
5135      BigEndian = false;
5136      TLSSupported = false;
5137      LongWidth = LongAlign = 64;
5138      AddrSpaceMap = &SPIRAddrSpaceMap;
5139      // Define available target features
5140      // These must be defined in sorted order!
5141      NoAsmVariants = true;
5142    }
5143    virtual void getTargetDefines(const LangOptions &Opts,
5144                                  MacroBuilder &Builder) const {
5145      DefineStd(Builder, "SPIR", Opts);
5146    }
5147    virtual bool hasFeature(StringRef Feature) const {
5148      return Feature == "spir";
5149    }
5150
5151    virtual void getTargetBuiltins(const Builtin::Info *&Records,
5152                                   unsigned &NumRecords) const {}
5153    virtual const char *getClobbers() const {
5154      return "";
5155    }
5156    virtual void getGCCRegNames(const char * const *&Names,
5157                                unsigned &NumNames) const {}
5158    virtual bool validateAsmConstraint(const char *&Name,
5159                                       TargetInfo::ConstraintInfo &info) const {
5160      return true;
5161    }
5162    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5163                                  unsigned &NumAliases) const {}
5164    virtual BuiltinVaListKind getBuiltinVaListKind() const {
5165      return TargetInfo::VoidPtrBuiltinVaList;
5166    }
5167  };
5168
5169
5170  class SPIR32TargetInfo : public SPIRTargetInfo {
5171  public:
5172    SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5173      PointerWidth = PointerAlign = 32;
5174      SizeType     = TargetInfo::UnsignedInt;
5175      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5176      DescriptionString
5177        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5178          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5179          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5180          "v512:512:512-v1024:1024:1024";
5181    }
5182    virtual void getTargetDefines(const LangOptions &Opts,
5183                                  MacroBuilder &Builder) const {
5184      DefineStd(Builder, "SPIR32", Opts);
5185    }
5186  };
5187
5188  class SPIR64TargetInfo : public SPIRTargetInfo {
5189  public:
5190    SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5191      PointerWidth = PointerAlign = 64;
5192      SizeType     = TargetInfo::UnsignedLong;
5193      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5194      DescriptionString
5195        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5196          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5197          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5198          "v512:512:512-v1024:1024:1024";
5199    }
5200    virtual void getTargetDefines(const LangOptions &Opts,
5201                                  MacroBuilder &Builder) const {
5202      DefineStd(Builder, "SPIR64", Opts);
5203    }
5204  };
5205}
5206
5207
5208//===----------------------------------------------------------------------===//
5209// Driver code
5210//===----------------------------------------------------------------------===//
5211
5212static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5213  llvm::Triple::OSType os = Triple.getOS();
5214
5215  switch (Triple.getArch()) {
5216  default:
5217    return NULL;
5218
5219  case llvm::Triple::hexagon:
5220    return new HexagonTargetInfo(Triple);
5221
5222  case llvm::Triple::aarch64:
5223    switch (os) {
5224    case llvm::Triple::Linux:
5225      return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5226    default:
5227      return new AArch64TargetInfo(Triple);
5228    }
5229
5230  case llvm::Triple::arm:
5231  case llvm::Triple::thumb:
5232    if (Triple.isOSDarwin())
5233      return new DarwinARMTargetInfo(Triple);
5234
5235    switch (os) {
5236    case llvm::Triple::Linux:
5237      return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5238    case llvm::Triple::FreeBSD:
5239      return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5240    case llvm::Triple::NetBSD:
5241      return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5242    case llvm::Triple::OpenBSD:
5243      return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5244    case llvm::Triple::Bitrig:
5245      return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5246    case llvm::Triple::RTEMS:
5247      return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5248    case llvm::Triple::NaCl:
5249      return new NaClTargetInfo<ARMTargetInfo>(Triple);
5250    default:
5251      return new ARMTargetInfo(Triple);
5252    }
5253
5254  case llvm::Triple::msp430:
5255    return new MSP430TargetInfo(Triple);
5256
5257  case llvm::Triple::mips:
5258    switch (os) {
5259    case llvm::Triple::Linux:
5260      return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5261    case llvm::Triple::RTEMS:
5262      return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5263    case llvm::Triple::FreeBSD:
5264      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5265    case llvm::Triple::NetBSD:
5266      return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5267    default:
5268      return new Mips32EBTargetInfo(Triple);
5269    }
5270
5271  case llvm::Triple::mipsel:
5272    switch (os) {
5273    case llvm::Triple::Linux:
5274      return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5275    case llvm::Triple::RTEMS:
5276      return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5277    case llvm::Triple::FreeBSD:
5278      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5279    case llvm::Triple::NetBSD:
5280      return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5281    default:
5282      return new Mips32ELTargetInfo(Triple);
5283    }
5284
5285  case llvm::Triple::mips64:
5286    switch (os) {
5287    case llvm::Triple::Linux:
5288      return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5289    case llvm::Triple::RTEMS:
5290      return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5291    case llvm::Triple::FreeBSD:
5292      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5293    case llvm::Triple::NetBSD:
5294      return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5295    case llvm::Triple::OpenBSD:
5296      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5297    default:
5298      return new Mips64EBTargetInfo(Triple);
5299    }
5300
5301  case llvm::Triple::mips64el:
5302    switch (os) {
5303    case llvm::Triple::Linux:
5304      return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5305    case llvm::Triple::RTEMS:
5306      return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5307    case llvm::Triple::FreeBSD:
5308      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5309    case llvm::Triple::NetBSD:
5310      return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5311    case llvm::Triple::OpenBSD:
5312      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5313    default:
5314      return new Mips64ELTargetInfo(Triple);
5315    }
5316
5317  case llvm::Triple::le32:
5318    switch (os) {
5319      case llvm::Triple::NaCl:
5320        return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5321      default:
5322        return NULL;
5323    }
5324
5325  case llvm::Triple::ppc:
5326    if (Triple.isOSDarwin())
5327      return new DarwinPPC32TargetInfo(Triple);
5328    switch (os) {
5329    case llvm::Triple::Linux:
5330      return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5331    case llvm::Triple::FreeBSD:
5332      return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5333    case llvm::Triple::NetBSD:
5334      return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5335    case llvm::Triple::OpenBSD:
5336      return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5337    case llvm::Triple::RTEMS:
5338      return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5339    default:
5340      return new PPC32TargetInfo(Triple);
5341    }
5342
5343  case llvm::Triple::ppc64:
5344    if (Triple.isOSDarwin())
5345      return new DarwinPPC64TargetInfo(Triple);
5346    switch (os) {
5347    case llvm::Triple::Linux:
5348      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5349    case llvm::Triple::Lv2:
5350      return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5351    case llvm::Triple::FreeBSD:
5352      return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5353    case llvm::Triple::NetBSD:
5354      return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5355    default:
5356      return new PPC64TargetInfo(Triple);
5357    }
5358
5359  case llvm::Triple::nvptx:
5360    return new NVPTX32TargetInfo(Triple);
5361  case llvm::Triple::nvptx64:
5362    return new NVPTX64TargetInfo(Triple);
5363
5364  case llvm::Triple::mblaze:
5365    return new MBlazeTargetInfo(Triple);
5366
5367  case llvm::Triple::r600:
5368    return new R600TargetInfo(Triple);
5369
5370  case llvm::Triple::sparc:
5371    switch (os) {
5372    case llvm::Triple::Linux:
5373      return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5374    case llvm::Triple::AuroraUX:
5375      return new AuroraUXSparcV8TargetInfo(Triple);
5376    case llvm::Triple::Solaris:
5377      return new SolarisSparcV8TargetInfo(Triple);
5378    case llvm::Triple::NetBSD:
5379      return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5380    case llvm::Triple::OpenBSD:
5381      return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5382    case llvm::Triple::RTEMS:
5383      return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5384    default:
5385      return new SparcV8TargetInfo(Triple);
5386    }
5387
5388  case llvm::Triple::sparcv9:
5389    switch (os) {
5390    case llvm::Triple::Linux:
5391      return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5392    case llvm::Triple::AuroraUX:
5393      return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5394    case llvm::Triple::Solaris:
5395      return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5396    case llvm::Triple::NetBSD:
5397      return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5398    case llvm::Triple::OpenBSD:
5399      return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5400    case llvm::Triple::FreeBSD:
5401      return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5402    default:
5403      return new SparcV9TargetInfo(Triple);
5404    }
5405
5406  case llvm::Triple::systemz:
5407    switch (os) {
5408    case llvm::Triple::Linux:
5409      return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5410    default:
5411      return new SystemZTargetInfo(Triple);
5412    }
5413
5414  case llvm::Triple::tce:
5415    return new TCETargetInfo(Triple);
5416
5417  case llvm::Triple::x86:
5418    if (Triple.isOSDarwin())
5419      return new DarwinI386TargetInfo(Triple);
5420
5421    switch (os) {
5422    case llvm::Triple::AuroraUX:
5423      return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5424    case llvm::Triple::Linux:
5425      return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5426    case llvm::Triple::DragonFly:
5427      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5428    case llvm::Triple::NetBSD:
5429      return new NetBSDI386TargetInfo(Triple);
5430    case llvm::Triple::OpenBSD:
5431      return new OpenBSDI386TargetInfo(Triple);
5432    case llvm::Triple::Bitrig:
5433      return new BitrigI386TargetInfo(Triple);
5434    case llvm::Triple::FreeBSD:
5435      return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5436    case llvm::Triple::Minix:
5437      return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5438    case llvm::Triple::Solaris:
5439      return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5440    case llvm::Triple::Cygwin:
5441      return new CygwinX86_32TargetInfo(Triple);
5442    case llvm::Triple::MinGW32:
5443      return new MinGWX86_32TargetInfo(Triple);
5444    case llvm::Triple::Win32:
5445      return new VisualStudioWindowsX86_32TargetInfo(Triple);
5446    case llvm::Triple::Haiku:
5447      return new HaikuX86_32TargetInfo(Triple);
5448    case llvm::Triple::RTEMS:
5449      return new RTEMSX86_32TargetInfo(Triple);
5450    case llvm::Triple::NaCl:
5451      return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5452    default:
5453      return new X86_32TargetInfo(Triple);
5454    }
5455
5456  case llvm::Triple::x86_64:
5457    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5458      return new DarwinX86_64TargetInfo(Triple);
5459
5460    switch (os) {
5461    case llvm::Triple::AuroraUX:
5462      return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5463    case llvm::Triple::Linux:
5464      return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5465    case llvm::Triple::DragonFly:
5466      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5467    case llvm::Triple::NetBSD:
5468      return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5469    case llvm::Triple::OpenBSD:
5470      return new OpenBSDX86_64TargetInfo(Triple);
5471    case llvm::Triple::Bitrig:
5472      return new BitrigX86_64TargetInfo(Triple);
5473    case llvm::Triple::FreeBSD:
5474      return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5475    case llvm::Triple::Solaris:
5476      return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5477    case llvm::Triple::MinGW32:
5478      return new MinGWX86_64TargetInfo(Triple);
5479    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5480      return new VisualStudioWindowsX86_64TargetInfo(Triple);
5481    case llvm::Triple::NaCl:
5482      return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5483    default:
5484      return new X86_64TargetInfo(Triple);
5485    }
5486
5487    case llvm::Triple::spir: {
5488      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5489          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5490        return NULL;
5491      return new SPIR32TargetInfo(Triple);
5492    }
5493    case llvm::Triple::spir64: {
5494      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5495          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5496        return NULL;
5497      return new SPIR64TargetInfo(Triple);
5498    }
5499  }
5500}
5501
5502/// CreateTargetInfo - Return the target info object for the specified target
5503/// triple.
5504TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5505                                         TargetOptions *Opts) {
5506  llvm::Triple Triple(Opts->Triple);
5507
5508  // Construct the target
5509  OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5510  if (!Target) {
5511    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5512    return 0;
5513  }
5514  Target->setTargetOpts(Opts);
5515
5516  // Set the target CPU if specified.
5517  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5518    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5519    return 0;
5520  }
5521
5522  // Set the target ABI if specified.
5523  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5524    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5525    return 0;
5526  }
5527
5528  // Set the target C++ ABI.
5529  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5530    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5531    return 0;
5532  }
5533
5534  // Compute the default target features, we need the target to handle this
5535  // because features may have dependencies on one another.
5536  llvm::StringMap<bool> Features;
5537  Target->getDefaultFeatures(Features);
5538
5539  // Apply the user specified deltas.
5540  // First the enables.
5541  for (std::vector<std::string>::const_iterator
5542         it = Opts->FeaturesAsWritten.begin(),
5543         ie = Opts->FeaturesAsWritten.end();
5544       it != ie; ++it) {
5545    const char *Name = it->c_str();
5546
5547    if (Name[0] != '+')
5548      continue;
5549
5550    // Apply the feature via the target.
5551    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5552      Diags.Report(diag::err_target_invalid_feature) << Name;
5553      return 0;
5554    }
5555  }
5556
5557  // Then the disables.
5558  for (std::vector<std::string>::const_iterator
5559         it = Opts->FeaturesAsWritten.begin(),
5560         ie = Opts->FeaturesAsWritten.end();
5561       it != ie; ++it) {
5562    const char *Name = it->c_str();
5563
5564    if (Name[0] == '+')
5565      continue;
5566
5567    // Apply the feature via the target.
5568    if (Name[0] != '-' ||
5569        !Target->setFeatureEnabled(Features, Name + 1, false)) {
5570      Diags.Report(diag::err_target_invalid_feature) << Name;
5571      return 0;
5572    }
5573  }
5574
5575  // Add the features to the compile options.
5576  //
5577  // FIXME: If we are completely confident that we have the right set, we only
5578  // need to pass the minuses.
5579  Opts->Features.clear();
5580  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5581         ie = Features.end(); it != ie; ++it)
5582    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5583  Target->HandleTargetFeatures(Opts->Features);
5584
5585  return Target.take();
5586}
5587