Targets.cpp revision babaf31d401310464db93627ef6b195a7ffb1029 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/MC/MCSectionMachO.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Type.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "5621");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.AddressSanitizer) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.getOS() == llvm::Triple::IOS) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const std::string& triple) :
183    OSTargetInfo<Target>(triple) {
184      llvm::Triple T = llvm::Triple(triple);
185      this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186      this->MCountName = "\01mcount";
187    }
188
189  virtual std::string isValidSectionSpecifier(StringRef SR) const {
190    // Let MCSectionMachO validate this.
191    StringRef Segment, Section;
192    unsigned TAA, StubSize;
193    bool HasTAA;
194    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                       TAA, HasTAA, StubSize);
196  }
197
198  virtual const char *getStaticInitSectionSpecifier() const {
199    // FIXME: We should return 0 when building kexts.
200    return "__TEXT,__StaticInit,regular,pure_instructions";
201  }
202
203  /// Darwin does not support protected visibility.  Darwin's "default"
204  /// is very similar to ELF's "protected";  Darwin requires a "weak"
205  /// attribute on declarations that can be dynamically replaced.
206  virtual bool hasProtectedVisibility() const {
207    return false;
208  }
209};
210
211
212// DragonFlyBSD Target
213template<typename Target>
214class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215protected:
216  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                            MacroBuilder &Builder) const {
218    // DragonFly defines; list based off of gcc output
219    Builder.defineMacro("__DragonFly__");
220    Builder.defineMacro("__DragonFly_cc_version", "100001");
221    Builder.defineMacro("__ELF__");
222    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223    Builder.defineMacro("__tune_i386__");
224    DefineStd(Builder, "unix", Opts);
225  }
226public:
227  DragonFlyBSDTargetInfo(const std::string &triple)
228    : OSTargetInfo<Target>(triple) {
229      this->UserLabelPrefix = "";
230
231      llvm::Triple Triple(triple);
232      switch (Triple.getArch()) {
233        default:
234        case llvm::Triple::x86:
235        case llvm::Triple::x86_64:
236          this->MCountName = ".mcount";
237          break;
238      }
239  }
240};
241
242// FreeBSD Target
243template<typename Target>
244class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245protected:
246  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                            MacroBuilder &Builder) const {
248    // FreeBSD defines; list based off of gcc output
249
250    unsigned Release = Triple.getOSMajorVersion();
251    if (Release == 0U)
252      Release = 8;
253
254    Builder.defineMacro("__FreeBSD__", Twine(Release));
255    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257    DefineStd(Builder, "unix", Opts);
258    Builder.defineMacro("__ELF__");
259  }
260public:
261  FreeBSDTargetInfo(const std::string &triple)
262    : OSTargetInfo<Target>(triple) {
263      this->UserLabelPrefix = "";
264
265      llvm::Triple Triple(triple);
266      switch (Triple.getArch()) {
267        default:
268        case llvm::Triple::x86:
269        case llvm::Triple::x86_64:
270          this->MCountName = ".mcount";
271          break;
272        case llvm::Triple::mips:
273        case llvm::Triple::mipsel:
274        case llvm::Triple::ppc:
275        case llvm::Triple::ppc64:
276          this->MCountName = "_mcount";
277          break;
278        case llvm::Triple::arm:
279          this->MCountName = "__mcount";
280          break;
281      }
282
283    }
284};
285
286// Minix Target
287template<typename Target>
288class MinixTargetInfo : public OSTargetInfo<Target> {
289protected:
290  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                            MacroBuilder &Builder) const {
292    // Minix defines
293
294    Builder.defineMacro("__minix", "3");
295    Builder.defineMacro("_EM_WSIZE", "4");
296    Builder.defineMacro("_EM_PSIZE", "4");
297    Builder.defineMacro("_EM_SSIZE", "2");
298    Builder.defineMacro("_EM_LSIZE", "4");
299    Builder.defineMacro("_EM_FSIZE", "4");
300    Builder.defineMacro("_EM_DSIZE", "8");
301    Builder.defineMacro("__ELF__");
302    DefineStd(Builder, "unix", Opts);
303  }
304public:
305  MinixTargetInfo(const std::string &triple)
306    : OSTargetInfo<Target>(triple) {
307      this->UserLabelPrefix = "";
308    }
309};
310
311// Linux target
312template<typename Target>
313class LinuxTargetInfo : public OSTargetInfo<Target> {
314protected:
315  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                            MacroBuilder &Builder) const {
317    // Linux defines; list based off of gcc output
318    DefineStd(Builder, "unix", Opts);
319    DefineStd(Builder, "linux", Opts);
320    Builder.defineMacro("__gnu_linux__");
321    Builder.defineMacro("__ELF__");
322    if (Triple.getEnvironment() == llvm::Triple::Android)
323      Builder.defineMacro("__ANDROID__", "1");
324    if (Opts.POSIXThreads)
325      Builder.defineMacro("_REENTRANT");
326    if (Opts.CPlusPlus)
327      Builder.defineMacro("_GNU_SOURCE");
328  }
329public:
330  LinuxTargetInfo(const std::string& triple)
331    : OSTargetInfo<Target>(triple) {
332    this->UserLabelPrefix = "";
333    this->WIntType = TargetInfo::UnsignedInt;
334  }
335
336  virtual const char *getStaticInitSectionSpecifier() const {
337    return ".text.startup";
338  }
339};
340
341// NetBSD Target
342template<typename Target>
343class NetBSDTargetInfo : public OSTargetInfo<Target> {
344protected:
345  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                            MacroBuilder &Builder) const {
347    // NetBSD defines; list based off of gcc output
348    Builder.defineMacro("__NetBSD__");
349    Builder.defineMacro("__unix__");
350    Builder.defineMacro("__ELF__");
351    if (Opts.POSIXThreads)
352      Builder.defineMacro("_POSIX_THREADS");
353  }
354public:
355  NetBSDTargetInfo(const std::string &triple)
356    : OSTargetInfo<Target>(triple) {
357      this->UserLabelPrefix = "";
358    }
359};
360
361// OpenBSD Target
362template<typename Target>
363class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364protected:
365  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                            MacroBuilder &Builder) const {
367    // OpenBSD defines; list based off of gcc output
368
369    Builder.defineMacro("__OpenBSD__");
370    DefineStd(Builder, "unix", Opts);
371    Builder.defineMacro("__ELF__");
372    if (Opts.POSIXThreads)
373      Builder.defineMacro("_REENTRANT");
374  }
375public:
376  OpenBSDTargetInfo(const std::string &triple)
377    : OSTargetInfo<Target>(triple) {
378      this->UserLabelPrefix = "";
379      this->TLSSupported = false;
380
381      llvm::Triple Triple(triple);
382      switch (Triple.getArch()) {
383        default:
384        case llvm::Triple::x86:
385        case llvm::Triple::x86_64:
386        case llvm::Triple::arm:
387	case llvm::Triple::sparc:
388          this->MCountName = "__mcount";
389          break;
390        case llvm::Triple::mips64:
391        case llvm::Triple::mips64el:
392        case llvm::Triple::ppc:
393	case llvm::Triple::sparcv9:
394          this->MCountName = "_mcount";
395          break;
396      }
397  }
398};
399
400// Bitrig Target
401template<typename Target>
402class BitrigTargetInfo : public OSTargetInfo<Target> {
403protected:
404  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                            MacroBuilder &Builder) const {
406    // Bitrig defines; list based off of gcc output
407
408    Builder.defineMacro("__Bitrig__");
409    DefineStd(Builder, "unix", Opts);
410    Builder.defineMacro("__ELF__");
411    if (Opts.POSIXThreads)
412      Builder.defineMacro("_REENTRANT");
413  }
414public:
415  BitrigTargetInfo(const std::string &triple)
416    : OSTargetInfo<Target>(triple) {
417      this->UserLabelPrefix = "";
418      this->TLSSupported = false;
419      this->MCountName = "__mcount";
420  }
421};
422
423// PSP Target
424template<typename Target>
425class PSPTargetInfo : public OSTargetInfo<Target> {
426protected:
427  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                            MacroBuilder &Builder) const {
429    // PSP defines; list based on the output of the pspdev gcc toolchain.
430    Builder.defineMacro("PSP");
431    Builder.defineMacro("_PSP");
432    Builder.defineMacro("__psp__");
433    Builder.defineMacro("__ELF__");
434  }
435public:
436  PSPTargetInfo(const std::string& triple)
437    : OSTargetInfo<Target>(triple) {
438    this->UserLabelPrefix = "";
439  }
440};
441
442// PS3 PPU Target
443template<typename Target>
444class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445protected:
446  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                            MacroBuilder &Builder) const {
448    // PS3 PPU defines.
449    Builder.defineMacro("__PPC__");
450    Builder.defineMacro("__PPU__");
451    Builder.defineMacro("__CELLOS_LV2__");
452    Builder.defineMacro("__ELF__");
453    Builder.defineMacro("__LP32__");
454    Builder.defineMacro("_ARCH_PPC64");
455    Builder.defineMacro("__powerpc64__");
456  }
457public:
458  PS3PPUTargetInfo(const std::string& triple)
459    : OSTargetInfo<Target>(triple) {
460    this->UserLabelPrefix = "";
461    this->LongWidth = this->LongAlign = 32;
462    this->PointerWidth = this->PointerAlign = 32;
463    this->IntMaxType = TargetInfo::SignedLongLong;
464    this->UIntMaxType = TargetInfo::UnsignedLongLong;
465    this->Int64Type = TargetInfo::SignedLongLong;
466    this->SizeType = TargetInfo::UnsignedInt;
467    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469  }
470};
471
472// FIXME: Need a real SPU target.
473// PS3 SPU Target
474template<typename Target>
475class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476protected:
477  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                            MacroBuilder &Builder) const {
479    // PS3 PPU defines.
480    Builder.defineMacro("__SPU__");
481    Builder.defineMacro("__ELF__");
482  }
483public:
484  PS3SPUTargetInfo(const std::string& triple)
485    : OSTargetInfo<Target>(triple) {
486    this->UserLabelPrefix = "";
487  }
488};
489
490// AuroraUX target
491template<typename Target>
492class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493protected:
494  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                            MacroBuilder &Builder) const {
496    DefineStd(Builder, "sun", Opts);
497    DefineStd(Builder, "unix", Opts);
498    Builder.defineMacro("__ELF__");
499    Builder.defineMacro("__svr4__");
500    Builder.defineMacro("__SVR4");
501  }
502public:
503  AuroraUXTargetInfo(const std::string& triple)
504    : OSTargetInfo<Target>(triple) {
505    this->UserLabelPrefix = "";
506    this->WCharType = this->SignedLong;
507    // FIXME: WIntType should be SignedLong
508  }
509};
510
511// Solaris target
512template<typename Target>
513class SolarisTargetInfo : public OSTargetInfo<Target> {
514protected:
515  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                            MacroBuilder &Builder) const {
517    DefineStd(Builder, "sun", Opts);
518    DefineStd(Builder, "unix", Opts);
519    Builder.defineMacro("__ELF__");
520    Builder.defineMacro("__svr4__");
521    Builder.defineMacro("__SVR4");
522    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523    // newer, but to 500 for everything else.  feature_test.h has a check to
524    // ensure that you are not using C99 with an old version of X/Open or C89
525    // with a new version.
526    if (Opts.C99 || Opts.C11)
527      Builder.defineMacro("_XOPEN_SOURCE", "600");
528    else
529      Builder.defineMacro("_XOPEN_SOURCE", "500");
530    if (Opts.CPlusPlus)
531      Builder.defineMacro("__C99FEATURES__");
532    Builder.defineMacro("_LARGEFILE_SOURCE");
533    Builder.defineMacro("_LARGEFILE64_SOURCE");
534    Builder.defineMacro("__EXTENSIONS__");
535    Builder.defineMacro("_REENTRANT");
536  }
537public:
538  SolarisTargetInfo(const std::string& triple)
539    : OSTargetInfo<Target>(triple) {
540    this->UserLabelPrefix = "";
541    this->WCharType = this->SignedInt;
542    // FIXME: WIntType should be SignedLong
543  }
544};
545
546// Windows target
547template<typename Target>
548class WindowsTargetInfo : public OSTargetInfo<Target> {
549protected:
550  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                            MacroBuilder &Builder) const {
552    Builder.defineMacro("_WIN32");
553  }
554  void getVisualStudioDefines(const LangOptions &Opts,
555                              MacroBuilder &Builder) const {
556    if (Opts.CPlusPlus) {
557      if (Opts.RTTI)
558        Builder.defineMacro("_CPPRTTI");
559
560      if (Opts.Exceptions)
561        Builder.defineMacro("_CPPUNWIND");
562    }
563
564    if (!Opts.CharIsSigned)
565      Builder.defineMacro("_CHAR_UNSIGNED");
566
567    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568    //        but it works for now.
569    if (Opts.POSIXThreads)
570      Builder.defineMacro("_MT");
571
572    if (Opts.MSCVersion != 0)
573      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574
575    if (Opts.MicrosoftExt) {
576      Builder.defineMacro("_MSC_EXTENSIONS");
577
578      if (Opts.CPlusPlus0x) {
579        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582      }
583    }
584
585    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586  }
587
588public:
589  WindowsTargetInfo(const std::string &triple)
590    : OSTargetInfo<Target>(triple) {}
591};
592
593} // end anonymous namespace.
594
595//===----------------------------------------------------------------------===//
596// Specific target implementations.
597//===----------------------------------------------------------------------===//
598
599namespace {
600// PPC abstract base class
601class PPCTargetInfo : public TargetInfo {
602  static const Builtin::Info BuiltinInfo[];
603  static const char * const GCCRegNames[];
604  static const TargetInfo::GCCRegAlias GCCRegAliases[];
605  std::string CPU;
606public:
607  PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
608    LongDoubleWidth = LongDoubleAlign = 128;
609    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
610  }
611
612  /// \brief Flags for architecture specific defines.
613  typedef enum {
614    ArchDefineNone  = 0,
615    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
616    ArchDefinePpcgr = 1 << 1,
617    ArchDefinePpcsq = 1 << 2,
618    ArchDefine440   = 1 << 3,
619    ArchDefine603   = 1 << 4,
620    ArchDefine604   = 1 << 5,
621    ArchDefinePwr4  = 1 << 6,
622    ArchDefinePwr6  = 1 << 7
623  } ArchDefineTypes;
624
625  virtual bool setCPU(const std::string &Name) {
626    bool CPUKnown = llvm::StringSwitch<bool>(Name)
627      .Case("generic", true)
628      .Case("440", true)
629      .Case("450", true)
630      .Case("601", true)
631      .Case("602", true)
632      .Case("603", true)
633      .Case("603e", true)
634      .Case("603ev", true)
635      .Case("604", true)
636      .Case("604e", true)
637      .Case("620", true)
638      .Case("g3", true)
639      .Case("7400", true)
640      .Case("g4", true)
641      .Case("7450", true)
642      .Case("g4+", true)
643      .Case("750", true)
644      .Case("970", true)
645      .Case("g5", true)
646      .Case("a2", true)
647      .Case("e500mc", true)
648      .Case("e5500", true)
649      .Case("pwr6", true)
650      .Case("pwr7", true)
651      .Case("ppc", true)
652      .Case("ppc64", true)
653      .Default(false);
654
655    if (CPUKnown)
656      CPU = Name;
657
658    return CPUKnown;
659  }
660
661  virtual void getTargetBuiltins(const Builtin::Info *&Records,
662                                 unsigned &NumRecords) const {
663    Records = BuiltinInfo;
664    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
665  }
666
667  virtual bool isCLZForZeroUndef() const { return false; }
668
669  virtual void getTargetDefines(const LangOptions &Opts,
670                                MacroBuilder &Builder) const;
671
672  virtual bool hasFeature(StringRef Feature) const;
673
674  virtual void getGCCRegNames(const char * const *&Names,
675                              unsigned &NumNames) const;
676  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
677                                unsigned &NumAliases) const;
678  virtual bool validateAsmConstraint(const char *&Name,
679                                     TargetInfo::ConstraintInfo &Info) const {
680    switch (*Name) {
681    default: return false;
682    case 'O': // Zero
683      break;
684    case 'b': // Base register
685    case 'f': // Floating point register
686      Info.setAllowsRegister();
687      break;
688    // FIXME: The following are added to allow parsing.
689    // I just took a guess at what the actions should be.
690    // Also, is more specific checking needed?  I.e. specific registers?
691    case 'd': // Floating point register (containing 64-bit value)
692    case 'v': // Altivec vector register
693      Info.setAllowsRegister();
694      break;
695    case 'w':
696      switch (Name[1]) {
697        case 'd':// VSX vector register to hold vector double data
698        case 'f':// VSX vector register to hold vector float data
699        case 's':// VSX vector register to hold scalar float data
700        case 'a':// Any VSX register
701          break;
702        default:
703          return false;
704      }
705      Info.setAllowsRegister();
706      Name++; // Skip over 'w'.
707      break;
708    case 'h': // `MQ', `CTR', or `LINK' register
709    case 'q': // `MQ' register
710    case 'c': // `CTR' register
711    case 'l': // `LINK' register
712    case 'x': // `CR' register (condition register) number 0
713    case 'y': // `CR' register (condition register)
714    case 'z': // `XER[CA]' carry bit (part of the XER register)
715      Info.setAllowsRegister();
716      break;
717    case 'I': // Signed 16-bit constant
718    case 'J': // Unsigned 16-bit constant shifted left 16 bits
719              //  (use `L' instead for SImode constants)
720    case 'K': // Unsigned 16-bit constant
721    case 'L': // Signed 16-bit constant shifted left 16 bits
722    case 'M': // Constant larger than 31
723    case 'N': // Exact power of 2
724    case 'P': // Constant whose negation is a signed 16-bit constant
725    case 'G': // Floating point constant that can be loaded into a
726              // register with one instruction per word
727    case 'H': // Integer/Floating point constant that can be loaded
728              // into a register using three instructions
729      break;
730    case 'm': // Memory operand. Note that on PowerPC targets, m can
731              // include addresses that update the base register. It
732              // is therefore only safe to use `m' in an asm statement
733              // if that asm statement accesses the operand exactly once.
734              // The asm statement must also use `%U<opno>' as a
735              // placeholder for the "update" flag in the corresponding
736              // load or store instruction. For example:
737              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
738              // is correct but:
739              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
740              // is not. Use es rather than m if you don't want the base
741              // register to be updated.
742    case 'e':
743      if (Name[1] != 's')
744          return false;
745              // es: A "stable" memory operand; that is, one which does not
746              // include any automodification of the base register. Unlike
747              // `m', this constraint can be used in asm statements that
748              // might access the operand several times, or that might not
749              // access it at all.
750      Info.setAllowsMemory();
751      Name++; // Skip over 'e'.
752      break;
753    case 'Q': // Memory operand that is an offset from a register (it is
754              // usually better to use `m' or `es' in asm statements)
755    case 'Z': // Memory operand that is an indexed or indirect from a
756              // register (it is usually better to use `m' or `es' in
757              // asm statements)
758      Info.setAllowsMemory();
759      Info.setAllowsRegister();
760      break;
761    case 'R': // AIX TOC entry
762    case 'a': // Address operand that is an indexed or indirect from a
763              // register (`p' is preferable for asm statements)
764    case 'S': // Constant suitable as a 64-bit mask operand
765    case 'T': // Constant suitable as a 32-bit mask operand
766    case 'U': // System V Release 4 small data area reference
767    case 't': // AND masks that can be performed by two rldic{l, r}
768              // instructions
769    case 'W': // Vector constant that does not require memory
770    case 'j': // Vector constant that is all zeros.
771      break;
772    // End FIXME.
773    }
774    return true;
775  }
776  virtual const char *getClobbers() const {
777    return "";
778  }
779};
780
781const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
782#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
783#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
784                                              ALL_LANGUAGES },
785#include "clang/Basic/BuiltinsPPC.def"
786};
787
788
789/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
790/// #defines that are not tied to a specific subtarget.
791void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
792                                     MacroBuilder &Builder) const {
793  // Target identification.
794  Builder.defineMacro("__ppc__");
795  Builder.defineMacro("_ARCH_PPC");
796  Builder.defineMacro("__powerpc__");
797  Builder.defineMacro("__POWERPC__");
798  if (PointerWidth == 64) {
799    Builder.defineMacro("_ARCH_PPC64");
800    Builder.defineMacro("__powerpc64__");
801    Builder.defineMacro("__ppc64__");
802  } else {
803    Builder.defineMacro("__ppc__");
804  }
805
806  // Target properties.
807  if (getTriple().getOS() != llvm::Triple::NetBSD &&
808      getTriple().getOS() != llvm::Triple::OpenBSD)
809    Builder.defineMacro("_BIG_ENDIAN");
810  Builder.defineMacro("__BIG_ENDIAN__");
811
812  // Subtarget options.
813  Builder.defineMacro("__NATURAL_ALIGNMENT__");
814  Builder.defineMacro("__REGISTER_PREFIX__", "");
815
816  // FIXME: Should be controlled by command line option.
817  Builder.defineMacro("__LONG_DOUBLE_128__");
818
819  if (Opts.AltiVec) {
820    Builder.defineMacro("__VEC__", "10206");
821    Builder.defineMacro("__ALTIVEC__");
822  }
823
824  // CPU identification.
825  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
826    .Case("440",   ArchDefineName)
827    .Case("450",   ArchDefineName | ArchDefine440)
828    .Case("601",   ArchDefineName)
829    .Case("602",   ArchDefineName | ArchDefinePpcgr)
830    .Case("603",   ArchDefineName | ArchDefinePpcgr)
831    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
832    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
833    .Case("604",   ArchDefineName | ArchDefinePpcgr)
834    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
835    .Case("620",   ArchDefineName | ArchDefinePpcgr)
836    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
837    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
838    .Case("750",   ArchDefineName | ArchDefinePpcgr)
839    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
840                     | ArchDefinePpcsq)
841    .Case("pwr6",  ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
842    .Case("pwr7",  ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr
843                     | ArchDefinePpcsq)
844    .Default(ArchDefineNone);
845
846  if (defs & ArchDefineName)
847    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
848  if (defs & ArchDefinePpcgr)
849    Builder.defineMacro("_ARCH_PPCGR");
850  if (defs & ArchDefinePpcsq)
851    Builder.defineMacro("_ARCH_PPCSQ");
852  if (defs & ArchDefine440)
853    Builder.defineMacro("_ARCH_440");
854  if (defs & ArchDefine603)
855    Builder.defineMacro("_ARCH_603");
856  if (defs & ArchDefine604)
857    Builder.defineMacro("_ARCH_604");
858  if (defs & (ArchDefinePwr4 | ArchDefinePwr6))
859    Builder.defineMacro("_ARCH_PWR4");
860  if (defs & ArchDefinePwr6) {
861    Builder.defineMacro("_ARCH_PWR5");
862    Builder.defineMacro("_ARCH_PWR6");
863  }
864}
865
866bool PPCTargetInfo::hasFeature(StringRef Feature) const {
867  return Feature == "powerpc";
868}
869
870
871const char * const PPCTargetInfo::GCCRegNames[] = {
872  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
873  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
874  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
875  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
876  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
877  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
878  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
879  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
880  "mq", "lr", "ctr", "ap",
881  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
882  "xer",
883  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
884  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
885  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
886  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
887  "vrsave", "vscr",
888  "spe_acc", "spefscr",
889  "sfp"
890};
891
892void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
893                                   unsigned &NumNames) const {
894  Names = GCCRegNames;
895  NumNames = llvm::array_lengthof(GCCRegNames);
896}
897
898const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
899  // While some of these aliases do map to different registers
900  // they still share the same register name.
901  { { "0" }, "r0" },
902  { { "1"}, "r1" },
903  { { "2" }, "r2" },
904  { { "3" }, "r3" },
905  { { "4" }, "r4" },
906  { { "5" }, "r5" },
907  { { "6" }, "r6" },
908  { { "7" }, "r7" },
909  { { "8" }, "r8" },
910  { { "9" }, "r9" },
911  { { "10" }, "r10" },
912  { { "11" }, "r11" },
913  { { "12" }, "r12" },
914  { { "13" }, "r13" },
915  { { "14" }, "r14" },
916  { { "15" }, "r15" },
917  { { "16" }, "r16" },
918  { { "17" }, "r17" },
919  { { "18" }, "r18" },
920  { { "19" }, "r19" },
921  { { "20" }, "r20" },
922  { { "21" }, "r21" },
923  { { "22" }, "r22" },
924  { { "23" }, "r23" },
925  { { "24" }, "r24" },
926  { { "25" }, "r25" },
927  { { "26" }, "r26" },
928  { { "27" }, "r27" },
929  { { "28" }, "r28" },
930  { { "29" }, "r29" },
931  { { "30" }, "r30" },
932  { { "31" }, "r31" },
933  { { "fr0" }, "f0" },
934  { { "fr1" }, "f1" },
935  { { "fr2" }, "f2" },
936  { { "fr3" }, "f3" },
937  { { "fr4" }, "f4" },
938  { { "fr5" }, "f5" },
939  { { "fr6" }, "f6" },
940  { { "fr7" }, "f7" },
941  { { "fr8" }, "f8" },
942  { { "fr9" }, "f9" },
943  { { "fr10" }, "f10" },
944  { { "fr11" }, "f11" },
945  { { "fr12" }, "f12" },
946  { { "fr13" }, "f13" },
947  { { "fr14" }, "f14" },
948  { { "fr15" }, "f15" },
949  { { "fr16" }, "f16" },
950  { { "fr17" }, "f17" },
951  { { "fr18" }, "f18" },
952  { { "fr19" }, "f19" },
953  { { "fr20" }, "f20" },
954  { { "fr21" }, "f21" },
955  { { "fr22" }, "f22" },
956  { { "fr23" }, "f23" },
957  { { "fr24" }, "f24" },
958  { { "fr25" }, "f25" },
959  { { "fr26" }, "f26" },
960  { { "fr27" }, "f27" },
961  { { "fr28" }, "f28" },
962  { { "fr29" }, "f29" },
963  { { "fr30" }, "f30" },
964  { { "fr31" }, "f31" },
965  { { "cc" }, "cr0" },
966};
967
968void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
969                                     unsigned &NumAliases) const {
970  Aliases = GCCRegAliases;
971  NumAliases = llvm::array_lengthof(GCCRegAliases);
972}
973} // end anonymous namespace.
974
975namespace {
976class PPC32TargetInfo : public PPCTargetInfo {
977public:
978  PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
979    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
980                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
981
982    switch (getTriple().getOS()) {
983    case llvm::Triple::Linux:
984    case llvm::Triple::FreeBSD:
985    case llvm::Triple::NetBSD:
986      SizeType = UnsignedInt;
987      PtrDiffType = SignedInt;
988      IntPtrType = SignedInt;
989      break;
990    default:
991      break;
992    }
993
994    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
995      LongDoubleWidth = LongDoubleAlign = 64;
996      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
997    }
998  }
999
1000  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1001    // This is the ELF definition, and is overridden by the Darwin sub-target
1002    return TargetInfo::PowerABIBuiltinVaList;
1003  }
1004};
1005} // end anonymous namespace.
1006
1007namespace {
1008class PPC64TargetInfo : public PPCTargetInfo {
1009public:
1010  PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1011    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1012    IntMaxType = SignedLong;
1013    UIntMaxType = UnsignedLong;
1014    Int64Type = SignedLong;
1015    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1016                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1017
1018    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1019      LongDoubleWidth = LongDoubleAlign = 64;
1020      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1021    }
1022  }
1023  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1024    return TargetInfo::CharPtrBuiltinVaList;
1025  }
1026};
1027} // end anonymous namespace.
1028
1029
1030namespace {
1031class DarwinPPC32TargetInfo :
1032  public DarwinTargetInfo<PPC32TargetInfo> {
1033public:
1034  DarwinPPC32TargetInfo(const std::string& triple)
1035    : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1036    HasAlignMac68kSupport = true;
1037    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1038    LongLongAlign = 32;
1039    SuitableAlign = 128;
1040    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1041                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1042  }
1043  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1044    return TargetInfo::CharPtrBuiltinVaList;
1045  }
1046};
1047
1048class DarwinPPC64TargetInfo :
1049  public DarwinTargetInfo<PPC64TargetInfo> {
1050public:
1051  DarwinPPC64TargetInfo(const std::string& triple)
1052    : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1053    HasAlignMac68kSupport = true;
1054    SuitableAlign = 128;
1055  }
1056};
1057} // end anonymous namespace.
1058
1059namespace {
1060  static const unsigned NVPTXAddrSpaceMap[] = {
1061    1,    // opencl_global
1062    3,    // opencl_local
1063    4,    // opencl_constant
1064    1,    // cuda_device
1065    4,    // cuda_constant
1066    3,    // cuda_shared
1067  };
1068  class NVPTXTargetInfo : public TargetInfo {
1069    static const char * const GCCRegNames[];
1070    static const Builtin::Info BuiltinInfo[];
1071    std::vector<llvm::StringRef> AvailableFeatures;
1072  public:
1073    NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1074      BigEndian = false;
1075      TLSSupported = false;
1076      LongWidth = LongAlign = 64;
1077      AddrSpaceMap = &NVPTXAddrSpaceMap;
1078      // Define available target features
1079      // These must be defined in sorted order!
1080      NoAsmVariants = true;
1081    }
1082    virtual void getTargetDefines(const LangOptions &Opts,
1083                                  MacroBuilder &Builder) const {
1084      Builder.defineMacro("__PTX__");
1085      Builder.defineMacro("__NVPTX__");
1086    }
1087    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1088                                   unsigned &NumRecords) const {
1089      Records = BuiltinInfo;
1090      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1091    }
1092    virtual bool hasFeature(StringRef Feature) const {
1093      return Feature == "ptx" || Feature == "nvptx";
1094    }
1095
1096    virtual void getGCCRegNames(const char * const *&Names,
1097                                unsigned &NumNames) const;
1098    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1099                                  unsigned &NumAliases) const {
1100      // No aliases.
1101      Aliases = 0;
1102      NumAliases = 0;
1103    }
1104    virtual bool validateAsmConstraint(const char *&Name,
1105                                       TargetInfo::ConstraintInfo &info) const {
1106      // FIXME: implement
1107      return true;
1108    }
1109    virtual const char *getClobbers() const {
1110      // FIXME: Is this really right?
1111      return "";
1112    }
1113    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1114      // FIXME: implement
1115      return TargetInfo::CharPtrBuiltinVaList;
1116    }
1117    virtual bool setCPU(const std::string &Name) {
1118      return Name == "sm_10" || Name == "sm_13" || Name == "sm_20";
1119    }
1120    virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1121                                   StringRef Name,
1122                                   bool Enabled) const;
1123  };
1124
1125  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1126#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1127#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1128                                              ALL_LANGUAGES },
1129#include "clang/Basic/BuiltinsNVPTX.def"
1130  };
1131
1132  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1133    "r0"
1134  };
1135
1136  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1137                                     unsigned &NumNames) const {
1138    Names = GCCRegNames;
1139    NumNames = llvm::array_lengthof(GCCRegNames);
1140  }
1141
1142  bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1143                                          StringRef Name,
1144                                          bool Enabled) const {
1145    if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1146                          Name)) {
1147      Features[Name] = Enabled;
1148      return true;
1149    } else {
1150      return false;
1151    }
1152  }
1153
1154  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1155  public:
1156    NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1157      PointerWidth = PointerAlign = 32;
1158      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1159      DescriptionString
1160        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1161          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1162          "n16:32:64";
1163  }
1164  };
1165
1166  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1167  public:
1168    NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1169      PointerWidth = PointerAlign = 64;
1170      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1171      DescriptionString
1172        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1173          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1174          "n16:32:64";
1175  }
1176  };
1177}
1178
1179namespace {
1180// MBlaze abstract base class
1181class MBlazeTargetInfo : public TargetInfo {
1182  static const char * const GCCRegNames[];
1183  static const TargetInfo::GCCRegAlias GCCRegAliases[];
1184
1185public:
1186  MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1187    DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1188  }
1189
1190  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1191                                 unsigned &NumRecords) const {
1192    // FIXME: Implement.
1193    Records = 0;
1194    NumRecords = 0;
1195  }
1196
1197  virtual void getTargetDefines(const LangOptions &Opts,
1198                                MacroBuilder &Builder) const;
1199
1200  virtual bool hasFeature(StringRef Feature) const {
1201    return Feature == "mblaze";
1202  }
1203
1204  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1205    return TargetInfo::CharPtrBuiltinVaList;
1206  }
1207  virtual const char *getTargetPrefix() const {
1208    return "mblaze";
1209  }
1210  virtual void getGCCRegNames(const char * const *&Names,
1211                              unsigned &NumNames) const;
1212  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1213                                unsigned &NumAliases) const;
1214  virtual bool validateAsmConstraint(const char *&Name,
1215                                     TargetInfo::ConstraintInfo &Info) const {
1216    switch (*Name) {
1217    default: return false;
1218    case 'O': // Zero
1219      return true;
1220    case 'b': // Base register
1221    case 'f': // Floating point register
1222      Info.setAllowsRegister();
1223      return true;
1224    }
1225  }
1226  virtual const char *getClobbers() const {
1227    return "";
1228  }
1229};
1230
1231/// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1232/// #defines that are not tied to a specific subtarget.
1233void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1234                                     MacroBuilder &Builder) const {
1235  // Target identification.
1236  Builder.defineMacro("__microblaze__");
1237  Builder.defineMacro("_ARCH_MICROBLAZE");
1238  Builder.defineMacro("__MICROBLAZE__");
1239
1240  // Target properties.
1241  Builder.defineMacro("_BIG_ENDIAN");
1242  Builder.defineMacro("__BIG_ENDIAN__");
1243
1244  // Subtarget options.
1245  Builder.defineMacro("__REGISTER_PREFIX__", "");
1246}
1247
1248
1249const char * const MBlazeTargetInfo::GCCRegNames[] = {
1250  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1251  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1252  "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1253  "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1254  "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1255  "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1256  "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1257  "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1258  "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1259  "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1260};
1261
1262void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1263                                   unsigned &NumNames) const {
1264  Names = GCCRegNames;
1265  NumNames = llvm::array_lengthof(GCCRegNames);
1266}
1267
1268const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1269  { {"f0"},  "r0" },
1270  { {"f1"},  "r1" },
1271  { {"f2"},  "r2" },
1272  { {"f3"},  "r3" },
1273  { {"f4"},  "r4" },
1274  { {"f5"},  "r5" },
1275  { {"f6"},  "r6" },
1276  { {"f7"},  "r7" },
1277  { {"f8"},  "r8" },
1278  { {"f9"},  "r9" },
1279  { {"f10"}, "r10" },
1280  { {"f11"}, "r11" },
1281  { {"f12"}, "r12" },
1282  { {"f13"}, "r13" },
1283  { {"f14"}, "r14" },
1284  { {"f15"}, "r15" },
1285  { {"f16"}, "r16" },
1286  { {"f17"}, "r17" },
1287  { {"f18"}, "r18" },
1288  { {"f19"}, "r19" },
1289  { {"f20"}, "r20" },
1290  { {"f21"}, "r21" },
1291  { {"f22"}, "r22" },
1292  { {"f23"}, "r23" },
1293  { {"f24"}, "r24" },
1294  { {"f25"}, "r25" },
1295  { {"f26"}, "r26" },
1296  { {"f27"}, "r27" },
1297  { {"f28"}, "r28" },
1298  { {"f29"}, "r29" },
1299  { {"f30"}, "r30" },
1300  { {"f31"}, "r31" },
1301};
1302
1303void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1304                                     unsigned &NumAliases) const {
1305  Aliases = GCCRegAliases;
1306  NumAliases = llvm::array_lengthof(GCCRegAliases);
1307}
1308} // end anonymous namespace.
1309
1310namespace {
1311// Namespace for x86 abstract base class
1312const Builtin::Info BuiltinInfo[] = {
1313#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1314#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1315                                              ALL_LANGUAGES },
1316#include "clang/Basic/BuiltinsX86.def"
1317};
1318
1319static const char* const GCCRegNames[] = {
1320  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1321  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1322  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1323  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1324  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1325  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1326  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1327  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1328  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1329};
1330
1331const TargetInfo::AddlRegName AddlRegNames[] = {
1332  { { "al", "ah", "eax", "rax" }, 0 },
1333  { { "bl", "bh", "ebx", "rbx" }, 3 },
1334  { { "cl", "ch", "ecx", "rcx" }, 2 },
1335  { { "dl", "dh", "edx", "rdx" }, 1 },
1336  { { "esi", "rsi" }, 4 },
1337  { { "edi", "rdi" }, 5 },
1338  { { "esp", "rsp" }, 7 },
1339  { { "ebp", "rbp" }, 6 },
1340};
1341
1342// X86 target abstract base class; x86-32 and x86-64 are very close, so
1343// most of the implementation can be shared.
1344class X86TargetInfo : public TargetInfo {
1345  enum X86SSEEnum {
1346    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1347  } SSELevel;
1348  enum MMX3DNowEnum {
1349    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1350  } MMX3DNowLevel;
1351
1352  bool HasAES;
1353  bool HasPCLMUL;
1354  bool HasLZCNT;
1355  bool HasRDRND;
1356  bool HasBMI;
1357  bool HasBMI2;
1358  bool HasPOPCNT;
1359  bool HasSSE4a;
1360  bool HasFMA4;
1361  bool HasFMA;
1362  bool HasXOP;
1363  bool HasF16C;
1364
1365  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1366  ///
1367  /// Each enumeration represents a particular CPU supported by Clang. These
1368  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1369  enum CPUKind {
1370    CK_Generic,
1371
1372    /// \name i386
1373    /// i386-generation processors.
1374    //@{
1375    CK_i386,
1376    //@}
1377
1378    /// \name i486
1379    /// i486-generation processors.
1380    //@{
1381    CK_i486,
1382    CK_WinChipC6,
1383    CK_WinChip2,
1384    CK_C3,
1385    //@}
1386
1387    /// \name i586
1388    /// i586-generation processors, P5 microarchitecture based.
1389    //@{
1390    CK_i586,
1391    CK_Pentium,
1392    CK_PentiumMMX,
1393    //@}
1394
1395    /// \name i686
1396    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1397    //@{
1398    CK_i686,
1399    CK_PentiumPro,
1400    CK_Pentium2,
1401    CK_Pentium3,
1402    CK_Pentium3M,
1403    CK_PentiumM,
1404    CK_C3_2,
1405
1406    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1407    /// Clang however has some logic to suport this.
1408    // FIXME: Warn, deprecate, and potentially remove this.
1409    CK_Yonah,
1410    //@}
1411
1412    /// \name Netburst
1413    /// Netburst microarchitecture based processors.
1414    //@{
1415    CK_Pentium4,
1416    CK_Pentium4M,
1417    CK_Prescott,
1418    CK_Nocona,
1419    //@}
1420
1421    /// \name Core
1422    /// Core microarchitecture based processors.
1423    //@{
1424    CK_Core2,
1425
1426    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1427    /// codename which GCC no longer accepts as an option to -march, but Clang
1428    /// has some logic for recognizing it.
1429    // FIXME: Warn, deprecate, and potentially remove this.
1430    CK_Penryn,
1431    //@}
1432
1433    /// \name Atom
1434    /// Atom processors
1435    //@{
1436    CK_Atom,
1437    //@}
1438
1439    /// \name Nehalem
1440    /// Nehalem microarchitecture based processors.
1441    //@{
1442    CK_Corei7,
1443    CK_Corei7AVX,
1444    CK_CoreAVXi,
1445    CK_CoreAVX2,
1446    //@}
1447
1448    /// \name K6
1449    /// K6 architecture processors.
1450    //@{
1451    CK_K6,
1452    CK_K6_2,
1453    CK_K6_3,
1454    //@}
1455
1456    /// \name K7
1457    /// K7 architecture processors.
1458    //@{
1459    CK_Athlon,
1460    CK_AthlonThunderbird,
1461    CK_Athlon4,
1462    CK_AthlonXP,
1463    CK_AthlonMP,
1464    //@}
1465
1466    /// \name K8
1467    /// K8 architecture processors.
1468    //@{
1469    CK_Athlon64,
1470    CK_Athlon64SSE3,
1471    CK_AthlonFX,
1472    CK_K8,
1473    CK_K8SSE3,
1474    CK_Opteron,
1475    CK_OpteronSSE3,
1476    CK_AMDFAM10,
1477    //@}
1478
1479    /// \name Bobcat
1480    /// Bobcat architecture processors.
1481    //@{
1482    CK_BTVER1,
1483    //@}
1484
1485    /// \name Bulldozer
1486    /// Bulldozer architecture processors.
1487    //@{
1488    CK_BDVER1,
1489    CK_BDVER2,
1490    //@}
1491
1492    /// This specification is deprecated and will be removed in the future.
1493    /// Users should prefer \see CK_K8.
1494    // FIXME: Warn on this when the CPU is set to it.
1495    CK_x86_64,
1496    //@}
1497
1498    /// \name Geode
1499    /// Geode processors.
1500    //@{
1501    CK_Geode
1502    //@}
1503  } CPU;
1504
1505public:
1506  X86TargetInfo(const std::string& triple)
1507    : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1508      HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1509      HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasSSE4a(false),
1510      HasFMA4(false), HasFMA(false), HasXOP(false), HasF16C(false),
1511      CPU(CK_Generic) {
1512    BigEndian = false;
1513    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1514  }
1515  virtual unsigned getFloatEvalMethod() const {
1516    // X87 evaluates with 80 bits "long double" precision.
1517    return SSELevel == NoSSE ? 2 : 0;
1518  }
1519  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1520                                 unsigned &NumRecords) const {
1521    Records = BuiltinInfo;
1522    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1523  }
1524  virtual void getGCCRegNames(const char * const *&Names,
1525                              unsigned &NumNames) const {
1526    Names = GCCRegNames;
1527    NumNames = llvm::array_lengthof(GCCRegNames);
1528  }
1529  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1530                                unsigned &NumAliases) const {
1531    Aliases = 0;
1532    NumAliases = 0;
1533  }
1534  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1535				  unsigned &NumNames) const {
1536    Names = AddlRegNames;
1537    NumNames = llvm::array_lengthof(AddlRegNames);
1538  }
1539  virtual bool validateAsmConstraint(const char *&Name,
1540                                     TargetInfo::ConstraintInfo &info) const;
1541  virtual std::string convertConstraint(const char *&Constraint) const;
1542  virtual const char *getClobbers() const {
1543    return "~{dirflag},~{fpsr},~{flags}";
1544  }
1545  virtual void getTargetDefines(const LangOptions &Opts,
1546                                MacroBuilder &Builder) const;
1547  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1548                                 StringRef Name,
1549                                 bool Enabled) const;
1550  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1551  virtual bool hasFeature(StringRef Feature) const;
1552  virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1553  virtual const char* getABI() const {
1554    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1555      return "avx";
1556    else if (getTriple().getArch() == llvm::Triple::x86 &&
1557             MMX3DNowLevel == NoMMX3DNow)
1558      return "no-mmx";
1559    return "";
1560  }
1561  virtual bool setCPU(const std::string &Name) {
1562    CPU = llvm::StringSwitch<CPUKind>(Name)
1563      .Case("i386", CK_i386)
1564      .Case("i486", CK_i486)
1565      .Case("winchip-c6", CK_WinChipC6)
1566      .Case("winchip2", CK_WinChip2)
1567      .Case("c3", CK_C3)
1568      .Case("i586", CK_i586)
1569      .Case("pentium", CK_Pentium)
1570      .Case("pentium-mmx", CK_PentiumMMX)
1571      .Case("i686", CK_i686)
1572      .Case("pentiumpro", CK_PentiumPro)
1573      .Case("pentium2", CK_Pentium2)
1574      .Case("pentium3", CK_Pentium3)
1575      .Case("pentium3m", CK_Pentium3M)
1576      .Case("pentium-m", CK_PentiumM)
1577      .Case("c3-2", CK_C3_2)
1578      .Case("yonah", CK_Yonah)
1579      .Case("pentium4", CK_Pentium4)
1580      .Case("pentium4m", CK_Pentium4M)
1581      .Case("prescott", CK_Prescott)
1582      .Case("nocona", CK_Nocona)
1583      .Case("core2", CK_Core2)
1584      .Case("penryn", CK_Penryn)
1585      .Case("atom", CK_Atom)
1586      .Case("corei7", CK_Corei7)
1587      .Case("corei7-avx", CK_Corei7AVX)
1588      .Case("core-avx-i", CK_CoreAVXi)
1589      .Case("core-avx2", CK_CoreAVX2)
1590      .Case("k6", CK_K6)
1591      .Case("k6-2", CK_K6_2)
1592      .Case("k6-3", CK_K6_3)
1593      .Case("athlon", CK_Athlon)
1594      .Case("athlon-tbird", CK_AthlonThunderbird)
1595      .Case("athlon-4", CK_Athlon4)
1596      .Case("athlon-xp", CK_AthlonXP)
1597      .Case("athlon-mp", CK_AthlonMP)
1598      .Case("athlon64", CK_Athlon64)
1599      .Case("athlon64-sse3", CK_Athlon64SSE3)
1600      .Case("athlon-fx", CK_AthlonFX)
1601      .Case("k8", CK_K8)
1602      .Case("k8-sse3", CK_K8SSE3)
1603      .Case("opteron", CK_Opteron)
1604      .Case("opteron-sse3", CK_OpteronSSE3)
1605      .Case("amdfam10", CK_AMDFAM10)
1606      .Case("btver1", CK_BTVER1)
1607      .Case("bdver1", CK_BDVER1)
1608      .Case("bdver2", CK_BDVER2)
1609      .Case("x86-64", CK_x86_64)
1610      .Case("geode", CK_Geode)
1611      .Default(CK_Generic);
1612
1613    // Perform any per-CPU checks necessary to determine if this CPU is
1614    // acceptable.
1615    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1616    // invalid without explaining *why*.
1617    switch (CPU) {
1618    case CK_Generic:
1619      // No processor selected!
1620      return false;
1621
1622    case CK_i386:
1623    case CK_i486:
1624    case CK_WinChipC6:
1625    case CK_WinChip2:
1626    case CK_C3:
1627    case CK_i586:
1628    case CK_Pentium:
1629    case CK_PentiumMMX:
1630    case CK_i686:
1631    case CK_PentiumPro:
1632    case CK_Pentium2:
1633    case CK_Pentium3:
1634    case CK_Pentium3M:
1635    case CK_PentiumM:
1636    case CK_Yonah:
1637    case CK_C3_2:
1638    case CK_Pentium4:
1639    case CK_Pentium4M:
1640    case CK_Prescott:
1641    case CK_K6:
1642    case CK_K6_2:
1643    case CK_K6_3:
1644    case CK_Athlon:
1645    case CK_AthlonThunderbird:
1646    case CK_Athlon4:
1647    case CK_AthlonXP:
1648    case CK_AthlonMP:
1649    case CK_Geode:
1650      // Only accept certain architectures when compiling in 32-bit mode.
1651      if (getTriple().getArch() != llvm::Triple::x86)
1652        return false;
1653
1654      // Fallthrough
1655    case CK_Nocona:
1656    case CK_Core2:
1657    case CK_Penryn:
1658    case CK_Atom:
1659    case CK_Corei7:
1660    case CK_Corei7AVX:
1661    case CK_CoreAVXi:
1662    case CK_CoreAVX2:
1663    case CK_Athlon64:
1664    case CK_Athlon64SSE3:
1665    case CK_AthlonFX:
1666    case CK_K8:
1667    case CK_K8SSE3:
1668    case CK_Opteron:
1669    case CK_OpteronSSE3:
1670    case CK_AMDFAM10:
1671    case CK_BTVER1:
1672    case CK_BDVER1:
1673    case CK_BDVER2:
1674    case CK_x86_64:
1675      return true;
1676    }
1677    llvm_unreachable("Unhandled CPU kind");
1678  }
1679
1680  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1681    // We accept all non-ARM calling conventions
1682    return (CC == CC_X86ThisCall ||
1683            CC == CC_X86FastCall ||
1684            CC == CC_X86StdCall ||
1685            CC == CC_C ||
1686            CC == CC_X86Pascal) ? CCCR_OK : CCCR_Warning;
1687  }
1688
1689  virtual CallingConv getDefaultCallingConv() const {
1690    return CC_C;
1691  }
1692};
1693
1694void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1695  // FIXME: This should not be here.
1696  Features["3dnow"] = false;
1697  Features["3dnowa"] = false;
1698  Features["mmx"] = false;
1699  Features["sse"] = false;
1700  Features["sse2"] = false;
1701  Features["sse3"] = false;
1702  Features["ssse3"] = false;
1703  Features["sse41"] = false;
1704  Features["sse42"] = false;
1705  Features["sse4a"] = false;
1706  Features["aes"] = false;
1707  Features["pclmul"] = false;
1708  Features["avx"] = false;
1709  Features["avx2"] = false;
1710  Features["lzcnt"] = false;
1711  Features["rdrand"] = false;
1712  Features["bmi"] = false;
1713  Features["bmi2"] = false;
1714  Features["popcnt"] = false;
1715  Features["fma4"] = false;
1716  Features["fma"] = false;
1717  Features["xop"] = false;
1718  Features["f16c"] = false;
1719
1720  // FIXME: This *really* should not be here.
1721
1722  // X86_64 always has SSE2.
1723  if (getTriple().getArch() == llvm::Triple::x86_64)
1724    Features["sse2"] = Features["sse"] = Features["mmx"] = true;
1725
1726  switch (CPU) {
1727  case CK_Generic:
1728  case CK_i386:
1729  case CK_i486:
1730  case CK_i586:
1731  case CK_Pentium:
1732  case CK_i686:
1733  case CK_PentiumPro:
1734    break;
1735  case CK_PentiumMMX:
1736  case CK_Pentium2:
1737    setFeatureEnabled(Features, "mmx", true);
1738    break;
1739  case CK_Pentium3:
1740  case CK_Pentium3M:
1741    setFeatureEnabled(Features, "mmx", true);
1742    setFeatureEnabled(Features, "sse", true);
1743    break;
1744  case CK_PentiumM:
1745  case CK_Pentium4:
1746  case CK_Pentium4M:
1747  case CK_x86_64:
1748    setFeatureEnabled(Features, "mmx", true);
1749    setFeatureEnabled(Features, "sse2", true);
1750    break;
1751  case CK_Yonah:
1752  case CK_Prescott:
1753  case CK_Nocona:
1754    setFeatureEnabled(Features, "mmx", true);
1755    setFeatureEnabled(Features, "sse3", true);
1756    break;
1757  case CK_Core2:
1758    setFeatureEnabled(Features, "mmx", true);
1759    setFeatureEnabled(Features, "ssse3", true);
1760    break;
1761  case CK_Penryn:
1762    setFeatureEnabled(Features, "mmx", true);
1763    setFeatureEnabled(Features, "sse4.1", true);
1764    break;
1765  case CK_Atom:
1766    setFeatureEnabled(Features, "mmx", true);
1767    setFeatureEnabled(Features, "ssse3", true);
1768    break;
1769  case CK_Corei7:
1770    setFeatureEnabled(Features, "mmx", true);
1771    setFeatureEnabled(Features, "sse4", true);
1772    break;
1773  case CK_Corei7AVX:
1774    setFeatureEnabled(Features, "mmx", true);
1775    setFeatureEnabled(Features, "avx", true);
1776    setFeatureEnabled(Features, "aes", true);
1777    setFeatureEnabled(Features, "pclmul", true);
1778    break;
1779  case CK_CoreAVXi:
1780    setFeatureEnabled(Features, "mmx", true);
1781    setFeatureEnabled(Features, "avx", true);
1782    setFeatureEnabled(Features, "aes", true);
1783    setFeatureEnabled(Features, "pclmul", true);
1784    setFeatureEnabled(Features, "rdrnd", true);
1785    break;
1786  case CK_CoreAVX2:
1787    setFeatureEnabled(Features, "mmx", true);
1788    setFeatureEnabled(Features, "avx2", true);
1789    setFeatureEnabled(Features, "aes", true);
1790    setFeatureEnabled(Features, "pclmul", true);
1791    setFeatureEnabled(Features, "lzcnt", true);
1792    setFeatureEnabled(Features, "rdrnd", true);
1793    setFeatureEnabled(Features, "bmi", true);
1794    setFeatureEnabled(Features, "bmi2", true);
1795    setFeatureEnabled(Features, "fma", true);
1796    break;
1797  case CK_K6:
1798  case CK_WinChipC6:
1799    setFeatureEnabled(Features, "mmx", true);
1800    break;
1801  case CK_K6_2:
1802  case CK_K6_3:
1803  case CK_WinChip2:
1804  case CK_C3:
1805    setFeatureEnabled(Features, "3dnow", true);
1806    break;
1807  case CK_Athlon:
1808  case CK_AthlonThunderbird:
1809  case CK_Geode:
1810    setFeatureEnabled(Features, "3dnowa", true);
1811    break;
1812  case CK_Athlon4:
1813  case CK_AthlonXP:
1814  case CK_AthlonMP:
1815    setFeatureEnabled(Features, "sse", true);
1816    setFeatureEnabled(Features, "3dnowa", true);
1817    break;
1818  case CK_K8:
1819  case CK_Opteron:
1820  case CK_Athlon64:
1821  case CK_AthlonFX:
1822    setFeatureEnabled(Features, "sse2", true);
1823    setFeatureEnabled(Features, "3dnowa", true);
1824    break;
1825  case CK_K8SSE3:
1826  case CK_OpteronSSE3:
1827  case CK_Athlon64SSE3:
1828    setFeatureEnabled(Features, "sse3", true);
1829    setFeatureEnabled(Features, "3dnowa", true);
1830    break;
1831  case CK_AMDFAM10:
1832    setFeatureEnabled(Features, "sse3", true);
1833    setFeatureEnabled(Features, "sse4a", true);
1834    setFeatureEnabled(Features, "3dnowa", true);
1835    break;
1836  case CK_BTVER1:
1837    setFeatureEnabled(Features, "ssse3", true);
1838    setFeatureEnabled(Features, "sse4a", true);
1839    break;
1840  case CK_BDVER1:
1841  case CK_BDVER2:
1842    setFeatureEnabled(Features, "avx", true);
1843    setFeatureEnabled(Features, "xop", true);
1844    setFeatureEnabled(Features, "aes", true);
1845    setFeatureEnabled(Features, "pclmul", true);
1846    break;
1847  case CK_C3_2:
1848    setFeatureEnabled(Features, "mmx", true);
1849    setFeatureEnabled(Features, "sse", true);
1850    break;
1851  }
1852}
1853
1854bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1855                                      StringRef Name,
1856                                      bool Enabled) const {
1857  // FIXME: This *really* should not be here.  We need some way of translating
1858  // options into llvm subtarget features.
1859  if (!Features.count(Name) &&
1860      (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
1861       Name != "rdrnd"))
1862    return false;
1863
1864  // FIXME: this should probably use a switch with fall through.
1865
1866  if (Enabled) {
1867    if (Name == "mmx")
1868      Features["mmx"] = true;
1869    else if (Name == "sse")
1870      Features["mmx"] = Features["sse"] = true;
1871    else if (Name == "sse2")
1872      Features["mmx"] = Features["sse"] = Features["sse2"] = true;
1873    else if (Name == "sse3")
1874      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1875        true;
1876    else if (Name == "ssse3")
1877      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1878        Features["ssse3"] = true;
1879    else if (Name == "sse4" || Name == "sse4.2")
1880      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1881        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1882        Features["popcnt"] = true;
1883    else if (Name == "sse4.1")
1884      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1885        Features["ssse3"] = Features["sse41"] = true;
1886    else if (Name == "3dnow")
1887      Features["mmx"] = Features["3dnow"] = true;
1888    else if (Name == "3dnowa")
1889      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
1890    else if (Name == "aes")
1891      Features["sse"] = Features["sse2"] = Features["aes"] = true;
1892    else if (Name == "pclmul")
1893      Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
1894    else if (Name == "avx")
1895      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1896        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1897        Features["popcnt"] = Features["avx"] = true;
1898    else if (Name == "avx2")
1899      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1900        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1901        Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
1902    else if (Name == "fma")
1903      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1904        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1905        Features["popcnt"] = Features["avx"] = Features["fma"] = true;
1906    else if (Name == "fma4")
1907        Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1908        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1909        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
1910        Features["fma4"] = true;
1911    else if (Name == "xop")
1912        Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1913        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1914        Features["popcnt"] = Features["avx"] = Features["sse4a"] =
1915        Features["fma4"] = Features["xop"] = true;
1916    else if (Name == "sse4a")
1917      Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
1918        Features["sse4a"] = true;
1919    else if (Name == "lzcnt")
1920      Features["lzcnt"] = true;
1921    else if (Name == "rdrnd")
1922      Features["rdrand"] = true;
1923    else if (Name == "bmi")
1924      Features["bmi"] = true;
1925    else if (Name == "bmi2")
1926      Features["bmi2"] = true;
1927    else if (Name == "popcnt")
1928      Features["popcnt"] = true;
1929    else if (Name == "f16c")
1930      Features["f16c"] = true;
1931  } else {
1932    if (Name == "mmx")
1933      Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
1934    else if (Name == "sse")
1935      Features["sse"] = Features["sse2"] = Features["sse3"] =
1936        Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1937        Features["sse4a"] = Features["avx"] = Features["avx2"] =
1938        Features["fma"] = Features["fma4"] = Features["aes"] =
1939        Features["pclmul"] = Features["xop"] = false;
1940    else if (Name == "sse2")
1941      Features["sse2"] = Features["sse3"] = Features["ssse3"] =
1942        Features["sse41"] = Features["sse42"] = Features["sse4a"] =
1943        Features["avx"] = Features["avx2"] = Features["fma"] =
1944        Features["fma4"] = Features["aes"] = Features["pclmul"] =
1945        Features["xop"] = false;
1946    else if (Name == "sse3")
1947      Features["sse3"] = Features["ssse3"] = Features["sse41"] =
1948        Features["sse42"] = Features["sse4a"] = Features["avx"] =
1949        Features["avx2"] = Features["fma"] = Features["fma4"] =
1950        Features["xop"] = false;
1951    else if (Name == "ssse3")
1952      Features["ssse3"] = Features["sse41"] = Features["sse42"] =
1953        Features["avx"] = Features["avx2"] = Features["fma"] = false;
1954    else if (Name == "sse4" || Name == "sse4.1")
1955      Features["sse41"] = Features["sse42"] = Features["avx"] =
1956        Features["avx2"] = Features["fma"] = false;
1957    else if (Name == "sse4.2")
1958      Features["sse42"] = Features["avx"] = Features["avx2"] =
1959        Features["fma"] = false;
1960    else if (Name == "3dnow")
1961      Features["3dnow"] = Features["3dnowa"] = false;
1962    else if (Name == "3dnowa")
1963      Features["3dnowa"] = false;
1964    else if (Name == "aes")
1965      Features["aes"] = false;
1966    else if (Name == "pclmul")
1967      Features["pclmul"] = false;
1968    else if (Name == "avx")
1969      Features["avx"] = Features["avx2"] = Features["fma"] =
1970        Features["fma4"] = Features["xop"] = false;
1971    else if (Name == "avx2")
1972      Features["avx2"] = false;
1973    else if (Name == "fma")
1974      Features["fma"] = false;
1975    else if (Name == "sse4a")
1976      Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
1977    else if (Name == "lzcnt")
1978      Features["lzcnt"] = false;
1979    else if (Name == "rdrnd")
1980      Features["rdrand"] = false;
1981    else if (Name == "bmi")
1982      Features["bmi"] = false;
1983    else if (Name == "bmi2")
1984      Features["bmi2"] = false;
1985    else if (Name == "popcnt")
1986      Features["popcnt"] = false;
1987    else if (Name == "fma4")
1988      Features["fma4"] = Features["xop"] = false;
1989    else if (Name == "xop")
1990      Features["xop"] = false;
1991    else if (Name == "f16c")
1992      Features["f16c"] = false;
1993  }
1994
1995  return true;
1996}
1997
1998/// HandleTargetOptions - Perform initialization based on the user
1999/// configured set of features.
2000void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2001  // Remember the maximum enabled sselevel.
2002  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2003    // Ignore disabled features.
2004    if (Features[i][0] == '-')
2005      continue;
2006
2007    StringRef Feature = StringRef(Features[i]).substr(1);
2008
2009    if (Feature == "aes") {
2010      HasAES = true;
2011      continue;
2012    }
2013
2014    if (Feature == "pclmul") {
2015      HasPCLMUL = true;
2016      continue;
2017    }
2018
2019    if (Feature == "lzcnt") {
2020      HasLZCNT = true;
2021      continue;
2022    }
2023
2024    if (Feature == "rdrand") {
2025      HasRDRND = true;
2026      continue;
2027    }
2028
2029    if (Feature == "bmi") {
2030      HasBMI = true;
2031      continue;
2032    }
2033
2034    if (Feature == "bmi2") {
2035      HasBMI2 = true;
2036      continue;
2037    }
2038
2039    if (Feature == "popcnt") {
2040      HasPOPCNT = true;
2041      continue;
2042    }
2043
2044    if (Feature == "sse4a") {
2045      HasSSE4a = true;
2046      continue;
2047    }
2048
2049    if (Feature == "fma4") {
2050      HasFMA4 = true;
2051      continue;
2052    }
2053
2054    if (Feature == "fma") {
2055      HasFMA = true;
2056      continue;
2057    }
2058
2059    if (Feature == "xop") {
2060      HasXOP = true;
2061      continue;
2062    }
2063
2064    if (Feature == "f16c") {
2065      HasF16C = true;
2066      continue;
2067    }
2068
2069    assert(Features[i][0] == '+' && "Invalid target feature!");
2070    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2071      .Case("avx2", AVX2)
2072      .Case("avx", AVX)
2073      .Case("sse42", SSE42)
2074      .Case("sse41", SSE41)
2075      .Case("ssse3", SSSE3)
2076      .Case("sse3", SSE3)
2077      .Case("sse2", SSE2)
2078      .Case("sse", SSE1)
2079      .Default(NoSSE);
2080    SSELevel = std::max(SSELevel, Level);
2081
2082    MMX3DNowEnum ThreeDNowLevel =
2083      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2084        .Case("3dnowa", AMD3DNowAthlon)
2085        .Case("3dnow", AMD3DNow)
2086        .Case("mmx", MMX)
2087        .Default(NoMMX3DNow);
2088
2089    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2090  }
2091
2092  // Don't tell the backend if we're turning off mmx; it will end up disabling
2093  // SSE, which we don't want.
2094  std::vector<std::string>::iterator it;
2095  it = std::find(Features.begin(), Features.end(), "-mmx");
2096  if (it != Features.end())
2097    Features.erase(it);
2098}
2099
2100/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2101/// definitions for this particular subtarget.
2102void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2103                                     MacroBuilder &Builder) const {
2104  // Target identification.
2105  if (getTriple().getArch() == llvm::Triple::x86_64) {
2106    Builder.defineMacro("__amd64__");
2107    Builder.defineMacro("__amd64");
2108    Builder.defineMacro("__x86_64");
2109    Builder.defineMacro("__x86_64__");
2110  } else {
2111    DefineStd(Builder, "i386", Opts);
2112  }
2113
2114  // Subtarget options.
2115  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2116  // truly should be based on -mtune options.
2117  switch (CPU) {
2118  case CK_Generic:
2119    break;
2120  case CK_i386:
2121    // The rest are coming from the i386 define above.
2122    Builder.defineMacro("__tune_i386__");
2123    break;
2124  case CK_i486:
2125  case CK_WinChipC6:
2126  case CK_WinChip2:
2127  case CK_C3:
2128    defineCPUMacros(Builder, "i486");
2129    break;
2130  case CK_PentiumMMX:
2131    Builder.defineMacro("__pentium_mmx__");
2132    Builder.defineMacro("__tune_pentium_mmx__");
2133    // Fallthrough
2134  case CK_i586:
2135  case CK_Pentium:
2136    defineCPUMacros(Builder, "i586");
2137    defineCPUMacros(Builder, "pentium");
2138    break;
2139  case CK_Pentium3:
2140  case CK_Pentium3M:
2141  case CK_PentiumM:
2142    Builder.defineMacro("__tune_pentium3__");
2143    // Fallthrough
2144  case CK_Pentium2:
2145  case CK_C3_2:
2146    Builder.defineMacro("__tune_pentium2__");
2147    // Fallthrough
2148  case CK_PentiumPro:
2149    Builder.defineMacro("__tune_i686__");
2150    Builder.defineMacro("__tune_pentiumpro__");
2151    // Fallthrough
2152  case CK_i686:
2153    Builder.defineMacro("__i686");
2154    Builder.defineMacro("__i686__");
2155    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2156    Builder.defineMacro("__pentiumpro");
2157    Builder.defineMacro("__pentiumpro__");
2158    break;
2159  case CK_Pentium4:
2160  case CK_Pentium4M:
2161    defineCPUMacros(Builder, "pentium4");
2162    break;
2163  case CK_Yonah:
2164  case CK_Prescott:
2165  case CK_Nocona:
2166    defineCPUMacros(Builder, "nocona");
2167    break;
2168  case CK_Core2:
2169  case CK_Penryn:
2170    defineCPUMacros(Builder, "core2");
2171    break;
2172  case CK_Atom:
2173    defineCPUMacros(Builder, "atom");
2174    break;
2175  case CK_Corei7:
2176  case CK_Corei7AVX:
2177  case CK_CoreAVXi:
2178  case CK_CoreAVX2:
2179    defineCPUMacros(Builder, "corei7");
2180    break;
2181  case CK_K6_2:
2182    Builder.defineMacro("__k6_2__");
2183    Builder.defineMacro("__tune_k6_2__");
2184    // Fallthrough
2185  case CK_K6_3:
2186    if (CPU != CK_K6_2) {  // In case of fallthrough
2187      // FIXME: GCC may be enabling these in cases where some other k6
2188      // architecture is specified but -m3dnow is explicitly provided. The
2189      // exact semantics need to be determined and emulated here.
2190      Builder.defineMacro("__k6_3__");
2191      Builder.defineMacro("__tune_k6_3__");
2192    }
2193    // Fallthrough
2194  case CK_K6:
2195    defineCPUMacros(Builder, "k6");
2196    break;
2197  case CK_Athlon:
2198  case CK_AthlonThunderbird:
2199  case CK_Athlon4:
2200  case CK_AthlonXP:
2201  case CK_AthlonMP:
2202    defineCPUMacros(Builder, "athlon");
2203    if (SSELevel != NoSSE) {
2204      Builder.defineMacro("__athlon_sse__");
2205      Builder.defineMacro("__tune_athlon_sse__");
2206    }
2207    break;
2208  case CK_K8:
2209  case CK_K8SSE3:
2210  case CK_x86_64:
2211  case CK_Opteron:
2212  case CK_OpteronSSE3:
2213  case CK_Athlon64:
2214  case CK_Athlon64SSE3:
2215  case CK_AthlonFX:
2216    defineCPUMacros(Builder, "k8");
2217    break;
2218  case CK_AMDFAM10:
2219    defineCPUMacros(Builder, "amdfam10");
2220    break;
2221  case CK_BTVER1:
2222    defineCPUMacros(Builder, "btver1");
2223    break;
2224  case CK_BDVER1:
2225    defineCPUMacros(Builder, "bdver1");
2226    break;
2227  case CK_BDVER2:
2228    defineCPUMacros(Builder, "bdver2");
2229    break;
2230  case CK_Geode:
2231    defineCPUMacros(Builder, "geode");
2232    break;
2233  }
2234
2235  // Target properties.
2236  Builder.defineMacro("__LITTLE_ENDIAN__");
2237  Builder.defineMacro("__REGISTER_PREFIX__", "");
2238
2239  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2240  // functions in glibc header files that use FP Stack inline asm which the
2241  // backend can't deal with (PR879).
2242  Builder.defineMacro("__NO_MATH_INLINES");
2243
2244  if (HasAES)
2245    Builder.defineMacro("__AES__");
2246
2247  if (HasPCLMUL)
2248    Builder.defineMacro("__PCLMUL__");
2249
2250  if (HasLZCNT)
2251    Builder.defineMacro("__LZCNT__");
2252
2253  if (HasRDRND)
2254    Builder.defineMacro("__RDRND__");
2255
2256  if (HasBMI)
2257    Builder.defineMacro("__BMI__");
2258
2259  if (HasBMI2)
2260    Builder.defineMacro("__BMI2__");
2261
2262  if (HasPOPCNT)
2263    Builder.defineMacro("__POPCNT__");
2264
2265  if (HasSSE4a)
2266    Builder.defineMacro("__SSE4A__");
2267
2268  if (HasFMA4)
2269    Builder.defineMacro("__FMA4__");
2270
2271  if (HasFMA)
2272    Builder.defineMacro("__FMA__");
2273
2274  if (HasXOP)
2275    Builder.defineMacro("__XOP__");
2276
2277  if (HasF16C)
2278    Builder.defineMacro("__F16C__");
2279
2280  // Each case falls through to the previous one here.
2281  switch (SSELevel) {
2282  case AVX2:
2283    Builder.defineMacro("__AVX2__");
2284  case AVX:
2285    Builder.defineMacro("__AVX__");
2286  case SSE42:
2287    Builder.defineMacro("__SSE4_2__");
2288  case SSE41:
2289    Builder.defineMacro("__SSE4_1__");
2290  case SSSE3:
2291    Builder.defineMacro("__SSSE3__");
2292  case SSE3:
2293    Builder.defineMacro("__SSE3__");
2294  case SSE2:
2295    Builder.defineMacro("__SSE2__");
2296    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2297  case SSE1:
2298    Builder.defineMacro("__SSE__");
2299    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2300  case NoSSE:
2301    break;
2302  }
2303
2304  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2305    switch (SSELevel) {
2306    case AVX2:
2307    case AVX:
2308    case SSE42:
2309    case SSE41:
2310    case SSSE3:
2311    case SSE3:
2312    case SSE2:
2313      Builder.defineMacro("_M_IX86_FP", Twine(2));
2314      break;
2315    case SSE1:
2316      Builder.defineMacro("_M_IX86_FP", Twine(1));
2317      break;
2318    default:
2319      Builder.defineMacro("_M_IX86_FP", Twine(0));
2320    }
2321  }
2322
2323  // Each case falls through to the previous one here.
2324  switch (MMX3DNowLevel) {
2325  case AMD3DNowAthlon:
2326    Builder.defineMacro("__3dNOW_A__");
2327  case AMD3DNow:
2328    Builder.defineMacro("__3dNOW__");
2329  case MMX:
2330    Builder.defineMacro("__MMX__");
2331  case NoMMX3DNow:
2332    break;
2333  }
2334}
2335
2336bool X86TargetInfo::hasFeature(StringRef Feature) const {
2337  return llvm::StringSwitch<bool>(Feature)
2338      .Case("aes", HasAES)
2339      .Case("avx", SSELevel >= AVX)
2340      .Case("avx2", SSELevel >= AVX2)
2341      .Case("bmi", HasBMI)
2342      .Case("bmi2", HasBMI2)
2343      .Case("fma", HasFMA)
2344      .Case("fma4", HasFMA4)
2345      .Case("lzcnt", HasLZCNT)
2346      .Case("rdrnd", HasRDRND)
2347      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2348      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2349      .Case("mmx", MMX3DNowLevel >= MMX)
2350      .Case("pclmul", HasPCLMUL)
2351      .Case("popcnt", HasPOPCNT)
2352      .Case("sse", SSELevel >= SSE1)
2353      .Case("sse2", SSELevel >= SSE2)
2354      .Case("sse3", SSELevel >= SSE3)
2355      .Case("ssse3", SSELevel >= SSSE3)
2356      .Case("sse41", SSELevel >= SSE41)
2357      .Case("sse42", SSELevel >= SSE42)
2358      .Case("sse4a", HasSSE4a)
2359      .Case("x86", true)
2360      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2361      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2362      .Case("xop", HasXOP)
2363      .Case("f16c", HasF16C)
2364      .Default(false);
2365}
2366
2367bool
2368X86TargetInfo::validateAsmConstraint(const char *&Name,
2369                                     TargetInfo::ConstraintInfo &Info) const {
2370  switch (*Name) {
2371  default: return false;
2372  case 'Y': // first letter of a pair:
2373    switch (*(Name+1)) {
2374    default: return false;
2375    case '0':  // First SSE register.
2376    case 't':  // Any SSE register, when SSE2 is enabled.
2377    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2378    case 'm':  // any MMX register, when inter-unit moves enabled.
2379      break;   // falls through to setAllowsRegister.
2380  }
2381  case 'a': // eax.
2382  case 'b': // ebx.
2383  case 'c': // ecx.
2384  case 'd': // edx.
2385  case 'S': // esi.
2386  case 'D': // edi.
2387  case 'A': // edx:eax.
2388  case 'f': // any x87 floating point stack register.
2389  case 't': // top of floating point stack.
2390  case 'u': // second from top of floating point stack.
2391  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2392  case 'y': // Any MMX register.
2393  case 'x': // Any SSE register.
2394  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2395  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2396  case 'l': // "Index" registers: any general register that can be used as an
2397            // index in a base+index memory access.
2398    Info.setAllowsRegister();
2399    return true;
2400  case 'C': // SSE floating point constant.
2401  case 'G': // x87 floating point constant.
2402  case 'e': // 32-bit signed integer constant for use with zero-extending
2403            // x86_64 instructions.
2404  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2405            // x86_64 instructions.
2406    return true;
2407  }
2408}
2409
2410
2411std::string
2412X86TargetInfo::convertConstraint(const char *&Constraint) const {
2413  switch (*Constraint) {
2414  case 'a': return std::string("{ax}");
2415  case 'b': return std::string("{bx}");
2416  case 'c': return std::string("{cx}");
2417  case 'd': return std::string("{dx}");
2418  case 'S': return std::string("{si}");
2419  case 'D': return std::string("{di}");
2420  case 'p': // address
2421    return std::string("im");
2422  case 't': // top of floating point stack.
2423    return std::string("{st}");
2424  case 'u': // second from top of floating point stack.
2425    return std::string("{st(1)}"); // second from top of floating point stack.
2426  default:
2427    return std::string(1, *Constraint);
2428  }
2429}
2430} // end anonymous namespace
2431
2432namespace {
2433// X86-32 generic target
2434class X86_32TargetInfo : public X86TargetInfo {
2435public:
2436  X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2437    DoubleAlign = LongLongAlign = 32;
2438    LongDoubleWidth = 96;
2439    LongDoubleAlign = 32;
2440    SuitableAlign = 128;
2441    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2442                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2443                        "a0:0:64-f80:32:32-n8:16:32-S128";
2444    SizeType = UnsignedInt;
2445    PtrDiffType = SignedInt;
2446    IntPtrType = SignedInt;
2447    RegParmMax = 3;
2448
2449    // Use fpret for all types.
2450    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2451                             (1 << TargetInfo::Double) |
2452                             (1 << TargetInfo::LongDouble));
2453
2454    // x86-32 has atomics up to 8 bytes
2455    // FIXME: Check that we actually have cmpxchg8b before setting
2456    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2457    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2458  }
2459  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2460    return TargetInfo::CharPtrBuiltinVaList;
2461  }
2462
2463  int getEHDataRegisterNumber(unsigned RegNo) const {
2464    if (RegNo == 0) return 0;
2465    if (RegNo == 1) return 2;
2466    return -1;
2467  }
2468};
2469} // end anonymous namespace
2470
2471namespace {
2472class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2473public:
2474  NetBSDI386TargetInfo(const std::string &triple) :
2475    NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2476  }
2477
2478  virtual unsigned getFloatEvalMethod() const {
2479    // NetBSD defaults to "double" rounding
2480    return 1;
2481  }
2482};
2483} // end anonymous namespace
2484
2485namespace {
2486class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2487public:
2488  OpenBSDI386TargetInfo(const std::string& triple) :
2489    OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2490    SizeType = UnsignedLong;
2491    IntPtrType = SignedLong;
2492    PtrDiffType = SignedLong;
2493  }
2494};
2495} // end anonymous namespace
2496
2497namespace {
2498class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2499public:
2500  BitrigI386TargetInfo(const std::string& triple) :
2501    BitrigTargetInfo<X86_32TargetInfo>(triple) {
2502    SizeType = UnsignedLong;
2503    IntPtrType = SignedLong;
2504    PtrDiffType = SignedLong;
2505  }
2506};
2507} // end anonymous namespace
2508
2509namespace {
2510class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2511public:
2512  DarwinI386TargetInfo(const std::string& triple) :
2513    DarwinTargetInfo<X86_32TargetInfo>(triple) {
2514    LongDoubleWidth = 128;
2515    LongDoubleAlign = 128;
2516    SuitableAlign = 128;
2517    MaxVectorAlign = 256;
2518    SizeType = UnsignedLong;
2519    IntPtrType = SignedLong;
2520    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2521                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2522                        "a0:0:64-f80:128:128-n8:16:32-S128";
2523    HasAlignMac68kSupport = true;
2524  }
2525
2526};
2527} // end anonymous namespace
2528
2529namespace {
2530// x86-32 Windows target
2531class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2532public:
2533  WindowsX86_32TargetInfo(const std::string& triple)
2534    : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2535    TLSSupported = false;
2536    WCharType = UnsignedShort;
2537    DoubleAlign = LongLongAlign = 64;
2538    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2539                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2540                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2541  }
2542  virtual void getTargetDefines(const LangOptions &Opts,
2543                                MacroBuilder &Builder) const {
2544    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2545  }
2546};
2547} // end anonymous namespace
2548
2549namespace {
2550
2551// x86-32 Windows Visual Studio target
2552class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2553public:
2554  VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2555    : WindowsX86_32TargetInfo(triple) {
2556    LongDoubleWidth = LongDoubleAlign = 64;
2557    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2558  }
2559  virtual void getTargetDefines(const LangOptions &Opts,
2560                                MacroBuilder &Builder) const {
2561    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2562    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2563    // The value of the following reflects processor type.
2564    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2565    // We lost the original triple, so we use the default.
2566    Builder.defineMacro("_M_IX86", "600");
2567  }
2568};
2569} // end anonymous namespace
2570
2571namespace {
2572// x86-32 MinGW target
2573class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2574public:
2575  MinGWX86_32TargetInfo(const std::string& triple)
2576    : WindowsX86_32TargetInfo(triple) {
2577  }
2578  virtual void getTargetDefines(const LangOptions &Opts,
2579                                MacroBuilder &Builder) const {
2580    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2581    DefineStd(Builder, "WIN32", Opts);
2582    DefineStd(Builder, "WINNT", Opts);
2583    Builder.defineMacro("_X86_");
2584    Builder.defineMacro("__MSVCRT__");
2585    Builder.defineMacro("__MINGW32__");
2586
2587    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2588    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2589    if (Opts.MicrosoftExt)
2590      // Provide "as-is" __declspec.
2591      Builder.defineMacro("__declspec", "__declspec");
2592    else
2593      // Provide alias of __attribute__ like mingw32-gcc.
2594      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2595  }
2596};
2597} // end anonymous namespace
2598
2599namespace {
2600// x86-32 Cygwin target
2601class CygwinX86_32TargetInfo : public X86_32TargetInfo {
2602public:
2603  CygwinX86_32TargetInfo(const std::string& triple)
2604    : X86_32TargetInfo(triple) {
2605    TLSSupported = false;
2606    WCharType = UnsignedShort;
2607    DoubleAlign = LongLongAlign = 64;
2608    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2609                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2610                        "a0:0:64-f80:32:32-n8:16:32-S32";
2611  }
2612  virtual void getTargetDefines(const LangOptions &Opts,
2613                                MacroBuilder &Builder) const {
2614    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2615    Builder.defineMacro("__CYGWIN__");
2616    Builder.defineMacro("__CYGWIN32__");
2617    DefineStd(Builder, "unix", Opts);
2618    if (Opts.CPlusPlus)
2619      Builder.defineMacro("_GNU_SOURCE");
2620  }
2621};
2622} // end anonymous namespace
2623
2624namespace {
2625// x86-32 Haiku target
2626class HaikuX86_32TargetInfo : public X86_32TargetInfo {
2627public:
2628  HaikuX86_32TargetInfo(const std::string& triple)
2629    : X86_32TargetInfo(triple) {
2630    SizeType = UnsignedLong;
2631    IntPtrType = SignedLong;
2632    PtrDiffType = SignedLong;
2633    this->UserLabelPrefix = "";
2634  }
2635  virtual void getTargetDefines(const LangOptions &Opts,
2636                                MacroBuilder &Builder) const {
2637    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2638    Builder.defineMacro("__INTEL__");
2639    Builder.defineMacro("__HAIKU__");
2640  }
2641};
2642} // end anonymous namespace
2643
2644// RTEMS Target
2645template<typename Target>
2646class RTEMSTargetInfo : public OSTargetInfo<Target> {
2647protected:
2648  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
2649                            MacroBuilder &Builder) const {
2650    // RTEMS defines; list based off of gcc output
2651
2652    Builder.defineMacro("__rtems__");
2653    Builder.defineMacro("__ELF__");
2654  }
2655public:
2656  RTEMSTargetInfo(const std::string &triple)
2657    : OSTargetInfo<Target>(triple) {
2658      this->UserLabelPrefix = "";
2659
2660      llvm::Triple Triple(triple);
2661      switch (Triple.getArch()) {
2662        default:
2663        case llvm::Triple::x86:
2664          // this->MCountName = ".mcount";
2665          break;
2666        case llvm::Triple::mips:
2667        case llvm::Triple::mipsel:
2668        case llvm::Triple::ppc:
2669        case llvm::Triple::ppc64:
2670          // this->MCountName = "_mcount";
2671          break;
2672        case llvm::Triple::arm:
2673          // this->MCountName = "__mcount";
2674          break;
2675      }
2676
2677    }
2678};
2679
2680namespace {
2681// x86-32 RTEMS target
2682class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
2683public:
2684  RTEMSX86_32TargetInfo(const std::string& triple)
2685    : X86_32TargetInfo(triple) {
2686    SizeType = UnsignedLong;
2687    IntPtrType = SignedLong;
2688    PtrDiffType = SignedLong;
2689    this->UserLabelPrefix = "";
2690  }
2691  virtual void getTargetDefines(const LangOptions &Opts,
2692                                MacroBuilder &Builder) const {
2693    X86_32TargetInfo::getTargetDefines(Opts, Builder);
2694    Builder.defineMacro("__INTEL__");
2695    Builder.defineMacro("__rtems__");
2696  }
2697};
2698} // end anonymous namespace
2699
2700namespace {
2701// x86-64 generic target
2702class X86_64TargetInfo : public X86TargetInfo {
2703public:
2704  X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
2705    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
2706    LongDoubleWidth = 128;
2707    LongDoubleAlign = 128;
2708    LargeArrayMinWidth = 128;
2709    LargeArrayAlign = 128;
2710    SuitableAlign = 128;
2711    IntMaxType = SignedLong;
2712    UIntMaxType = UnsignedLong;
2713    Int64Type = SignedLong;
2714    RegParmMax = 6;
2715
2716    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2717                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
2718                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
2719
2720    // Use fpret only for long double.
2721    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
2722
2723    // Use fp2ret for _Complex long double.
2724    ComplexLongDoubleUsesFP2Ret = true;
2725
2726    // x86-64 has atomics up to 16 bytes.
2727    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
2728    // on CPUs with cmpxchg16b
2729    MaxAtomicPromoteWidth = 128;
2730    MaxAtomicInlineWidth = 64;
2731  }
2732  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2733    return TargetInfo::X86_64ABIBuiltinVaList;
2734  }
2735
2736  int getEHDataRegisterNumber(unsigned RegNo) const {
2737    if (RegNo == 0) return 0;
2738    if (RegNo == 1) return 1;
2739    return -1;
2740  }
2741
2742  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2743    return TargetInfo::checkCallingConvention(CC);
2744  }
2745
2746  virtual CallingConv getDefaultCallingConv() const {
2747    return CC_Default;
2748  }
2749
2750};
2751} // end anonymous namespace
2752
2753namespace {
2754// x86-64 Windows target
2755class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
2756public:
2757  WindowsX86_64TargetInfo(const std::string& triple)
2758    : WindowsTargetInfo<X86_64TargetInfo>(triple) {
2759    TLSSupported = false;
2760    WCharType = UnsignedShort;
2761    LongWidth = LongAlign = 32;
2762    DoubleAlign = LongLongAlign = 64;
2763    IntMaxType = SignedLongLong;
2764    UIntMaxType = UnsignedLongLong;
2765    Int64Type = SignedLongLong;
2766    SizeType = UnsignedLongLong;
2767    PtrDiffType = SignedLongLong;
2768    IntPtrType = SignedLongLong;
2769    this->UserLabelPrefix = "";
2770  }
2771  virtual void getTargetDefines(const LangOptions &Opts,
2772                                MacroBuilder &Builder) const {
2773    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
2774    Builder.defineMacro("_WIN64");
2775  }
2776  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2777    return TargetInfo::CharPtrBuiltinVaList;
2778  }
2779};
2780} // end anonymous namespace
2781
2782namespace {
2783// x86-64 Windows Visual Studio target
2784class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
2785public:
2786  VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
2787    : WindowsX86_64TargetInfo(triple) {
2788    LongDoubleWidth = LongDoubleAlign = 64;
2789    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2790  }
2791  virtual void getTargetDefines(const LangOptions &Opts,
2792                                MacroBuilder &Builder) const {
2793    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
2794    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
2795    Builder.defineMacro("_M_X64");
2796    Builder.defineMacro("_M_AMD64");
2797  }
2798};
2799} // end anonymous namespace
2800
2801namespace {
2802// x86-64 MinGW target
2803class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
2804public:
2805  MinGWX86_64TargetInfo(const std::string& triple)
2806    : WindowsX86_64TargetInfo(triple) {
2807  }
2808  virtual void getTargetDefines(const LangOptions &Opts,
2809                                MacroBuilder &Builder) const {
2810    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
2811    DefineStd(Builder, "WIN64", Opts);
2812    Builder.defineMacro("__MSVCRT__");
2813    Builder.defineMacro("__MINGW32__");
2814    Builder.defineMacro("__MINGW64__");
2815
2816    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
2817    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
2818    if (Opts.MicrosoftExt)
2819      // Provide "as-is" __declspec.
2820      Builder.defineMacro("__declspec", "__declspec");
2821    else
2822      // Provide alias of __attribute__ like mingw32-gcc.
2823      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
2824  }
2825};
2826} // end anonymous namespace
2827
2828namespace {
2829class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
2830public:
2831  DarwinX86_64TargetInfo(const std::string& triple)
2832      : DarwinTargetInfo<X86_64TargetInfo>(triple) {
2833    Int64Type = SignedLongLong;
2834    MaxVectorAlign = 256;
2835  }
2836};
2837} // end anonymous namespace
2838
2839namespace {
2840class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
2841public:
2842  OpenBSDX86_64TargetInfo(const std::string& triple)
2843      : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
2844    IntMaxType = SignedLongLong;
2845    UIntMaxType = UnsignedLongLong;
2846    Int64Type = SignedLongLong;
2847  }
2848};
2849} // end anonymous namespace
2850
2851namespace {
2852class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
2853public:
2854  BitrigX86_64TargetInfo(const std::string& triple)
2855      : BitrigTargetInfo<X86_64TargetInfo>(triple) {
2856     IntMaxType = SignedLongLong;
2857     UIntMaxType = UnsignedLongLong;
2858     Int64Type = SignedLongLong;
2859  }
2860};
2861} // end anonymous namespace
2862
2863namespace {
2864class ARMTargetInfo : public TargetInfo {
2865  // Possible FPU choices.
2866  enum FPUMode {
2867    VFP2FPU = (1 << 0),
2868    VFP3FPU = (1 << 1),
2869    VFP4FPU = (1 << 2),
2870    NeonFPU = (1 << 3)
2871  };
2872
2873  static bool FPUModeIsVFP(FPUMode Mode) {
2874    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
2875  }
2876
2877  static const TargetInfo::GCCRegAlias GCCRegAliases[];
2878  static const char * const GCCRegNames[];
2879
2880  std::string ABI, CPU;
2881
2882  unsigned FPU : 4;
2883
2884  unsigned IsAAPCS : 1;
2885  unsigned IsThumb : 1;
2886
2887  // Initialized via features.
2888  unsigned SoftFloat : 1;
2889  unsigned SoftFloatABI : 1;
2890
2891  static const Builtin::Info BuiltinInfo[];
2892
2893public:
2894  ARMTargetInfo(const std::string &TripleStr)
2895    : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
2896  {
2897    BigEndian = false;
2898    SizeType = UnsignedInt;
2899    PtrDiffType = SignedInt;
2900    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
2901    WCharType = UnsignedInt;
2902
2903    // {} in inline assembly are neon specifiers, not assembly variant
2904    // specifiers.
2905    NoAsmVariants = true;
2906
2907    // FIXME: Should we just treat this as a feature?
2908    IsThumb = getTriple().getArchName().startswith("thumb");
2909    if (IsThumb) {
2910      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
2911      // so set preferred for small types to 32.
2912      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
2913                           "i64:64:64-f32:32:32-f64:64:64-"
2914                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
2915    } else {
2916      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2917                           "i64:64:64-f32:32:32-f64:64:64-"
2918                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
2919    }
2920
2921    // ARM targets default to using the ARM C++ ABI.
2922    CXXABI = CXXABI_ARM;
2923
2924    // ARM has atomics up to 8 bytes
2925    // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e
2926    MaxAtomicPromoteWidth = 64;
2927
2928    // Do force alignment of members that follow zero length bitfields.  If
2929    // the alignment of the zero-length bitfield is greater than the member
2930    // that follows it, `bar', `bar' will be aligned as the  type of the
2931    // zero length bitfield.
2932    UseZeroLengthBitfieldAlignment = true;
2933  }
2934  virtual const char *getABI() const { return ABI.c_str(); }
2935  virtual bool setABI(const std::string &Name) {
2936    ABI = Name;
2937
2938    // The defaults (above) are for AAPCS, check if we need to change them.
2939    //
2940    // FIXME: We need support for -meabi... we could just mangle it into the
2941    // name.
2942    if (Name == "apcs-gnu") {
2943      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
2944      SizeType = UnsignedLong;
2945
2946      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
2947      WCharType = SignedInt;
2948
2949      // Do not respect the alignment of bit-field types when laying out
2950      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
2951      UseBitFieldTypeAlignment = false;
2952
2953      /// gcc forces the alignment to 4 bytes, regardless of the type of the
2954      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
2955      /// gcc.
2956      ZeroLengthBitfieldBoundary = 32;
2957
2958      IsAAPCS = false;
2959
2960      if (IsThumb) {
2961        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
2962        // so set preferred for small types to 32.
2963        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
2964                             "i64:32:64-f32:32:32-f64:32:64-"
2965                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
2966      } else {
2967        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2968                             "i64:32:64-f32:32:32-f64:32:64-"
2969                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
2970      }
2971
2972      // FIXME: Override "preferred align" for double and long long.
2973    } else if (Name == "aapcs") {
2974      IsAAPCS = true;
2975      // FIXME: Enumerated types are variable width in straight AAPCS.
2976    } else if (Name == "aapcs-linux") {
2977      IsAAPCS = true;
2978    } else
2979      return false;
2980
2981    return true;
2982  }
2983
2984  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2985    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
2986      Features["vfp2"] = true;
2987    else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
2988             CPU == "cortex-a9" || CPU == "cortex-a9-mp")
2989      Features["neon"] = true;
2990    else if (CPU == "swift") {
2991      Features["vfp4"] = true;
2992      Features["neon"] = true;
2993    }
2994  }
2995
2996  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
2997                                 StringRef Name,
2998                                 bool Enabled) const {
2999    if (Name == "soft-float" || Name == "soft-float-abi" ||
3000        Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3001        Name == "d16" || Name == "neonfp") {
3002      Features[Name] = Enabled;
3003    } else
3004      return false;
3005
3006    return true;
3007  }
3008
3009  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3010    FPU = 0;
3011    SoftFloat = SoftFloatABI = false;
3012    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3013      if (Features[i] == "+soft-float")
3014        SoftFloat = true;
3015      else if (Features[i] == "+soft-float-abi")
3016        SoftFloatABI = true;
3017      else if (Features[i] == "+vfp2")
3018        FPU |= VFP2FPU;
3019      else if (Features[i] == "+vfp3")
3020        FPU |= VFP3FPU;
3021      else if (Features[i] == "+vfp4")
3022        FPU |= VFP4FPU;
3023      else if (Features[i] == "+neon")
3024        FPU |= NeonFPU;
3025    }
3026
3027    // Remove front-end specific options which the backend handles differently.
3028    std::vector<std::string>::iterator it;
3029    it = std::find(Features.begin(), Features.end(), "+soft-float");
3030    if (it != Features.end())
3031      Features.erase(it);
3032    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3033    if (it != Features.end())
3034      Features.erase(it);
3035  }
3036
3037  virtual bool hasFeature(StringRef Feature) const {
3038    return llvm::StringSwitch<bool>(Feature)
3039        .Case("arm", true)
3040        .Case("softfloat", SoftFloat)
3041        .Case("thumb", IsThumb)
3042        .Case("neon", FPU == NeonFPU && !SoftFloat &&
3043              StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3044        .Default(false);
3045  }
3046  // FIXME: Should we actually have some table instead of these switches?
3047  static const char *getCPUDefineSuffix(StringRef Name) {
3048    return llvm::StringSwitch<const char*>(Name)
3049      .Cases("arm8", "arm810", "4")
3050      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3051      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3052      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3053      .Case("ep9312", "4T")
3054      .Cases("arm10tdmi", "arm1020t", "5T")
3055      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3056      .Case("arm926ej-s", "5TEJ")
3057      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3058      .Cases("xscale", "iwmmxt", "5TE")
3059      .Case("arm1136j-s", "6J")
3060      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3061      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3062      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3063      .Cases("cortex-a8", "cortex-a9", "cortex-a15", "7A")
3064      .Case("cortex-a9-mp", "7F")
3065      .Case("swift", "7S")
3066      .Cases("cortex-m3", "cortex-m4", "7M")
3067      .Case("cortex-m0", "6M")
3068      .Default(0);
3069  }
3070  static const char *getCPUProfile(StringRef Name) {
3071    return llvm::StringSwitch<const char*>(Name)
3072      .Cases("cortex-a8", "cortex-a9", "A")
3073      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3074      .Default("");
3075  }
3076  virtual bool setCPU(const std::string &Name) {
3077    if (!getCPUDefineSuffix(Name))
3078      return false;
3079
3080    CPU = Name;
3081    return true;
3082  }
3083  virtual void getTargetDefines(const LangOptions &Opts,
3084                                MacroBuilder &Builder) const {
3085    // Target identification.
3086    Builder.defineMacro("__arm");
3087    Builder.defineMacro("__arm__");
3088
3089    // Target properties.
3090    Builder.defineMacro("__ARMEL__");
3091    Builder.defineMacro("__LITTLE_ENDIAN__");
3092    Builder.defineMacro("__REGISTER_PREFIX__", "");
3093
3094    StringRef CPUArch = getCPUDefineSuffix(CPU);
3095    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3096    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3097    StringRef CPUProfile = getCPUProfile(CPU);
3098    if (!CPUProfile.empty())
3099      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3100
3101    // Subtarget options.
3102
3103    // FIXME: It's more complicated than this and we don't really support
3104    // interworking.
3105    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3106      Builder.defineMacro("__THUMB_INTERWORK__");
3107
3108    if (ABI == "aapcs" || ABI == "aapcs-linux") {
3109      Builder.defineMacro("__ARM_EABI__");
3110      Builder.defineMacro("__ARM_PCS", "1");
3111
3112      if (!SoftFloat && !SoftFloatABI)
3113        Builder.defineMacro("__ARM_PCS_VFP", "1");
3114    }
3115
3116    if (SoftFloat)
3117      Builder.defineMacro("__SOFTFP__");
3118
3119    if (CPU == "xscale")
3120      Builder.defineMacro("__XSCALE__");
3121
3122    bool IsARMv7 = CPUArch.startswith("7");
3123    if (IsThumb) {
3124      Builder.defineMacro("__THUMBEL__");
3125      Builder.defineMacro("__thumb__");
3126      if (CPUArch == "6T2" || IsARMv7)
3127        Builder.defineMacro("__thumb2__");
3128    }
3129
3130    // Note, this is always on in gcc, even though it doesn't make sense.
3131    Builder.defineMacro("__APCS_32__");
3132
3133    if (FPUModeIsVFP((FPUMode) FPU)) {
3134      Builder.defineMacro("__VFP_FP__");
3135      if (FPU & VFP2FPU)
3136        Builder.defineMacro("__ARM_VFPV2__");
3137      if (FPU & VFP3FPU)
3138        Builder.defineMacro("__ARM_VFPV3__");
3139      if (FPU & VFP4FPU)
3140        Builder.defineMacro("__ARM_VFPV4__");
3141    }
3142
3143    // This only gets set when Neon instructions are actually available, unlike
3144    // the VFP define, hence the soft float and arch check. This is subtly
3145    // different from gcc, we follow the intent which was that it should be set
3146    // when Neon instructions are actually available.
3147    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3148      Builder.defineMacro("__ARM_NEON__");
3149  }
3150  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3151                                 unsigned &NumRecords) const {
3152    Records = BuiltinInfo;
3153    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3154  }
3155  virtual bool isCLZForZeroUndef() const { return false; }
3156  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3157    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3158  }
3159  virtual void getGCCRegNames(const char * const *&Names,
3160                              unsigned &NumNames) const;
3161  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3162                                unsigned &NumAliases) const;
3163  virtual bool validateAsmConstraint(const char *&Name,
3164                                     TargetInfo::ConstraintInfo &Info) const {
3165    switch (*Name) {
3166    default: break;
3167    case 'l': // r0-r7
3168    case 'h': // r8-r15
3169    case 'w': // VFP Floating point register single precision
3170    case 'P': // VFP Floating point register double precision
3171      Info.setAllowsRegister();
3172      return true;
3173    case 'Q': // A memory address that is a single base register.
3174      Info.setAllowsMemory();
3175      return true;
3176    case 'U': // a memory reference...
3177      switch (Name[1]) {
3178      case 'q': // ...ARMV4 ldrsb
3179      case 'v': // ...VFP load/store (reg+constant offset)
3180      case 'y': // ...iWMMXt load/store
3181      case 't': // address valid for load/store opaque types wider
3182	        // than 128-bits
3183      case 'n': // valid address for Neon doubleword vector load/store
3184      case 'm': // valid address for Neon element and structure load/store
3185      case 's': // valid address for non-offset loads/stores of quad-word
3186	        // values in four ARM registers
3187        Info.setAllowsMemory();
3188        Name++;
3189        return true;
3190      }
3191    }
3192    return false;
3193  }
3194  virtual std::string convertConstraint(const char *&Constraint) const {
3195    std::string R;
3196    switch (*Constraint) {
3197    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3198      R = std::string("^") + std::string(Constraint, 2);
3199      Constraint++;
3200      break;
3201    case 'p': // 'p' should be translated to 'r' by default.
3202      R = std::string("r");
3203      break;
3204    default:
3205      return std::string(1, *Constraint);
3206    }
3207    return R;
3208  }
3209  virtual const char *getClobbers() const {
3210    // FIXME: Is this really right?
3211    return "";
3212  }
3213
3214  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3215    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3216  }
3217};
3218
3219const char * const ARMTargetInfo::GCCRegNames[] = {
3220  // Integer registers
3221  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3222  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3223
3224  // Float registers
3225  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3226  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3227  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3228  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3229
3230  // Double registers
3231  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3232  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3233  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3234  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3235
3236  // Quad registers
3237  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3238  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3239};
3240
3241void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3242                                   unsigned &NumNames) const {
3243  Names = GCCRegNames;
3244  NumNames = llvm::array_lengthof(GCCRegNames);
3245}
3246
3247const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3248  { { "a1" }, "r0" },
3249  { { "a2" }, "r1" },
3250  { { "a3" }, "r2" },
3251  { { "a4" }, "r3" },
3252  { { "v1" }, "r4" },
3253  { { "v2" }, "r5" },
3254  { { "v3" }, "r6" },
3255  { { "v4" }, "r7" },
3256  { { "v5" }, "r8" },
3257  { { "v6", "rfp" }, "r9" },
3258  { { "sl" }, "r10" },
3259  { { "fp" }, "r11" },
3260  { { "ip" }, "r12" },
3261  { { "r13" }, "sp" },
3262  { { "r14" }, "lr" },
3263  { { "r15" }, "pc" },
3264  // The S, D and Q registers overlap, but aren't really aliases; we
3265  // don't want to substitute one of these for a different-sized one.
3266};
3267
3268void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3269                                       unsigned &NumAliases) const {
3270  Aliases = GCCRegAliases;
3271  NumAliases = llvm::array_lengthof(GCCRegAliases);
3272}
3273
3274const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3275#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3276#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3277                                              ALL_LANGUAGES },
3278#include "clang/Basic/BuiltinsARM.def"
3279};
3280} // end anonymous namespace.
3281
3282namespace {
3283class DarwinARMTargetInfo :
3284  public DarwinTargetInfo<ARMTargetInfo> {
3285protected:
3286  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3287                            MacroBuilder &Builder) const {
3288    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
3289  }
3290
3291public:
3292  DarwinARMTargetInfo(const std::string& triple)
3293    : DarwinTargetInfo<ARMTargetInfo>(triple) {
3294    HasAlignMac68kSupport = true;
3295    // iOS always has 64-bit atomic instructions.
3296    // FIXME: This should be based off of the target features in ARMTargetInfo.
3297    MaxAtomicInlineWidth = 64;
3298  }
3299};
3300} // end anonymous namespace.
3301
3302
3303namespace {
3304// Hexagon abstract base class
3305class HexagonTargetInfo : public TargetInfo {
3306  static const Builtin::Info BuiltinInfo[];
3307  static const char * const GCCRegNames[];
3308  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3309  std::string CPU;
3310public:
3311  HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
3312    BigEndian = false;
3313    DescriptionString = ("e-p:32:32:32-"
3314                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32"
3315                         "f64:64:64-f32:32:32-a0:0-n32");
3316
3317    // {} in inline assembly are packet specifiers, not assembly variant
3318    // specifiers.
3319    NoAsmVariants = true;
3320  }
3321
3322  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3323                                 unsigned &NumRecords) const {
3324    Records = BuiltinInfo;
3325    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
3326  }
3327
3328  virtual bool validateAsmConstraint(const char *&Name,
3329                                     TargetInfo::ConstraintInfo &Info) const {
3330    return true;
3331  }
3332
3333  virtual void getTargetDefines(const LangOptions &Opts,
3334                                MacroBuilder &Builder) const;
3335
3336  virtual bool hasFeature(StringRef Feature) const {
3337    return Feature == "hexagon";
3338  }
3339
3340  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3341    return TargetInfo::CharPtrBuiltinVaList;
3342  }
3343  virtual void getGCCRegNames(const char * const *&Names,
3344                              unsigned &NumNames) const;
3345  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3346                                unsigned &NumAliases) const;
3347  virtual const char *getClobbers() const {
3348    return "";
3349  }
3350
3351  static const char *getHexagonCPUSuffix(StringRef Name) {
3352    return llvm::StringSwitch<const char*>(Name)
3353      .Case("hexagonv2", "2")
3354      .Case("hexagonv3", "3")
3355      .Case("hexagonv4", "4")
3356      .Case("hexagonv5", "5")
3357      .Default(0);
3358  }
3359
3360  virtual bool setCPU(const std::string &Name) {
3361    if (!getHexagonCPUSuffix(Name))
3362      return false;
3363
3364    CPU = Name;
3365    return true;
3366  }
3367};
3368
3369void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
3370                                MacroBuilder &Builder) const {
3371  Builder.defineMacro("qdsp6");
3372  Builder.defineMacro("__qdsp6", "1");
3373  Builder.defineMacro("__qdsp6__", "1");
3374
3375  Builder.defineMacro("hexagon");
3376  Builder.defineMacro("__hexagon", "1");
3377  Builder.defineMacro("__hexagon__", "1");
3378
3379  if(CPU == "hexagonv1") {
3380    Builder.defineMacro("__HEXAGON_V1__");
3381    Builder.defineMacro("__HEXAGON_ARCH__", "1");
3382    if(Opts.HexagonQdsp6Compat) {
3383      Builder.defineMacro("__QDSP6_V1__");
3384      Builder.defineMacro("__QDSP6_ARCH__", "1");
3385    }
3386  }
3387  else if(CPU == "hexagonv2") {
3388    Builder.defineMacro("__HEXAGON_V2__");
3389    Builder.defineMacro("__HEXAGON_ARCH__", "2");
3390    if(Opts.HexagonQdsp6Compat) {
3391      Builder.defineMacro("__QDSP6_V2__");
3392      Builder.defineMacro("__QDSP6_ARCH__", "2");
3393    }
3394  }
3395  else if(CPU == "hexagonv3") {
3396    Builder.defineMacro("__HEXAGON_V3__");
3397    Builder.defineMacro("__HEXAGON_ARCH__", "3");
3398    if(Opts.HexagonQdsp6Compat) {
3399      Builder.defineMacro("__QDSP6_V3__");
3400      Builder.defineMacro("__QDSP6_ARCH__", "3");
3401    }
3402  }
3403  else if(CPU == "hexagonv4") {
3404    Builder.defineMacro("__HEXAGON_V4__");
3405    Builder.defineMacro("__HEXAGON_ARCH__", "4");
3406    if(Opts.HexagonQdsp6Compat) {
3407      Builder.defineMacro("__QDSP6_V4__");
3408      Builder.defineMacro("__QDSP6_ARCH__", "4");
3409    }
3410  }
3411  else if(CPU == "hexagonv5") {
3412    Builder.defineMacro("__HEXAGON_V5__");
3413    Builder.defineMacro("__HEXAGON_ARCH__", "5");
3414    if(Opts.HexagonQdsp6Compat) {
3415      Builder.defineMacro("__QDSP6_V5__");
3416      Builder.defineMacro("__QDSP6_ARCH__", "5");
3417    }
3418  }
3419}
3420
3421const char * const HexagonTargetInfo::GCCRegNames[] = {
3422  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3423  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3424  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3425  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
3426  "p0", "p1", "p2", "p3",
3427  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
3428};
3429
3430void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
3431                                   unsigned &NumNames) const {
3432  Names = GCCRegNames;
3433  NumNames = llvm::array_lengthof(GCCRegNames);
3434}
3435
3436
3437const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
3438  { { "sp" }, "r29" },
3439  { { "fp" }, "r30" },
3440  { { "lr" }, "r31" },
3441 };
3442
3443void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3444                                     unsigned &NumAliases) const {
3445  Aliases = GCCRegAliases;
3446  NumAliases = llvm::array_lengthof(GCCRegAliases);
3447}
3448
3449
3450const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
3451#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3452#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3453                                              ALL_LANGUAGES },
3454#include "clang/Basic/BuiltinsHexagon.def"
3455};
3456}
3457
3458
3459namespace {
3460class SparcV8TargetInfo : public TargetInfo {
3461  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3462  static const char * const GCCRegNames[];
3463  bool SoftFloat;
3464public:
3465  SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) {
3466    // FIXME: Support Sparc quad-precision long double?
3467    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3468                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
3469  }
3470  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3471                                 StringRef Name,
3472                                 bool Enabled) const {
3473    if (Name == "soft-float")
3474      Features[Name] = Enabled;
3475    else
3476      return false;
3477
3478    return true;
3479  }
3480  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3481    SoftFloat = false;
3482    for (unsigned i = 0, e = Features.size(); i != e; ++i)
3483      if (Features[i] == "+soft-float")
3484        SoftFloat = true;
3485  }
3486  virtual void getTargetDefines(const LangOptions &Opts,
3487                                MacroBuilder &Builder) const {
3488    DefineStd(Builder, "sparc", Opts);
3489    Builder.defineMacro("__sparcv8");
3490    Builder.defineMacro("__REGISTER_PREFIX__", "");
3491
3492    if (SoftFloat)
3493      Builder.defineMacro("SOFT_FLOAT", "1");
3494  }
3495
3496  virtual bool hasFeature(StringRef Feature) const {
3497    return llvm::StringSwitch<bool>(Feature)
3498             .Case("softfloat", SoftFloat)
3499             .Case("sparc", true)
3500             .Default(false);
3501  }
3502
3503  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3504                                 unsigned &NumRecords) const {
3505    // FIXME: Implement!
3506  }
3507  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3508    return TargetInfo::VoidPtrBuiltinVaList;
3509  }
3510  virtual void getGCCRegNames(const char * const *&Names,
3511                              unsigned &NumNames) const;
3512  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3513                                unsigned &NumAliases) const;
3514  virtual bool validateAsmConstraint(const char *&Name,
3515                                     TargetInfo::ConstraintInfo &info) const {
3516    // FIXME: Implement!
3517    return false;
3518  }
3519  virtual const char *getClobbers() const {
3520    // FIXME: Implement!
3521    return "";
3522  }
3523};
3524
3525const char * const SparcV8TargetInfo::GCCRegNames[] = {
3526  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3527  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3528  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3529  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3530};
3531
3532void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names,
3533                                       unsigned &NumNames) const {
3534  Names = GCCRegNames;
3535  NumNames = llvm::array_lengthof(GCCRegNames);
3536}
3537
3538const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = {
3539  { { "g0" }, "r0" },
3540  { { "g1" }, "r1" },
3541  { { "g2" }, "r2" },
3542  { { "g3" }, "r3" },
3543  { { "g4" }, "r4" },
3544  { { "g5" }, "r5" },
3545  { { "g6" }, "r6" },
3546  { { "g7" }, "r7" },
3547  { { "o0" }, "r8" },
3548  { { "o1" }, "r9" },
3549  { { "o2" }, "r10" },
3550  { { "o3" }, "r11" },
3551  { { "o4" }, "r12" },
3552  { { "o5" }, "r13" },
3553  { { "o6", "sp" }, "r14" },
3554  { { "o7" }, "r15" },
3555  { { "l0" }, "r16" },
3556  { { "l1" }, "r17" },
3557  { { "l2" }, "r18" },
3558  { { "l3" }, "r19" },
3559  { { "l4" }, "r20" },
3560  { { "l5" }, "r21" },
3561  { { "l6" }, "r22" },
3562  { { "l7" }, "r23" },
3563  { { "i0" }, "r24" },
3564  { { "i1" }, "r25" },
3565  { { "i2" }, "r26" },
3566  { { "i3" }, "r27" },
3567  { { "i4" }, "r28" },
3568  { { "i5" }, "r29" },
3569  { { "i6", "fp" }, "r30" },
3570  { { "i7" }, "r31" },
3571};
3572
3573void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3574                                         unsigned &NumAliases) const {
3575  Aliases = GCCRegAliases;
3576  NumAliases = llvm::array_lengthof(GCCRegAliases);
3577}
3578} // end anonymous namespace.
3579
3580namespace {
3581class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
3582public:
3583  AuroraUXSparcV8TargetInfo(const std::string& triple) :
3584      AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
3585    SizeType = UnsignedInt;
3586    PtrDiffType = SignedInt;
3587  }
3588};
3589class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
3590public:
3591  SolarisSparcV8TargetInfo(const std::string& triple) :
3592      SolarisTargetInfo<SparcV8TargetInfo>(triple) {
3593    SizeType = UnsignedInt;
3594    PtrDiffType = SignedInt;
3595  }
3596};
3597} // end anonymous namespace.
3598
3599namespace {
3600  class MSP430TargetInfo : public TargetInfo {
3601    static const char * const GCCRegNames[];
3602  public:
3603    MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
3604      BigEndian = false;
3605      TLSSupported = false;
3606      IntWidth = 16; IntAlign = 16;
3607      LongWidth = 32; LongLongWidth = 64;
3608      LongAlign = LongLongAlign = 16;
3609      PointerWidth = 16; PointerAlign = 16;
3610      SuitableAlign = 16;
3611      SizeType = UnsignedInt;
3612      IntMaxType = SignedLong;
3613      UIntMaxType = UnsignedLong;
3614      IntPtrType = SignedShort;
3615      PtrDiffType = SignedInt;
3616      SigAtomicType = SignedLong;
3617      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
3618   }
3619    virtual void getTargetDefines(const LangOptions &Opts,
3620                                  MacroBuilder &Builder) const {
3621      Builder.defineMacro("MSP430");
3622      Builder.defineMacro("__MSP430__");
3623      // FIXME: defines for different 'flavours' of MCU
3624    }
3625    virtual void getTargetBuiltins(const Builtin::Info *&Records,
3626                                   unsigned &NumRecords) const {
3627     // FIXME: Implement.
3628      Records = 0;
3629      NumRecords = 0;
3630    }
3631    virtual bool hasFeature(StringRef Feature) const {
3632      return Feature == "msp430";
3633    }
3634    virtual void getGCCRegNames(const char * const *&Names,
3635                                unsigned &NumNames) const;
3636    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3637                                  unsigned &NumAliases) const {
3638      // No aliases.
3639      Aliases = 0;
3640      NumAliases = 0;
3641    }
3642    virtual bool validateAsmConstraint(const char *&Name,
3643                                       TargetInfo::ConstraintInfo &info) const {
3644      // No target constraints for now.
3645      return false;
3646    }
3647    virtual const char *getClobbers() const {
3648      // FIXME: Is this really right?
3649      return "";
3650    }
3651    virtual BuiltinVaListKind getBuiltinVaListKind() const {
3652      // FIXME: implement
3653      return TargetInfo::CharPtrBuiltinVaList;
3654   }
3655  };
3656
3657  const char * const MSP430TargetInfo::GCCRegNames[] = {
3658    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3659    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3660  };
3661
3662  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
3663                                        unsigned &NumNames) const {
3664    Names = GCCRegNames;
3665    NumNames = llvm::array_lengthof(GCCRegNames);
3666  }
3667}
3668
3669namespace {
3670
3671  // LLVM and Clang cannot be used directly to output native binaries for
3672  // target, but is used to compile C code to llvm bitcode with correct
3673  // type and alignment information.
3674  //
3675  // TCE uses the llvm bitcode as input and uses it for generating customized
3676  // target processor and program binary. TCE co-design environment is
3677  // publicly available in http://tce.cs.tut.fi
3678
3679  static const unsigned TCEOpenCLAddrSpaceMap[] = {
3680      3, // opencl_global
3681      4, // opencl_local
3682      5, // opencl_constant
3683      0, // cuda_device
3684      0, // cuda_constant
3685      0  // cuda_shared
3686  };
3687
3688  class TCETargetInfo : public TargetInfo{
3689  public:
3690    TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
3691      TLSSupported = false;
3692      IntWidth = 32;
3693      LongWidth = LongLongWidth = 32;
3694      PointerWidth = 32;
3695      IntAlign = 32;
3696      LongAlign = LongLongAlign = 32;
3697      PointerAlign = 32;
3698      SuitableAlign = 32;
3699      SizeType = UnsignedInt;
3700      IntMaxType = SignedLong;
3701      UIntMaxType = UnsignedLong;
3702      IntPtrType = SignedInt;
3703      PtrDiffType = SignedInt;
3704      FloatWidth = 32;
3705      FloatAlign = 32;
3706      DoubleWidth = 32;
3707      DoubleAlign = 32;
3708      LongDoubleWidth = 32;
3709      LongDoubleAlign = 32;
3710      FloatFormat = &llvm::APFloat::IEEEsingle;
3711      DoubleFormat = &llvm::APFloat::IEEEsingle;
3712      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
3713      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
3714                          "i16:16:32-i32:32:32-i64:32:32-"
3715                          "f32:32:32-f64:32:32-v64:32:32-"
3716                          "v128:32:32-a0:0:32-n32";
3717      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
3718    }
3719
3720    virtual void getTargetDefines(const LangOptions &Opts,
3721                                  MacroBuilder &Builder) const {
3722      DefineStd(Builder, "tce", Opts);
3723      Builder.defineMacro("__TCE__");
3724      Builder.defineMacro("__TCE_V1__");
3725    }
3726    virtual bool hasFeature(StringRef Feature) const {
3727      return Feature == "tce";
3728    }
3729
3730    virtual void getTargetBuiltins(const Builtin::Info *&Records,
3731                                   unsigned &NumRecords) const {}
3732    virtual const char *getClobbers() const {
3733      return "";
3734    }
3735    virtual BuiltinVaListKind getBuiltinVaListKind() const {
3736      return TargetInfo::VoidPtrBuiltinVaList;
3737    }
3738    virtual void getGCCRegNames(const char * const *&Names,
3739                                unsigned &NumNames) const {}
3740    virtual bool validateAsmConstraint(const char *&Name,
3741                                       TargetInfo::ConstraintInfo &info) const {
3742      return true;
3743    }
3744    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3745                                  unsigned &NumAliases) const {}
3746  };
3747}
3748
3749namespace {
3750class MipsTargetInfoBase : public TargetInfo {
3751  static const Builtin::Info BuiltinInfo[];
3752  std::string CPU;
3753  bool IsMips16;
3754  enum MipsFloatABI {
3755    HardFloat, SingleFloat, SoftFloat
3756  } FloatABI;
3757  enum DspRevEnum {
3758    NoDSP, DSP1, DSP2
3759  } DspRev;
3760
3761protected:
3762  std::string ABI;
3763
3764public:
3765  MipsTargetInfoBase(const std::string& triple,
3766                     const std::string& ABIStr,
3767                     const std::string& CPUStr)
3768    : TargetInfo(triple),
3769      CPU(CPUStr),
3770      IsMips16(false),
3771      FloatABI(HardFloat),
3772      DspRev(NoDSP),
3773      ABI(ABIStr)
3774  {}
3775
3776  virtual const char *getABI() const { return ABI.c_str(); }
3777  virtual bool setABI(const std::string &Name) = 0;
3778  virtual bool setCPU(const std::string &Name) {
3779    CPU = Name;
3780    return true;
3781  }
3782  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3783    Features[ABI] = true;
3784    Features[CPU] = true;
3785  }
3786
3787  virtual void getTargetDefines(const LangOptions &Opts,
3788                                MacroBuilder &Builder) const {
3789    DefineStd(Builder, "mips", Opts);
3790    Builder.defineMacro("_mips");
3791    Builder.defineMacro("__REGISTER_PREFIX__", "");
3792
3793    switch (FloatABI) {
3794    case HardFloat:
3795      Builder.defineMacro("__mips_hard_float", Twine(1));
3796      break;
3797    case SingleFloat:
3798      Builder.defineMacro("__mips_hard_float", Twine(1));
3799      Builder.defineMacro("__mips_single_float", Twine(1));
3800      break;
3801    case SoftFloat:
3802      Builder.defineMacro("__mips_soft_float", Twine(1));
3803      break;
3804    }
3805
3806    if (IsMips16)
3807      Builder.defineMacro("__mips16", Twine(1));
3808
3809    switch (DspRev) {
3810    default:
3811      break;
3812    case DSP1:
3813      Builder.defineMacro("__mips_dsp_rev", Twine(1));
3814      Builder.defineMacro("__mips_dsp", Twine(1));
3815      break;
3816    case DSP2:
3817      Builder.defineMacro("__mips_dsp_rev", Twine(2));
3818      Builder.defineMacro("__mips_dspr2", Twine(1));
3819      Builder.defineMacro("__mips_dsp", Twine(1));
3820      break;
3821    }
3822
3823    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
3824    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
3825    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
3826
3827    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
3828    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
3829  }
3830
3831  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3832                                 unsigned &NumRecords) const {
3833    Records = BuiltinInfo;
3834    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
3835  }
3836  virtual bool hasFeature(StringRef Feature) const {
3837    return Feature == "mips";
3838  }
3839  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3840    return TargetInfo::VoidPtrBuiltinVaList;
3841  }
3842  virtual void getGCCRegNames(const char * const *&Names,
3843                              unsigned &NumNames) const {
3844    static const char * const GCCRegNames[] = {
3845      // CPU register names
3846      // Must match second column of GCCRegAliases
3847      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3848      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3849      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3850      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
3851      // Floating point register names
3852      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
3853      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
3854      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
3855      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
3856      // Hi/lo and condition register names
3857      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
3858      "$fcc5","$fcc6","$fcc7"
3859    };
3860    Names = GCCRegNames;
3861    NumNames = llvm::array_lengthof(GCCRegNames);
3862  }
3863  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3864                                unsigned &NumAliases) const = 0;
3865  virtual bool validateAsmConstraint(const char *&Name,
3866                                     TargetInfo::ConstraintInfo &Info) const {
3867    switch (*Name) {
3868    default:
3869      return false;
3870
3871    case 'r': // CPU registers.
3872    case 'd': // Equivalent to "r" unless generating MIPS16 code.
3873    case 'y': // Equivalent to "r", backwards compatibility only.
3874    case 'f': // floating-point registers.
3875    case 'c': // $25 for indirect jumps
3876    case 'l': // lo register
3877    case 'x': // hilo register pair
3878      Info.setAllowsRegister();
3879      return true;
3880    }
3881  }
3882
3883  virtual const char *getClobbers() const {
3884    // FIXME: Implement!
3885    return "";
3886  }
3887
3888  virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3889                                 StringRef Name,
3890                                 bool Enabled) const {
3891    if (Name == "soft-float" || Name == "single-float" ||
3892        Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
3893        Name == "mips32" || Name == "mips32r2" ||
3894        Name == "mips64" || Name == "mips64r2" ||
3895        Name == "mips16" || Name == "dsp" || Name == "dspr2") {
3896      Features[Name] = Enabled;
3897      return true;
3898    }
3899    return false;
3900  }
3901
3902  virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3903    IsMips16 = false;
3904    FloatABI = HardFloat;
3905    DspRev = NoDSP;
3906
3907    for (std::vector<std::string>::iterator it = Features.begin(),
3908         ie = Features.end(); it != ie; ++it) {
3909      if (*it == "+single-float")
3910        FloatABI = SingleFloat;
3911      else if (*it == "+soft-float")
3912        FloatABI = SoftFloat;
3913      else if (*it == "+mips16")
3914        IsMips16 = true;
3915      else if (*it == "+dsp")
3916        DspRev = std::max(DspRev, DSP1);
3917      else if (*it == "+dspr2")
3918        DspRev = std::max(DspRev, DSP2);
3919    }
3920
3921    // Remove front-end specific option.
3922    std::vector<std::string>::iterator it =
3923      std::find(Features.begin(), Features.end(), "+soft-float");
3924    if (it != Features.end())
3925      Features.erase(it);
3926  }
3927};
3928
3929const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
3930#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3931#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3932                                              ALL_LANGUAGES },
3933#include "clang/Basic/BuiltinsMips.def"
3934};
3935
3936class Mips32TargetInfoBase : public MipsTargetInfoBase {
3937public:
3938  Mips32TargetInfoBase(const std::string& triple) :
3939    MipsTargetInfoBase(triple, "o32", "mips32") {
3940    SizeType = UnsignedInt;
3941    PtrDiffType = SignedInt;
3942  }
3943  virtual bool setABI(const std::string &Name) {
3944    if ((Name == "o32") || (Name == "eabi")) {
3945      ABI = Name;
3946      return true;
3947    } else
3948      return false;
3949  }
3950  virtual void getTargetDefines(const LangOptions &Opts,
3951                                MacroBuilder &Builder) const {
3952    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
3953
3954    if (ABI == "o32") {
3955      Builder.defineMacro("__mips_o32");
3956      Builder.defineMacro("_ABIO32", "1");
3957      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
3958    }
3959    else if (ABI == "eabi")
3960      Builder.defineMacro("__mips_eabi");
3961    else
3962      llvm_unreachable("Invalid ABI for Mips32.");
3963  }
3964  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3965                                unsigned &NumAliases) const {
3966    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
3967      { { "at" },  "$1" },
3968      { { "v0" },  "$2" },
3969      { { "v1" },  "$3" },
3970      { { "a0" },  "$4" },
3971      { { "a1" },  "$5" },
3972      { { "a2" },  "$6" },
3973      { { "a3" },  "$7" },
3974      { { "t0" },  "$8" },
3975      { { "t1" },  "$9" },
3976      { { "t2" }, "$10" },
3977      { { "t3" }, "$11" },
3978      { { "t4" }, "$12" },
3979      { { "t5" }, "$13" },
3980      { { "t6" }, "$14" },
3981      { { "t7" }, "$15" },
3982      { { "s0" }, "$16" },
3983      { { "s1" }, "$17" },
3984      { { "s2" }, "$18" },
3985      { { "s3" }, "$19" },
3986      { { "s4" }, "$20" },
3987      { { "s5" }, "$21" },
3988      { { "s6" }, "$22" },
3989      { { "s7" }, "$23" },
3990      { { "t8" }, "$24" },
3991      { { "t9" }, "$25" },
3992      { { "k0" }, "$26" },
3993      { { "k1" }, "$27" },
3994      { { "gp" }, "$28" },
3995      { { "sp","$sp" }, "$29" },
3996      { { "fp","$fp" }, "$30" },
3997      { { "ra" }, "$31" }
3998    };
3999    Aliases = GCCRegAliases;
4000    NumAliases = llvm::array_lengthof(GCCRegAliases);
4001  }
4002};
4003
4004class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4005public:
4006  Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4007    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4008                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4009  }
4010  virtual void getTargetDefines(const LangOptions &Opts,
4011                                MacroBuilder &Builder) const {
4012    DefineStd(Builder, "MIPSEB", Opts);
4013    Builder.defineMacro("_MIPSEB");
4014    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4015  }
4016};
4017
4018class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4019public:
4020  Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4021    BigEndian = false;
4022    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4023                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32";
4024  }
4025  virtual void getTargetDefines(const LangOptions &Opts,
4026                                MacroBuilder &Builder) const {
4027    DefineStd(Builder, "MIPSEL", Opts);
4028    Builder.defineMacro("_MIPSEL");
4029    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4030  }
4031};
4032
4033class Mips64TargetInfoBase : public MipsTargetInfoBase {
4034  virtual void SetDescriptionString(const std::string &Name) = 0;
4035public:
4036  Mips64TargetInfoBase(const std::string& triple) :
4037    MipsTargetInfoBase(triple, "n64", "mips64") {
4038    LongWidth = LongAlign = 64;
4039    PointerWidth = PointerAlign = 64;
4040    LongDoubleWidth = LongDoubleAlign = 128;
4041    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4042    SuitableAlign = 128;
4043  }
4044  virtual bool setABI(const std::string &Name) {
4045    SetDescriptionString(Name);
4046
4047    if (Name != "n32" && Name != "n64")
4048      return false;
4049
4050    ABI = Name;
4051
4052    if (Name == "n32") {
4053      LongWidth = LongAlign = 32;
4054      PointerWidth = PointerAlign = 32;
4055    }
4056
4057    return true;
4058  }
4059  virtual void getTargetDefines(const LangOptions &Opts,
4060                                MacroBuilder &Builder) const {
4061    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4062
4063    Builder.defineMacro("__mips64");
4064    Builder.defineMacro("__mips64__");
4065
4066    if (ABI == "n32") {
4067      Builder.defineMacro("__mips_n32");
4068      Builder.defineMacro("_ABIN32", "2");
4069      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4070    }
4071    else if (ABI == "n64") {
4072      Builder.defineMacro("__mips_n64");
4073      Builder.defineMacro("_ABI64", "3");
4074      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4075    }
4076    else
4077      llvm_unreachable("Invalid ABI for Mips64.");
4078  }
4079  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4080                                unsigned &NumAliases) const {
4081    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4082      { { "at" },  "$1" },
4083      { { "v0" },  "$2" },
4084      { { "v1" },  "$3" },
4085      { { "a0" },  "$4" },
4086      { { "a1" },  "$5" },
4087      { { "a2" },  "$6" },
4088      { { "a3" },  "$7" },
4089      { { "a4" },  "$8" },
4090      { { "a5" },  "$9" },
4091      { { "a6" }, "$10" },
4092      { { "a7" }, "$11" },
4093      { { "t0" }, "$12" },
4094      { { "t1" }, "$13" },
4095      { { "t2" }, "$14" },
4096      { { "t3" }, "$15" },
4097      { { "s0" }, "$16" },
4098      { { "s1" }, "$17" },
4099      { { "s2" }, "$18" },
4100      { { "s3" }, "$19" },
4101      { { "s4" }, "$20" },
4102      { { "s5" }, "$21" },
4103      { { "s6" }, "$22" },
4104      { { "s7" }, "$23" },
4105      { { "t8" }, "$24" },
4106      { { "t9" }, "$25" },
4107      { { "k0" }, "$26" },
4108      { { "k1" }, "$27" },
4109      { { "gp" }, "$28" },
4110      { { "sp","$sp" }, "$29" },
4111      { { "fp","$fp" }, "$30" },
4112      { { "ra" }, "$31" }
4113    };
4114    Aliases = GCCRegAliases;
4115    NumAliases = llvm::array_lengthof(GCCRegAliases);
4116  }
4117};
4118
4119class Mips64EBTargetInfo : public Mips64TargetInfoBase {
4120  virtual void SetDescriptionString(const std::string &Name) {
4121    // Change DescriptionString only if ABI is n32.
4122    if (Name == "n32")
4123      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4124                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4125                          "v64:64:64-n32";
4126  }
4127public:
4128  Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4129    // Default ABI is n64.
4130    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4131                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4132                        "v64:64:64-n32";
4133  }
4134  virtual void getTargetDefines(const LangOptions &Opts,
4135                                MacroBuilder &Builder) const {
4136    DefineStd(Builder, "MIPSEB", Opts);
4137    Builder.defineMacro("_MIPSEB");
4138    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4139  }
4140};
4141
4142class Mips64ELTargetInfo : public Mips64TargetInfoBase {
4143  virtual void SetDescriptionString(const std::string &Name) {
4144    // Change DescriptionString only if ABI is n32.
4145    if (Name == "n32")
4146      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4147                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
4148                          "-v64:64:64-n32";
4149  }
4150public:
4151  Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
4152    // Default ABI is n64.
4153    BigEndian = false;
4154    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4155                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
4156                        "v64:64:64-n32";
4157  }
4158  virtual void getTargetDefines(const LangOptions &Opts,
4159                                MacroBuilder &Builder) const {
4160    DefineStd(Builder, "MIPSEL", Opts);
4161    Builder.defineMacro("_MIPSEL");
4162    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
4163  }
4164};
4165} // end anonymous namespace.
4166
4167namespace {
4168class PNaClTargetInfo : public TargetInfo {
4169public:
4170  PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
4171    BigEndian = false;
4172    this->UserLabelPrefix = "";
4173    this->LongAlign = 32;
4174    this->LongWidth = 32;
4175    this->PointerAlign = 32;
4176    this->PointerWidth = 32;
4177    this->IntMaxType = TargetInfo::SignedLongLong;
4178    this->UIntMaxType = TargetInfo::UnsignedLongLong;
4179    this->Int64Type = TargetInfo::SignedLongLong;
4180    this->DoubleAlign = 64;
4181    this->LongDoubleWidth = 64;
4182    this->LongDoubleAlign = 64;
4183    this->SizeType = TargetInfo::UnsignedInt;
4184    this->PtrDiffType = TargetInfo::SignedInt;
4185    this->IntPtrType = TargetInfo::SignedInt;
4186    this->RegParmMax = 2;
4187    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
4188                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
4189  }
4190
4191  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4192  }
4193  virtual void getArchDefines(const LangOptions &Opts,
4194                              MacroBuilder &Builder) const {
4195    Builder.defineMacro("__le32__");
4196    Builder.defineMacro("__pnacl__");
4197  }
4198  virtual void getTargetDefines(const LangOptions &Opts,
4199                                MacroBuilder &Builder) const {
4200    DefineStd(Builder, "unix", Opts);
4201    Builder.defineMacro("__ELF__");
4202    if (Opts.POSIXThreads)
4203      Builder.defineMacro("_REENTRANT");
4204    if (Opts.CPlusPlus)
4205      Builder.defineMacro("_GNU_SOURCE");
4206
4207    Builder.defineMacro("__LITTLE_ENDIAN__");
4208    Builder.defineMacro("__native_client__");
4209    getArchDefines(Opts, Builder);
4210  }
4211  virtual bool hasFeature(StringRef Feature) const {
4212    return Feature == "pnacl";
4213  }
4214  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4215                                 unsigned &NumRecords) const {
4216  }
4217  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4218    return TargetInfo::PNaClABIBuiltinVaList;
4219  }
4220  virtual void getGCCRegNames(const char * const *&Names,
4221                              unsigned &NumNames) const;
4222  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4223                                unsigned &NumAliases) const;
4224  virtual bool validateAsmConstraint(const char *&Name,
4225                                     TargetInfo::ConstraintInfo &Info) const {
4226    return false;
4227  }
4228
4229  virtual const char *getClobbers() const {
4230    return "";
4231  }
4232};
4233
4234void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
4235                                     unsigned &NumNames) const {
4236  Names = NULL;
4237  NumNames = 0;
4238}
4239
4240void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4241                                       unsigned &NumAliases) const {
4242  Aliases = NULL;
4243  NumAliases = 0;
4244}
4245} // end anonymous namespace.
4246
4247
4248//===----------------------------------------------------------------------===//
4249// Driver code
4250//===----------------------------------------------------------------------===//
4251
4252static TargetInfo *AllocateTarget(const std::string &T) {
4253  llvm::Triple Triple(T);
4254  llvm::Triple::OSType os = Triple.getOS();
4255
4256  switch (Triple.getArch()) {
4257  default:
4258    return NULL;
4259
4260  case llvm::Triple::hexagon:
4261    return new HexagonTargetInfo(T);
4262
4263  case llvm::Triple::arm:
4264  case llvm::Triple::thumb:
4265    if (Triple.isOSDarwin())
4266      return new DarwinARMTargetInfo(T);
4267
4268    switch (os) {
4269    case llvm::Triple::Linux:
4270      return new LinuxTargetInfo<ARMTargetInfo>(T);
4271    case llvm::Triple::FreeBSD:
4272      return new FreeBSDTargetInfo<ARMTargetInfo>(T);
4273    case llvm::Triple::NetBSD:
4274      return new NetBSDTargetInfo<ARMTargetInfo>(T);
4275    case llvm::Triple::OpenBSD:
4276      return new OpenBSDTargetInfo<ARMTargetInfo>(T);
4277    case llvm::Triple::Bitrig:
4278      return new BitrigTargetInfo<ARMTargetInfo>(T);
4279    case llvm::Triple::RTEMS:
4280      return new RTEMSTargetInfo<ARMTargetInfo>(T);
4281    default:
4282      return new ARMTargetInfo(T);
4283    }
4284
4285  case llvm::Triple::msp430:
4286    return new MSP430TargetInfo(T);
4287
4288  case llvm::Triple::mips:
4289    switch (os) {
4290    case llvm::Triple::Linux:
4291      return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
4292    case llvm::Triple::RTEMS:
4293      return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
4294    case llvm::Triple::FreeBSD:
4295      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
4296    case llvm::Triple::NetBSD:
4297      return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
4298    default:
4299      return new Mips32EBTargetInfo(T);
4300    }
4301
4302  case llvm::Triple::mipsel:
4303    switch (os) {
4304    case llvm::Triple::Linux:
4305      return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
4306    case llvm::Triple::RTEMS:
4307      return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
4308    case llvm::Triple::FreeBSD:
4309      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
4310    case llvm::Triple::NetBSD:
4311      return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
4312    default:
4313      return new Mips32ELTargetInfo(T);
4314    }
4315
4316  case llvm::Triple::mips64:
4317    switch (os) {
4318    case llvm::Triple::Linux:
4319      return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
4320    case llvm::Triple::RTEMS:
4321      return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
4322    case llvm::Triple::FreeBSD:
4323      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
4324    case llvm::Triple::NetBSD:
4325      return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
4326    case llvm::Triple::OpenBSD:
4327      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
4328    default:
4329      return new Mips64EBTargetInfo(T);
4330    }
4331
4332  case llvm::Triple::mips64el:
4333    switch (os) {
4334    case llvm::Triple::Linux:
4335      return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
4336    case llvm::Triple::RTEMS:
4337      return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
4338    case llvm::Triple::FreeBSD:
4339      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
4340    case llvm::Triple::NetBSD:
4341      return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
4342    case llvm::Triple::OpenBSD:
4343      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
4344    default:
4345      return new Mips64ELTargetInfo(T);
4346    }
4347
4348  case llvm::Triple::le32:
4349    switch (os) {
4350      case llvm::Triple::NativeClient:
4351        return new PNaClTargetInfo(T);
4352      default:
4353        return NULL;
4354    }
4355
4356  case llvm::Triple::ppc:
4357    if (Triple.isOSDarwin())
4358      return new DarwinPPC32TargetInfo(T);
4359    switch (os) {
4360    case llvm::Triple::Linux:
4361      return new LinuxTargetInfo<PPC32TargetInfo>(T);
4362    case llvm::Triple::FreeBSD:
4363      return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
4364    case llvm::Triple::NetBSD:
4365      return new NetBSDTargetInfo<PPC32TargetInfo>(T);
4366    case llvm::Triple::OpenBSD:
4367      return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
4368    case llvm::Triple::RTEMS:
4369      return new RTEMSTargetInfo<PPC32TargetInfo>(T);
4370    default:
4371      return new PPC32TargetInfo(T);
4372    }
4373
4374  case llvm::Triple::ppc64:
4375    if (Triple.isOSDarwin())
4376      return new DarwinPPC64TargetInfo(T);
4377    switch (os) {
4378    case llvm::Triple::Linux:
4379      return new LinuxTargetInfo<PPC64TargetInfo>(T);
4380    case llvm::Triple::Lv2:
4381      return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
4382    case llvm::Triple::FreeBSD:
4383      return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
4384    case llvm::Triple::NetBSD:
4385      return new NetBSDTargetInfo<PPC64TargetInfo>(T);
4386    default:
4387      return new PPC64TargetInfo(T);
4388    }
4389
4390  case llvm::Triple::nvptx:
4391    return new NVPTX32TargetInfo(T);
4392  case llvm::Triple::nvptx64:
4393    return new NVPTX64TargetInfo(T);
4394
4395  case llvm::Triple::mblaze:
4396    return new MBlazeTargetInfo(T);
4397
4398  case llvm::Triple::sparc:
4399    switch (os) {
4400    case llvm::Triple::Linux:
4401      return new LinuxTargetInfo<SparcV8TargetInfo>(T);
4402    case llvm::Triple::AuroraUX:
4403      return new AuroraUXSparcV8TargetInfo(T);
4404    case llvm::Triple::Solaris:
4405      return new SolarisSparcV8TargetInfo(T);
4406    case llvm::Triple::NetBSD:
4407      return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
4408    case llvm::Triple::OpenBSD:
4409      return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
4410    case llvm::Triple::RTEMS:
4411      return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
4412    default:
4413      return new SparcV8TargetInfo(T);
4414    }
4415
4416  // FIXME: Need a real SPU target.
4417  case llvm::Triple::cellspu:
4418    return new PS3SPUTargetInfo<PPC64TargetInfo>(T);
4419
4420  case llvm::Triple::tce:
4421    return new TCETargetInfo(T);
4422
4423  case llvm::Triple::x86:
4424    if (Triple.isOSDarwin())
4425      return new DarwinI386TargetInfo(T);
4426
4427    switch (os) {
4428    case llvm::Triple::AuroraUX:
4429      return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
4430    case llvm::Triple::Linux:
4431      return new LinuxTargetInfo<X86_32TargetInfo>(T);
4432    case llvm::Triple::DragonFly:
4433      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
4434    case llvm::Triple::NetBSD:
4435      return new NetBSDI386TargetInfo(T);
4436    case llvm::Triple::OpenBSD:
4437      return new OpenBSDI386TargetInfo(T);
4438    case llvm::Triple::Bitrig:
4439      return new BitrigI386TargetInfo(T);
4440    case llvm::Triple::FreeBSD:
4441      return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
4442    case llvm::Triple::Minix:
4443      return new MinixTargetInfo<X86_32TargetInfo>(T);
4444    case llvm::Triple::Solaris:
4445      return new SolarisTargetInfo<X86_32TargetInfo>(T);
4446    case llvm::Triple::Cygwin:
4447      return new CygwinX86_32TargetInfo(T);
4448    case llvm::Triple::MinGW32:
4449      return new MinGWX86_32TargetInfo(T);
4450    case llvm::Triple::Win32:
4451      return new VisualStudioWindowsX86_32TargetInfo(T);
4452    case llvm::Triple::Haiku:
4453      return new HaikuX86_32TargetInfo(T);
4454    case llvm::Triple::RTEMS:
4455      return new RTEMSX86_32TargetInfo(T);
4456    default:
4457      return new X86_32TargetInfo(T);
4458    }
4459
4460  case llvm::Triple::x86_64:
4461    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
4462      return new DarwinX86_64TargetInfo(T);
4463
4464    switch (os) {
4465    case llvm::Triple::AuroraUX:
4466      return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
4467    case llvm::Triple::Linux:
4468      return new LinuxTargetInfo<X86_64TargetInfo>(T);
4469    case llvm::Triple::DragonFly:
4470      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
4471    case llvm::Triple::NetBSD:
4472      return new NetBSDTargetInfo<X86_64TargetInfo>(T);
4473    case llvm::Triple::OpenBSD:
4474      return new OpenBSDX86_64TargetInfo(T);
4475    case llvm::Triple::Bitrig:
4476      return new BitrigX86_64TargetInfo(T);
4477    case llvm::Triple::FreeBSD:
4478      return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
4479    case llvm::Triple::Solaris:
4480      return new SolarisTargetInfo<X86_64TargetInfo>(T);
4481    case llvm::Triple::MinGW32:
4482      return new MinGWX86_64TargetInfo(T);
4483    case llvm::Triple::Win32:   // This is what Triple.h supports now.
4484      return new VisualStudioWindowsX86_64TargetInfo(T);
4485    default:
4486      return new X86_64TargetInfo(T);
4487    }
4488  }
4489}
4490
4491/// CreateTargetInfo - Return the target info object for the specified target
4492/// triple.
4493TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
4494                                         TargetOptions &Opts) {
4495  llvm::Triple Triple(Opts.Triple);
4496
4497  // Construct the target
4498  OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
4499  if (!Target) {
4500    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
4501    return 0;
4502  }
4503
4504  // Set the target CPU if specified.
4505  if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) {
4506    Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU;
4507    return 0;
4508  }
4509
4510  // Set the target ABI if specified.
4511  if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) {
4512    Diags.Report(diag::err_target_unknown_abi) << Opts.ABI;
4513    return 0;
4514  }
4515
4516  // Set the target C++ ABI.
4517  if (!Opts.CXXABI.empty() && !Target->setCXXABI(Opts.CXXABI)) {
4518    Diags.Report(diag::err_target_unknown_cxxabi) << Opts.CXXABI;
4519    return 0;
4520  }
4521
4522  // Compute the default target features, we need the target to handle this
4523  // because features may have dependencies on one another.
4524  llvm::StringMap<bool> Features;
4525  Target->getDefaultFeatures(Features);
4526
4527  // Apply the user specified deltas.
4528  // First the enables.
4529  for (std::vector<std::string>::const_iterator it = Opts.Features.begin(),
4530         ie = Opts.Features.end(); it != ie; ++it) {
4531    const char *Name = it->c_str();
4532
4533    if (Name[0] != '+')
4534      continue;
4535
4536    // Apply the feature via the target.
4537    if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
4538      Diags.Report(diag::err_target_invalid_feature) << Name;
4539      return 0;
4540    }
4541  }
4542
4543  // Then the disables.
4544  for (std::vector<std::string>::const_iterator it = Opts.Features.begin(),
4545         ie = Opts.Features.end(); it != ie; ++it) {
4546    const char *Name = it->c_str();
4547
4548    if (Name[0] == '+')
4549      continue;
4550
4551    // Apply the feature via the target.
4552    if (Name[0] != '-' ||
4553        !Target->setFeatureEnabled(Features, Name + 1, false)) {
4554      Diags.Report(diag::err_target_invalid_feature) << Name;
4555      return 0;
4556    }
4557  }
4558
4559  // Add the features to the compile options.
4560  //
4561  // FIXME: If we are completely confident that we have the right set, we only
4562  // need to pass the minuses.
4563  Opts.Features.clear();
4564  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
4565         ie = Features.end(); it != ie; ++it)
4566    Opts.Features.push_back((it->second ? "+" : "-") + it->first().str());
4567  Target->HandleTargetFeatures(Opts.Features);
4568
4569  return Target.take();
4570}
4571