Targets.cpp revision fc12c4aa20876bdf91bff98dc50eb68b4dd04b80 
1//===--- Targets.cpp - Implement -arch option and targets -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements construction of a TargetInfo object from a
11// target triple.
12//
13//===----------------------------------------------------------------------===//
14
15#include "clang/Basic/TargetInfo.h"
16#include "clang/Basic/Builtins.h"
17#include "clang/Basic/Diagnostic.h"
18#include "clang/Basic/LangOptions.h"
19#include "clang/Basic/MacroBuilder.h"
20#include "clang/Basic/TargetBuiltins.h"
21#include "clang/Basic/TargetOptions.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/OwningPtr.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringRef.h"
26#include "llvm/ADT/StringSwitch.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/Type.h"
29#include "llvm/MC/MCSectionMachO.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <algorithm>
32using namespace clang;
33
34//===----------------------------------------------------------------------===//
35//  Common code shared among targets.
36//===----------------------------------------------------------------------===//
37
38/// DefineStd - Define a macro name and standard variants.  For example if
39/// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40/// when in GNU mode.
41static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                      const LangOptions &Opts) {
43  assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44
45  // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46  // in the user's namespace.
47  if (Opts.GNUMode)
48    Builder.defineMacro(MacroName);
49
50  // Define __unix.
51  Builder.defineMacro("__" + MacroName);
52
53  // Define __unix__.
54  Builder.defineMacro("__" + MacroName + "__");
55}
56
57static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                            bool Tuning = true) {
59  Builder.defineMacro("__" + CPUName);
60  Builder.defineMacro("__" + CPUName + "__");
61  if (Tuning)
62    Builder.defineMacro("__tune_" + CPUName + "__");
63}
64
65//===----------------------------------------------------------------------===//
66// Defines specific to certain operating systems.
67//===----------------------------------------------------------------------===//
68
69namespace {
70template<typename TgtInfo>
71class OSTargetInfo : public TgtInfo {
72protected:
73  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                            MacroBuilder &Builder) const=0;
75public:
76  OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77  virtual void getTargetDefines(const LangOptions &Opts,
78                                MacroBuilder &Builder) const {
79    TgtInfo::getTargetDefines(Opts, Builder);
80    getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81  }
82
83};
84} // end anonymous namespace
85
86
87static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                             const llvm::Triple &Triple,
89                             StringRef &PlatformName,
90                             VersionTuple &PlatformMinVersion) {
91  Builder.defineMacro("__APPLE_CC__", "6000");
92  Builder.defineMacro("__APPLE__");
93  Builder.defineMacro("__MACH__");
94  Builder.defineMacro("OBJC_NEW_PROPERTIES");
95  // AddressSanitizer doesn't play well with source fortification, which is on
96  // by default on Darwin.
97  if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98
99  if (!Opts.ObjCAutoRefCount) {
100    // __weak is always defined, for use in blocks and with objc pointers.
101    Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102
103    // Darwin defines __strong even in C mode (just to nothing).
104    if (Opts.getGC() != LangOptions::NonGC)
105      Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106    else
107      Builder.defineMacro("__strong", "");
108
109    // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110    // allow this in C, since one might have block pointers in structs that
111    // are used in pure C code and in Objective-C ARC.
112    Builder.defineMacro("__unsafe_unretained", "");
113  }
114
115  if (Opts.Static)
116    Builder.defineMacro("__STATIC__");
117  else
118    Builder.defineMacro("__DYNAMIC__");
119
120  if (Opts.POSIXThreads)
121    Builder.defineMacro("_REENTRANT");
122
123  // Get the platform type and version number from the triple.
124  unsigned Maj, Min, Rev;
125  if (Triple.isMacOSX()) {
126    Triple.getMacOSXVersion(Maj, Min, Rev);
127    PlatformName = "macosx";
128  } else {
129    Triple.getOSVersion(Maj, Min, Rev);
130    PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131  }
132
133  // If -target arch-pc-win32-macho option specified, we're
134  // generating code for Win32 ABI. No need to emit
135  // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136  if (PlatformName == "win32") {
137    PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138    return;
139  }
140
141  // Set the appropriate OS version define.
142  if (Triple.isiOS()) {
143    assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144    char Str[6];
145    Str[0] = '0' + Maj;
146    Str[1] = '0' + (Min / 10);
147    Str[2] = '0' + (Min % 10);
148    Str[3] = '0' + (Rev / 10);
149    Str[4] = '0' + (Rev % 10);
150    Str[5] = '\0';
151    Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152  } else {
153    // Note that the Driver allows versions which aren't representable in the
154    // define (because we only get a single digit for the minor and micro
155    // revision numbers). So, we limit them to the maximum representable
156    // version.
157    assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158    assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159    char Str[5];
160    Str[0] = '0' + (Maj / 10);
161    Str[1] = '0' + (Maj % 10);
162    Str[2] = '0' + std::min(Min, 9U);
163    Str[3] = '0' + std::min(Rev, 9U);
164    Str[4] = '\0';
165    Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166  }
167
168  PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169}
170
171namespace {
172template<typename Target>
173class DarwinTargetInfo : public OSTargetInfo<Target> {
174protected:
175  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                            MacroBuilder &Builder) const {
177    getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                     this->PlatformMinVersion);
179  }
180
181public:
182  DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
183    this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
184    this->MCountName = "\01mcount";
185  }
186
187  virtual std::string isValidSectionSpecifier(StringRef SR) const {
188    // Let MCSectionMachO validate this.
189    StringRef Segment, Section;
190    unsigned TAA, StubSize;
191    bool HasTAA;
192    return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
193                                                       TAA, HasTAA, StubSize);
194  }
195
196  virtual const char *getStaticInitSectionSpecifier() const {
197    // FIXME: We should return 0 when building kexts.
198    return "__TEXT,__StaticInit,regular,pure_instructions";
199  }
200
201  /// Darwin does not support protected visibility.  Darwin's "default"
202  /// is very similar to ELF's "protected";  Darwin requires a "weak"
203  /// attribute on declarations that can be dynamically replaced.
204  virtual bool hasProtectedVisibility() const {
205    return false;
206  }
207};
208
209
210// DragonFlyBSD Target
211template<typename Target>
212class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
213protected:
214  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
215                            MacroBuilder &Builder) const {
216    // DragonFly defines; list based off of gcc output
217    Builder.defineMacro("__DragonFly__");
218    Builder.defineMacro("__DragonFly_cc_version", "100001");
219    Builder.defineMacro("__ELF__");
220    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
221    Builder.defineMacro("__tune_i386__");
222    DefineStd(Builder, "unix", Opts);
223  }
224public:
225  DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
226      : OSTargetInfo<Target>(Triple) {
227    this->UserLabelPrefix = "";
228
229    switch (Triple.getArch()) {
230    default:
231    case llvm::Triple::x86:
232    case llvm::Triple::x86_64:
233      this->MCountName = ".mcount";
234      break;
235    }
236  }
237};
238
239// FreeBSD Target
240template<typename Target>
241class FreeBSDTargetInfo : public OSTargetInfo<Target> {
242protected:
243  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
244                            MacroBuilder &Builder) const {
245    // FreeBSD defines; list based off of gcc output
246
247    unsigned Release = Triple.getOSMajorVersion();
248    if (Release == 0U)
249      Release = 8;
250
251    Builder.defineMacro("__FreeBSD__", Twine(Release));
252    Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
253    Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
254    DefineStd(Builder, "unix", Opts);
255    Builder.defineMacro("__ELF__");
256  }
257public:
258  FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
259    this->UserLabelPrefix = "";
260
261    switch (Triple.getArch()) {
262    default:
263    case llvm::Triple::x86:
264    case llvm::Triple::x86_64:
265      this->MCountName = ".mcount";
266      break;
267    case llvm::Triple::mips:
268    case llvm::Triple::mipsel:
269    case llvm::Triple::ppc:
270    case llvm::Triple::ppc64:
271    case llvm::Triple::ppc64le:
272      this->MCountName = "_mcount";
273      break;
274    case llvm::Triple::arm:
275      this->MCountName = "__mcount";
276      break;
277    }
278  }
279};
280
281// GNU/kFreeBSD Target
282template<typename Target>
283class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
284protected:
285  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
286                            MacroBuilder &Builder) const {
287    // GNU/kFreeBSD defines; list based off of gcc output
288
289    DefineStd(Builder, "unix", Opts);
290    Builder.defineMacro("__FreeBSD_kernel__");
291    Builder.defineMacro("__GLIBC__");
292    Builder.defineMacro("__ELF__");
293    if (Opts.POSIXThreads)
294      Builder.defineMacro("_REENTRANT");
295    if (Opts.CPlusPlus)
296      Builder.defineMacro("_GNU_SOURCE");
297  }
298public:
299  KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
300    this->UserLabelPrefix = "";
301  }
302};
303
304// Minix Target
305template<typename Target>
306class MinixTargetInfo : public OSTargetInfo<Target> {
307protected:
308  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
309                            MacroBuilder &Builder) const {
310    // Minix defines
311
312    Builder.defineMacro("__minix", "3");
313    Builder.defineMacro("_EM_WSIZE", "4");
314    Builder.defineMacro("_EM_PSIZE", "4");
315    Builder.defineMacro("_EM_SSIZE", "2");
316    Builder.defineMacro("_EM_LSIZE", "4");
317    Builder.defineMacro("_EM_FSIZE", "4");
318    Builder.defineMacro("_EM_DSIZE", "8");
319    Builder.defineMacro("__ELF__");
320    DefineStd(Builder, "unix", Opts);
321  }
322public:
323  MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
324    this->UserLabelPrefix = "";
325  }
326};
327
328// Linux target
329template<typename Target>
330class LinuxTargetInfo : public OSTargetInfo<Target> {
331protected:
332  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
333                            MacroBuilder &Builder) const {
334    // Linux defines; list based off of gcc output
335    DefineStd(Builder, "unix", Opts);
336    DefineStd(Builder, "linux", Opts);
337    Builder.defineMacro("__gnu_linux__");
338    Builder.defineMacro("__ELF__");
339    if (Triple.getEnvironment() == llvm::Triple::Android)
340      Builder.defineMacro("__ANDROID__", "1");
341    if (Opts.POSIXThreads)
342      Builder.defineMacro("_REENTRANT");
343    if (Opts.CPlusPlus)
344      Builder.defineMacro("_GNU_SOURCE");
345  }
346public:
347  LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
348    this->UserLabelPrefix = "";
349    this->WIntType = TargetInfo::UnsignedInt;
350  }
351
352  virtual const char *getStaticInitSectionSpecifier() const {
353    return ".text.startup";
354  }
355};
356
357// NetBSD Target
358template<typename Target>
359class NetBSDTargetInfo : public OSTargetInfo<Target> {
360protected:
361  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
362                            MacroBuilder &Builder) const {
363    // NetBSD defines; list based off of gcc output
364    Builder.defineMacro("__NetBSD__");
365    Builder.defineMacro("__unix__");
366    Builder.defineMacro("__ELF__");
367    if (Opts.POSIXThreads)
368      Builder.defineMacro("_POSIX_THREADS");
369  }
370public:
371  NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
372    this->UserLabelPrefix = "";
373  }
374};
375
376// OpenBSD Target
377template<typename Target>
378class OpenBSDTargetInfo : public OSTargetInfo<Target> {
379protected:
380  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
381                            MacroBuilder &Builder) const {
382    // OpenBSD defines; list based off of gcc output
383
384    Builder.defineMacro("__OpenBSD__");
385    DefineStd(Builder, "unix", Opts);
386    Builder.defineMacro("__ELF__");
387    if (Opts.POSIXThreads)
388      Builder.defineMacro("_REENTRANT");
389  }
390public:
391  OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
392    this->UserLabelPrefix = "";
393    this->TLSSupported = false;
394
395      switch (Triple.getArch()) {
396        default:
397        case llvm::Triple::x86:
398        case llvm::Triple::x86_64:
399        case llvm::Triple::arm:
400        case llvm::Triple::sparc:
401          this->MCountName = "__mcount";
402          break;
403        case llvm::Triple::mips64:
404        case llvm::Triple::mips64el:
405        case llvm::Triple::ppc:
406        case llvm::Triple::sparcv9:
407          this->MCountName = "_mcount";
408          break;
409      }
410  }
411};
412
413// Bitrig Target
414template<typename Target>
415class BitrigTargetInfo : public OSTargetInfo<Target> {
416protected:
417  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
418                            MacroBuilder &Builder) const {
419    // Bitrig defines; list based off of gcc output
420
421    Builder.defineMacro("__Bitrig__");
422    DefineStd(Builder, "unix", Opts);
423    Builder.defineMacro("__ELF__");
424    if (Opts.POSIXThreads)
425      Builder.defineMacro("_REENTRANT");
426  }
427public:
428  BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
429    this->UserLabelPrefix = "";
430    this->TLSSupported = false;
431    this->MCountName = "__mcount";
432  }
433};
434
435// PSP Target
436template<typename Target>
437class PSPTargetInfo : public OSTargetInfo<Target> {
438protected:
439  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
440                            MacroBuilder &Builder) const {
441    // PSP defines; list based on the output of the pspdev gcc toolchain.
442    Builder.defineMacro("PSP");
443    Builder.defineMacro("_PSP");
444    Builder.defineMacro("__psp__");
445    Builder.defineMacro("__ELF__");
446  }
447public:
448  PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
449    this->UserLabelPrefix = "";
450  }
451};
452
453// PS3 PPU Target
454template<typename Target>
455class PS3PPUTargetInfo : public OSTargetInfo<Target> {
456protected:
457  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458                            MacroBuilder &Builder) const {
459    // PS3 PPU defines.
460    Builder.defineMacro("__PPC__");
461    Builder.defineMacro("__PPU__");
462    Builder.defineMacro("__CELLOS_LV2__");
463    Builder.defineMacro("__ELF__");
464    Builder.defineMacro("__LP32__");
465    Builder.defineMacro("_ARCH_PPC64");
466    Builder.defineMacro("__powerpc64__");
467  }
468public:
469  PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
470    this->UserLabelPrefix = "";
471    this->LongWidth = this->LongAlign = 32;
472    this->PointerWidth = this->PointerAlign = 32;
473    this->IntMaxType = TargetInfo::SignedLongLong;
474    this->UIntMaxType = TargetInfo::UnsignedLongLong;
475    this->Int64Type = TargetInfo::SignedLongLong;
476    this->SizeType = TargetInfo::UnsignedInt;
477    this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
478                              "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
479  }
480};
481
482// FIXME: Need a real SPU target.
483// PS3 SPU Target
484template<typename Target>
485class PS3SPUTargetInfo : public OSTargetInfo<Target> {
486protected:
487  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
488                            MacroBuilder &Builder) const {
489    // PS3 PPU defines.
490    Builder.defineMacro("__SPU__");
491    Builder.defineMacro("__ELF__");
492  }
493public:
494  PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
495    this->UserLabelPrefix = "";
496  }
497};
498
499// AuroraUX target
500template<typename Target>
501class AuroraUXTargetInfo : public OSTargetInfo<Target> {
502protected:
503  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
504                            MacroBuilder &Builder) const {
505    DefineStd(Builder, "sun", Opts);
506    DefineStd(Builder, "unix", Opts);
507    Builder.defineMacro("__ELF__");
508    Builder.defineMacro("__svr4__");
509    Builder.defineMacro("__SVR4");
510  }
511public:
512  AuroraUXTargetInfo(const llvm::Triple &Triple)
513      : OSTargetInfo<Target>(Triple) {
514    this->UserLabelPrefix = "";
515    this->WCharType = this->SignedLong;
516    // FIXME: WIntType should be SignedLong
517  }
518};
519
520// Solaris target
521template<typename Target>
522class SolarisTargetInfo : public OSTargetInfo<Target> {
523protected:
524  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
525                            MacroBuilder &Builder) const {
526    DefineStd(Builder, "sun", Opts);
527    DefineStd(Builder, "unix", Opts);
528    Builder.defineMacro("__ELF__");
529    Builder.defineMacro("__svr4__");
530    Builder.defineMacro("__SVR4");
531    // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
532    // newer, but to 500 for everything else.  feature_test.h has a check to
533    // ensure that you are not using C99 with an old version of X/Open or C89
534    // with a new version.
535    if (Opts.C99 || Opts.C11)
536      Builder.defineMacro("_XOPEN_SOURCE", "600");
537    else
538      Builder.defineMacro("_XOPEN_SOURCE", "500");
539    if (Opts.CPlusPlus)
540      Builder.defineMacro("__C99FEATURES__");
541    Builder.defineMacro("_LARGEFILE_SOURCE");
542    Builder.defineMacro("_LARGEFILE64_SOURCE");
543    Builder.defineMacro("__EXTENSIONS__");
544    Builder.defineMacro("_REENTRANT");
545  }
546public:
547  SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
548    this->UserLabelPrefix = "";
549    this->WCharType = this->SignedInt;
550    // FIXME: WIntType should be SignedLong
551  }
552};
553
554// Windows target
555template<typename Target>
556class WindowsTargetInfo : public OSTargetInfo<Target> {
557protected:
558  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
559                            MacroBuilder &Builder) const {
560    Builder.defineMacro("_WIN32");
561  }
562  void getVisualStudioDefines(const LangOptions &Opts,
563                              MacroBuilder &Builder) const {
564    if (Opts.CPlusPlus) {
565      if (Opts.RTTI)
566        Builder.defineMacro("_CPPRTTI");
567
568      if (Opts.Exceptions)
569        Builder.defineMacro("_CPPUNWIND");
570    }
571
572    if (!Opts.CharIsSigned)
573      Builder.defineMacro("_CHAR_UNSIGNED");
574
575    // FIXME: POSIXThreads isn't exactly the option this should be defined for,
576    //        but it works for now.
577    if (Opts.POSIXThreads)
578      Builder.defineMacro("_MT");
579
580    if (Opts.MSCVersion != 0)
581      Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
582
583    if (Opts.MicrosoftExt) {
584      Builder.defineMacro("_MSC_EXTENSIONS");
585
586      if (Opts.CPlusPlus11) {
587        Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
588        Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
589        Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
590      }
591    }
592
593    Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
594  }
595
596public:
597  WindowsTargetInfo(const llvm::Triple &Triple)
598      : OSTargetInfo<Target>(Triple) {}
599};
600
601template <typename Target>
602class NaClTargetInfo : public OSTargetInfo<Target> {
603protected:
604  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
605                            MacroBuilder &Builder) const {
606    if (Opts.POSIXThreads)
607      Builder.defineMacro("_REENTRANT");
608    if (Opts.CPlusPlus)
609      Builder.defineMacro("_GNU_SOURCE");
610
611    DefineStd(Builder, "unix", Opts);
612    Builder.defineMacro("__ELF__");
613    Builder.defineMacro("__native_client__");
614  }
615
616public:
617  NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
618    this->UserLabelPrefix = "";
619    this->LongAlign = 32;
620    this->LongWidth = 32;
621    this->PointerAlign = 32;
622    this->PointerWidth = 32;
623    this->IntMaxType = TargetInfo::SignedLongLong;
624    this->UIntMaxType = TargetInfo::UnsignedLongLong;
625    this->Int64Type = TargetInfo::SignedLongLong;
626    this->DoubleAlign = 64;
627    this->LongDoubleWidth = 64;
628    this->LongDoubleAlign = 64;
629    this->SizeType = TargetInfo::UnsignedInt;
630    this->PtrDiffType = TargetInfo::SignedInt;
631    this->IntPtrType = TargetInfo::SignedInt;
632    // RegParmMax is inherited from the underlying architecture
633    this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
634    this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
635                              "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
636  }
637  virtual typename Target::CallingConvCheckResult checkCallingConvention(
638      CallingConv CC) const {
639    return CC == CC_PnaclCall ? Target::CCCR_OK :
640        Target::checkCallingConvention(CC);
641  }
642};
643} // end anonymous namespace.
644
645//===----------------------------------------------------------------------===//
646// Specific target implementations.
647//===----------------------------------------------------------------------===//
648
649namespace {
650// PPC abstract base class
651class PPCTargetInfo : public TargetInfo {
652  static const Builtin::Info BuiltinInfo[];
653  static const char * const GCCRegNames[];
654  static const TargetInfo::GCCRegAlias GCCRegAliases[];
655  std::string CPU;
656public:
657  PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
658    BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
659    LongDoubleWidth = LongDoubleAlign = 128;
660    LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
661  }
662
663  /// \brief Flags for architecture specific defines.
664  typedef enum {
665    ArchDefineNone  = 0,
666    ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
667    ArchDefinePpcgr = 1 << 1,
668    ArchDefinePpcsq = 1 << 2,
669    ArchDefine440   = 1 << 3,
670    ArchDefine603   = 1 << 4,
671    ArchDefine604   = 1 << 5,
672    ArchDefinePwr4  = 1 << 6,
673    ArchDefinePwr5  = 1 << 7,
674    ArchDefinePwr5x = 1 << 8,
675    ArchDefinePwr6  = 1 << 9,
676    ArchDefinePwr6x = 1 << 10,
677    ArchDefinePwr7  = 1 << 11,
678    ArchDefineA2    = 1 << 12,
679    ArchDefineA2q   = 1 << 13
680  } ArchDefineTypes;
681
682  // Note: GCC recognizes the following additional cpus:
683  //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
684  //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
685  //  titan, rs64.
686  virtual bool setCPU(const std::string &Name) {
687    bool CPUKnown = llvm::StringSwitch<bool>(Name)
688      .Case("generic", true)
689      .Case("440", true)
690      .Case("450", true)
691      .Case("601", true)
692      .Case("602", true)
693      .Case("603", true)
694      .Case("603e", true)
695      .Case("603ev", true)
696      .Case("604", true)
697      .Case("604e", true)
698      .Case("620", true)
699      .Case("630", true)
700      .Case("g3", true)
701      .Case("7400", true)
702      .Case("g4", true)
703      .Case("7450", true)
704      .Case("g4+", true)
705      .Case("750", true)
706      .Case("970", true)
707      .Case("g5", true)
708      .Case("a2", true)
709      .Case("a2q", true)
710      .Case("e500mc", true)
711      .Case("e5500", true)
712      .Case("power3", true)
713      .Case("pwr3", true)
714      .Case("power4", true)
715      .Case("pwr4", true)
716      .Case("power5", true)
717      .Case("pwr5", true)
718      .Case("power5x", true)
719      .Case("pwr5x", true)
720      .Case("power6", true)
721      .Case("pwr6", true)
722      .Case("power6x", true)
723      .Case("pwr6x", true)
724      .Case("power7", true)
725      .Case("pwr7", true)
726      .Case("powerpc", true)
727      .Case("ppc", true)
728      .Case("powerpc64", true)
729      .Case("ppc64", true)
730      .Case("powerpc64le", true)
731      .Case("ppc64le", true)
732      .Default(false);
733
734    if (CPUKnown)
735      CPU = Name;
736
737    return CPUKnown;
738  }
739
740  virtual void getTargetBuiltins(const Builtin::Info *&Records,
741                                 unsigned &NumRecords) const {
742    Records = BuiltinInfo;
743    NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
744  }
745
746  virtual bool isCLZForZeroUndef() const { return false; }
747
748  virtual void getTargetDefines(const LangOptions &Opts,
749                                MacroBuilder &Builder) const;
750
751  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
752
753  virtual bool hasFeature(StringRef Feature) const;
754
755  virtual void getGCCRegNames(const char * const *&Names,
756                              unsigned &NumNames) const;
757  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
758                                unsigned &NumAliases) const;
759  virtual bool validateAsmConstraint(const char *&Name,
760                                     TargetInfo::ConstraintInfo &Info) const {
761    switch (*Name) {
762    default: return false;
763    case 'O': // Zero
764      break;
765    case 'b': // Base register
766    case 'f': // Floating point register
767      Info.setAllowsRegister();
768      break;
769    // FIXME: The following are added to allow parsing.
770    // I just took a guess at what the actions should be.
771    // Also, is more specific checking needed?  I.e. specific registers?
772    case 'd': // Floating point register (containing 64-bit value)
773    case 'v': // Altivec vector register
774      Info.setAllowsRegister();
775      break;
776    case 'w':
777      switch (Name[1]) {
778        case 'd':// VSX vector register to hold vector double data
779        case 'f':// VSX vector register to hold vector float data
780        case 's':// VSX vector register to hold scalar float data
781        case 'a':// Any VSX register
782          break;
783        default:
784          return false;
785      }
786      Info.setAllowsRegister();
787      Name++; // Skip over 'w'.
788      break;
789    case 'h': // `MQ', `CTR', or `LINK' register
790    case 'q': // `MQ' register
791    case 'c': // `CTR' register
792    case 'l': // `LINK' register
793    case 'x': // `CR' register (condition register) number 0
794    case 'y': // `CR' register (condition register)
795    case 'z': // `XER[CA]' carry bit (part of the XER register)
796      Info.setAllowsRegister();
797      break;
798    case 'I': // Signed 16-bit constant
799    case 'J': // Unsigned 16-bit constant shifted left 16 bits
800              //  (use `L' instead for SImode constants)
801    case 'K': // Unsigned 16-bit constant
802    case 'L': // Signed 16-bit constant shifted left 16 bits
803    case 'M': // Constant larger than 31
804    case 'N': // Exact power of 2
805    case 'P': // Constant whose negation is a signed 16-bit constant
806    case 'G': // Floating point constant that can be loaded into a
807              // register with one instruction per word
808    case 'H': // Integer/Floating point constant that can be loaded
809              // into a register using three instructions
810      break;
811    case 'm': // Memory operand. Note that on PowerPC targets, m can
812              // include addresses that update the base register. It
813              // is therefore only safe to use `m' in an asm statement
814              // if that asm statement accesses the operand exactly once.
815              // The asm statement must also use `%U<opno>' as a
816              // placeholder for the "update" flag in the corresponding
817              // load or store instruction. For example:
818              // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
819              // is correct but:
820              // asm ("st %1,%0" : "=m" (mem) : "r" (val));
821              // is not. Use es rather than m if you don't want the base
822              // register to be updated.
823    case 'e':
824      if (Name[1] != 's')
825          return false;
826              // es: A "stable" memory operand; that is, one which does not
827              // include any automodification of the base register. Unlike
828              // `m', this constraint can be used in asm statements that
829              // might access the operand several times, or that might not
830              // access it at all.
831      Info.setAllowsMemory();
832      Name++; // Skip over 'e'.
833      break;
834    case 'Q': // Memory operand that is an offset from a register (it is
835              // usually better to use `m' or `es' in asm statements)
836    case 'Z': // Memory operand that is an indexed or indirect from a
837              // register (it is usually better to use `m' or `es' in
838              // asm statements)
839      Info.setAllowsMemory();
840      Info.setAllowsRegister();
841      break;
842    case 'R': // AIX TOC entry
843    case 'a': // Address operand that is an indexed or indirect from a
844              // register (`p' is preferable for asm statements)
845    case 'S': // Constant suitable as a 64-bit mask operand
846    case 'T': // Constant suitable as a 32-bit mask operand
847    case 'U': // System V Release 4 small data area reference
848    case 't': // AND masks that can be performed by two rldic{l, r}
849              // instructions
850    case 'W': // Vector constant that does not require memory
851    case 'j': // Vector constant that is all zeros.
852      break;
853    // End FIXME.
854    }
855    return true;
856  }
857  virtual const char *getClobbers() const {
858    return "";
859  }
860  int getEHDataRegisterNumber(unsigned RegNo) const {
861    if (RegNo == 0) return 3;
862    if (RegNo == 1) return 4;
863    return -1;
864  }
865};
866
867const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
868#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
869#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
870                                              ALL_LANGUAGES },
871#include "clang/Basic/BuiltinsPPC.def"
872};
873
874
875/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
876/// #defines that are not tied to a specific subtarget.
877void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
878                                     MacroBuilder &Builder) const {
879  // Target identification.
880  Builder.defineMacro("__ppc__");
881  Builder.defineMacro("__PPC__");
882  Builder.defineMacro("_ARCH_PPC");
883  Builder.defineMacro("__powerpc__");
884  Builder.defineMacro("__POWERPC__");
885  if (PointerWidth == 64) {
886    Builder.defineMacro("_ARCH_PPC64");
887    Builder.defineMacro("__powerpc64__");
888    Builder.defineMacro("__ppc64__");
889    Builder.defineMacro("__PPC64__");
890  }
891
892  // Target properties.
893  if (getTriple().getArch() == llvm::Triple::ppc64le) {
894    Builder.defineMacro("_LITTLE_ENDIAN");
895    Builder.defineMacro("__LITTLE_ENDIAN__");
896  } else {
897    if (getTriple().getOS() != llvm::Triple::NetBSD &&
898        getTriple().getOS() != llvm::Triple::OpenBSD)
899      Builder.defineMacro("_BIG_ENDIAN");
900    Builder.defineMacro("__BIG_ENDIAN__");
901  }
902
903  // Subtarget options.
904  Builder.defineMacro("__NATURAL_ALIGNMENT__");
905  Builder.defineMacro("__REGISTER_PREFIX__", "");
906
907  // FIXME: Should be controlled by command line option.
908  if (LongDoubleWidth == 128)
909    Builder.defineMacro("__LONG_DOUBLE_128__");
910
911  if (Opts.AltiVec) {
912    Builder.defineMacro("__VEC__", "10206");
913    Builder.defineMacro("__ALTIVEC__");
914  }
915
916  // CPU identification.
917  ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
918    .Case("440",   ArchDefineName)
919    .Case("450",   ArchDefineName | ArchDefine440)
920    .Case("601",   ArchDefineName)
921    .Case("602",   ArchDefineName | ArchDefinePpcgr)
922    .Case("603",   ArchDefineName | ArchDefinePpcgr)
923    .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
924    .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
925    .Case("604",   ArchDefineName | ArchDefinePpcgr)
926    .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
927    .Case("620",   ArchDefineName | ArchDefinePpcgr)
928    .Case("630",   ArchDefineName | ArchDefinePpcgr)
929    .Case("7400",  ArchDefineName | ArchDefinePpcgr)
930    .Case("7450",  ArchDefineName | ArchDefinePpcgr)
931    .Case("750",   ArchDefineName | ArchDefinePpcgr)
932    .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
933                     | ArchDefinePpcsq)
934    .Case("a2",    ArchDefineA2)
935    .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
936    .Case("pwr3",  ArchDefinePpcgr)
937    .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
938    .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
939                     | ArchDefinePpcsq)
940    .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
941                     | ArchDefinePpcgr | ArchDefinePpcsq)
942    .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
943                     | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
944    .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
945                     | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
946                     | ArchDefinePpcsq)
947    .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
948                     | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
949                     | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
950    .Case("power3",  ArchDefinePpcgr)
951    .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
952    .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
953                       | ArchDefinePpcsq)
954    .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
955                       | ArchDefinePpcgr | ArchDefinePpcsq)
956    .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
957                       | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
958    .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
959                       | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
960                       | ArchDefinePpcsq)
961    .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
962                       | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
963                       | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
964    .Default(ArchDefineNone);
965
966  if (defs & ArchDefineName)
967    Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
968  if (defs & ArchDefinePpcgr)
969    Builder.defineMacro("_ARCH_PPCGR");
970  if (defs & ArchDefinePpcsq)
971    Builder.defineMacro("_ARCH_PPCSQ");
972  if (defs & ArchDefine440)
973    Builder.defineMacro("_ARCH_440");
974  if (defs & ArchDefine603)
975    Builder.defineMacro("_ARCH_603");
976  if (defs & ArchDefine604)
977    Builder.defineMacro("_ARCH_604");
978  if (defs & ArchDefinePwr4)
979    Builder.defineMacro("_ARCH_PWR4");
980  if (defs & ArchDefinePwr5)
981    Builder.defineMacro("_ARCH_PWR5");
982  if (defs & ArchDefinePwr5x)
983    Builder.defineMacro("_ARCH_PWR5X");
984  if (defs & ArchDefinePwr6)
985    Builder.defineMacro("_ARCH_PWR6");
986  if (defs & ArchDefinePwr6x)
987    Builder.defineMacro("_ARCH_PWR6X");
988  if (defs & ArchDefinePwr7)
989    Builder.defineMacro("_ARCH_PWR7");
990  if (defs & ArchDefineA2)
991    Builder.defineMacro("_ARCH_A2");
992  if (defs & ArchDefineA2q) {
993    Builder.defineMacro("_ARCH_A2Q");
994    Builder.defineMacro("_ARCH_QP");
995  }
996
997  if (getTriple().getVendor() == llvm::Triple::BGQ) {
998    Builder.defineMacro("__bg__");
999    Builder.defineMacro("__THW_BLUEGENE__");
1000    Builder.defineMacro("__bgq__");
1001    Builder.defineMacro("__TOS_BGQ__");
1002  }
1003
1004  // FIXME: The following are not yet generated here by Clang, but are
1005  //        generated by GCC:
1006  //
1007  //   _SOFT_FLOAT_
1008  //   __RECIP_PRECISION__
1009  //   __APPLE_ALTIVEC__
1010  //   __VSX__
1011  //   __RECIP__
1012  //   __RECIPF__
1013  //   __RSQRTE__
1014  //   __RSQRTEF__
1015  //   _SOFT_DOUBLE_
1016  //   __NO_LWSYNC__
1017  //   __HAVE_BSWAP__
1018  //   __LONGDOUBLE128
1019  //   __CMODEL_MEDIUM__
1020  //   __CMODEL_LARGE__
1021  //   _CALL_SYSV
1022  //   _CALL_DARWIN
1023  //   __NO_FPRS__
1024}
1025
1026void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1027  Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1028    .Case("7400", true)
1029    .Case("g4", true)
1030    .Case("7450", true)
1031    .Case("g4+", true)
1032    .Case("970", true)
1033    .Case("g5", true)
1034    .Case("pwr6", true)
1035    .Case("pwr7", true)
1036    .Case("ppc64", true)
1037    .Case("ppc64le", true)
1038    .Default(false);
1039
1040  Features["qpx"] = (CPU == "a2q");
1041}
1042
1043bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1044  return Feature == "powerpc";
1045}
1046
1047
1048const char * const PPCTargetInfo::GCCRegNames[] = {
1049  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1050  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1051  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1052  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1053  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1054  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1055  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1056  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1057  "mq", "lr", "ctr", "ap",
1058  "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1059  "xer",
1060  "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1061  "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1062  "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1063  "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1064  "vrsave", "vscr",
1065  "spe_acc", "spefscr",
1066  "sfp"
1067};
1068
1069void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1070                                   unsigned &NumNames) const {
1071  Names = GCCRegNames;
1072  NumNames = llvm::array_lengthof(GCCRegNames);
1073}
1074
1075const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1076  // While some of these aliases do map to different registers
1077  // they still share the same register name.
1078  { { "0" }, "r0" },
1079  { { "1"}, "r1" },
1080  { { "2" }, "r2" },
1081  { { "3" }, "r3" },
1082  { { "4" }, "r4" },
1083  { { "5" }, "r5" },
1084  { { "6" }, "r6" },
1085  { { "7" }, "r7" },
1086  { { "8" }, "r8" },
1087  { { "9" }, "r9" },
1088  { { "10" }, "r10" },
1089  { { "11" }, "r11" },
1090  { { "12" }, "r12" },
1091  { { "13" }, "r13" },
1092  { { "14" }, "r14" },
1093  { { "15" }, "r15" },
1094  { { "16" }, "r16" },
1095  { { "17" }, "r17" },
1096  { { "18" }, "r18" },
1097  { { "19" }, "r19" },
1098  { { "20" }, "r20" },
1099  { { "21" }, "r21" },
1100  { { "22" }, "r22" },
1101  { { "23" }, "r23" },
1102  { { "24" }, "r24" },
1103  { { "25" }, "r25" },
1104  { { "26" }, "r26" },
1105  { { "27" }, "r27" },
1106  { { "28" }, "r28" },
1107  { { "29" }, "r29" },
1108  { { "30" }, "r30" },
1109  { { "31" }, "r31" },
1110  { { "fr0" }, "f0" },
1111  { { "fr1" }, "f1" },
1112  { { "fr2" }, "f2" },
1113  { { "fr3" }, "f3" },
1114  { { "fr4" }, "f4" },
1115  { { "fr5" }, "f5" },
1116  { { "fr6" }, "f6" },
1117  { { "fr7" }, "f7" },
1118  { { "fr8" }, "f8" },
1119  { { "fr9" }, "f9" },
1120  { { "fr10" }, "f10" },
1121  { { "fr11" }, "f11" },
1122  { { "fr12" }, "f12" },
1123  { { "fr13" }, "f13" },
1124  { { "fr14" }, "f14" },
1125  { { "fr15" }, "f15" },
1126  { { "fr16" }, "f16" },
1127  { { "fr17" }, "f17" },
1128  { { "fr18" }, "f18" },
1129  { { "fr19" }, "f19" },
1130  { { "fr20" }, "f20" },
1131  { { "fr21" }, "f21" },
1132  { { "fr22" }, "f22" },
1133  { { "fr23" }, "f23" },
1134  { { "fr24" }, "f24" },
1135  { { "fr25" }, "f25" },
1136  { { "fr26" }, "f26" },
1137  { { "fr27" }, "f27" },
1138  { { "fr28" }, "f28" },
1139  { { "fr29" }, "f29" },
1140  { { "fr30" }, "f30" },
1141  { { "fr31" }, "f31" },
1142  { { "cc" }, "cr0" },
1143};
1144
1145void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1146                                     unsigned &NumAliases) const {
1147  Aliases = GCCRegAliases;
1148  NumAliases = llvm::array_lengthof(GCCRegAliases);
1149}
1150} // end anonymous namespace.
1151
1152namespace {
1153class PPC32TargetInfo : public PPCTargetInfo {
1154public:
1155  PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1156    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1157                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1158
1159    switch (getTriple().getOS()) {
1160    case llvm::Triple::Linux:
1161    case llvm::Triple::FreeBSD:
1162    case llvm::Triple::NetBSD:
1163      SizeType = UnsignedInt;
1164      PtrDiffType = SignedInt;
1165      IntPtrType = SignedInt;
1166      break;
1167    default:
1168      break;
1169    }
1170
1171    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1172      LongDoubleWidth = LongDoubleAlign = 64;
1173      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1174    }
1175
1176    // PPC32 supports atomics up to 4 bytes.
1177    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1178  }
1179
1180  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1181    // This is the ELF definition, and is overridden by the Darwin sub-target
1182    return TargetInfo::PowerABIBuiltinVaList;
1183  }
1184};
1185} // end anonymous namespace.
1186
1187// Note: ABI differences may eventually require us to have a separate
1188// TargetInfo for little endian.
1189namespace {
1190class PPC64TargetInfo : public PPCTargetInfo {
1191public:
1192  PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1193    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1194    IntMaxType = SignedLong;
1195    UIntMaxType = UnsignedLong;
1196    Int64Type = SignedLong;
1197
1198    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1199      LongDoubleWidth = LongDoubleAlign = 64;
1200      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1201      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                          "i64:64:64-f32:32:32-f64:64:64-"
1203                          "v128:128:128-n32:64";
1204    } else
1205      DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1206                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1207                          "v128:128:128-n32:64";
1208
1209    // PPC64 supports atomics up to 8 bytes.
1210    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1211  }
1212  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1213    return TargetInfo::CharPtrBuiltinVaList;
1214  }
1215};
1216} // end anonymous namespace.
1217
1218
1219namespace {
1220class DarwinPPC32TargetInfo :
1221  public DarwinTargetInfo<PPC32TargetInfo> {
1222public:
1223  DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1224      : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1225    HasAlignMac68kSupport = true;
1226    BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1227    PtrDiffType = SignedInt;	// for http://llvm.org/bugs/show_bug.cgi?id=15726
1228    LongLongAlign = 32;
1229    SuitableAlign = 128;
1230    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1231                        "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1232  }
1233  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1234    return TargetInfo::CharPtrBuiltinVaList;
1235  }
1236};
1237
1238class DarwinPPC64TargetInfo :
1239  public DarwinTargetInfo<PPC64TargetInfo> {
1240public:
1241  DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1242      : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1243    HasAlignMac68kSupport = true;
1244    SuitableAlign = 128;
1245    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1246                        "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1247  }
1248};
1249} // end anonymous namespace.
1250
1251namespace {
1252  static const unsigned NVPTXAddrSpaceMap[] = {
1253    1,    // opencl_global
1254    3,    // opencl_local
1255    4,    // opencl_constant
1256    1,    // cuda_device
1257    4,    // cuda_constant
1258    3,    // cuda_shared
1259  };
1260  class NVPTXTargetInfo : public TargetInfo {
1261    static const char * const GCCRegNames[];
1262    static const Builtin::Info BuiltinInfo[];
1263  public:
1264    NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1265      BigEndian = false;
1266      TLSSupported = false;
1267      LongWidth = LongAlign = 64;
1268      AddrSpaceMap = &NVPTXAddrSpaceMap;
1269      UseAddrSpaceMapMangling = true;
1270      // Define available target features
1271      // These must be defined in sorted order!
1272      NoAsmVariants = true;
1273    }
1274    virtual void getTargetDefines(const LangOptions &Opts,
1275                                  MacroBuilder &Builder) const {
1276      Builder.defineMacro("__PTX__");
1277      Builder.defineMacro("__NVPTX__");
1278    }
1279    virtual void getTargetBuiltins(const Builtin::Info *&Records,
1280                                   unsigned &NumRecords) const {
1281      Records = BuiltinInfo;
1282      NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1283    }
1284    virtual bool hasFeature(StringRef Feature) const {
1285      return Feature == "ptx" || Feature == "nvptx";
1286    }
1287
1288    virtual void getGCCRegNames(const char * const *&Names,
1289                                unsigned &NumNames) const;
1290    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1291                                  unsigned &NumAliases) const {
1292      // No aliases.
1293      Aliases = 0;
1294      NumAliases = 0;
1295    }
1296    virtual bool validateAsmConstraint(const char *&Name,
1297                                       TargetInfo::ConstraintInfo &Info) const {
1298      switch (*Name) {
1299      default: return false;
1300      case 'c':
1301      case 'h':
1302      case 'r':
1303      case 'l':
1304      case 'f':
1305      case 'd':
1306        Info.setAllowsRegister();
1307        return true;
1308      }
1309    }
1310    virtual const char *getClobbers() const {
1311      // FIXME: Is this really right?
1312      return "";
1313    }
1314    virtual BuiltinVaListKind getBuiltinVaListKind() const {
1315      // FIXME: implement
1316      return TargetInfo::CharPtrBuiltinVaList;
1317    }
1318    virtual bool setCPU(const std::string &Name) {
1319      bool Valid = llvm::StringSwitch<bool>(Name)
1320        .Case("sm_20", true)
1321        .Case("sm_21", true)
1322        .Case("sm_30", true)
1323        .Case("sm_35", true)
1324        .Default(false);
1325
1326      return Valid;
1327    }
1328  };
1329
1330  const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1331#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1332#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1333                                              ALL_LANGUAGES },
1334#include "clang/Basic/BuiltinsNVPTX.def"
1335  };
1336
1337  const char * const NVPTXTargetInfo::GCCRegNames[] = {
1338    "r0"
1339  };
1340
1341  void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1342                                     unsigned &NumNames) const {
1343    Names = GCCRegNames;
1344    NumNames = llvm::array_lengthof(GCCRegNames);
1345  }
1346
1347  class NVPTX32TargetInfo : public NVPTXTargetInfo {
1348  public:
1349    NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1350      PointerWidth = PointerAlign = 32;
1351      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1352      DescriptionString
1353        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1354          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1355          "n16:32:64";
1356  }
1357  };
1358
1359  class NVPTX64TargetInfo : public NVPTXTargetInfo {
1360  public:
1361    NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1362      PointerWidth = PointerAlign = 64;
1363      SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1364      DescriptionString
1365        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1366          "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1367          "n16:32:64";
1368  }
1369  };
1370}
1371
1372namespace {
1373
1374static const unsigned R600AddrSpaceMap[] = {
1375  1,    // opencl_global
1376  3,    // opencl_local
1377  2,    // opencl_constant
1378  1,    // cuda_device
1379  2,    // cuda_constant
1380  3     // cuda_shared
1381};
1382
1383static const char *DescriptionStringR600 =
1384  "e"
1385  "-p:32:32:32"
1386  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1387  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1388  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1389  "-n32:64";
1390
1391static const char *DescriptionStringR600DoubleOps =
1392  "e"
1393  "-p:32:32:32"
1394  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1395  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1396  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1397  "-n32:64";
1398
1399static const char *DescriptionStringSI =
1400  "e"
1401  "-p:64:64:64"
1402  "-p3:32:32:32"
1403  "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1404  "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1405  "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1406  "-n32:64";
1407
1408class R600TargetInfo : public TargetInfo {
1409  /// \brief The GPU profiles supported by the R600 target.
1410  enum GPUKind {
1411    GK_NONE,
1412    GK_R600,
1413    GK_R600_DOUBLE_OPS,
1414    GK_R700,
1415    GK_R700_DOUBLE_OPS,
1416    GK_EVERGREEN,
1417    GK_EVERGREEN_DOUBLE_OPS,
1418    GK_NORTHERN_ISLANDS,
1419    GK_CAYMAN,
1420    GK_SOUTHERN_ISLANDS
1421  } GPU;
1422
1423public:
1424  R600TargetInfo(const llvm::Triple &Triple)
1425      : TargetInfo(Triple), GPU(GK_R600) {
1426    DescriptionString = DescriptionStringR600;
1427    AddrSpaceMap = &R600AddrSpaceMap;
1428    UseAddrSpaceMapMangling = true;
1429  }
1430
1431  virtual const char * getClobbers() const {
1432    return "";
1433  }
1434
1435  virtual void getGCCRegNames(const char * const *&Names,
1436                              unsigned &numNames) const  {
1437    Names = NULL;
1438    numNames = 0;
1439  }
1440
1441  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1442                                unsigned &NumAliases) const {
1443    Aliases = NULL;
1444    NumAliases = 0;
1445  }
1446
1447  virtual bool validateAsmConstraint(const char *&Name,
1448                                     TargetInfo::ConstraintInfo &info) const {
1449    return true;
1450  }
1451
1452  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1453                                 unsigned &NumRecords) const {
1454    Records = NULL;
1455    NumRecords = 0;
1456  }
1457
1458
1459  virtual void getTargetDefines(const LangOptions &Opts,
1460                                MacroBuilder &Builder) const {
1461    Builder.defineMacro("__R600__");
1462  }
1463
1464  virtual BuiltinVaListKind getBuiltinVaListKind() const {
1465    return TargetInfo::CharPtrBuiltinVaList;
1466  }
1467
1468  virtual bool setCPU(const std::string &Name) {
1469    GPU = llvm::StringSwitch<GPUKind>(Name)
1470      .Case("r600" ,    GK_R600)
1471      .Case("rv610",    GK_R600)
1472      .Case("rv620",    GK_R600)
1473      .Case("rv630",    GK_R600)
1474      .Case("rv635",    GK_R600)
1475      .Case("rs780",    GK_R600)
1476      .Case("rs880",    GK_R600)
1477      .Case("rv670",    GK_R600_DOUBLE_OPS)
1478      .Case("rv710",    GK_R700)
1479      .Case("rv730",    GK_R700)
1480      .Case("rv740",    GK_R700_DOUBLE_OPS)
1481      .Case("rv770",    GK_R700_DOUBLE_OPS)
1482      .Case("palm",     GK_EVERGREEN)
1483      .Case("cedar",    GK_EVERGREEN)
1484      .Case("sumo",     GK_EVERGREEN)
1485      .Case("sumo2",    GK_EVERGREEN)
1486      .Case("redwood",  GK_EVERGREEN)
1487      .Case("juniper",  GK_EVERGREEN)
1488      .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1489      .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1490      .Case("barts",    GK_NORTHERN_ISLANDS)
1491      .Case("turks",    GK_NORTHERN_ISLANDS)
1492      .Case("caicos",   GK_NORTHERN_ISLANDS)
1493      .Case("cayman",   GK_CAYMAN)
1494      .Case("aruba",    GK_CAYMAN)
1495      .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1496      .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1497      .Case("verde",    GK_SOUTHERN_ISLANDS)
1498      .Case("oland",    GK_SOUTHERN_ISLANDS)
1499      .Default(GK_NONE);
1500
1501    if (GPU == GK_NONE) {
1502      return false;
1503    }
1504
1505    // Set the correct data layout
1506    switch (GPU) {
1507    case GK_NONE:
1508    case GK_R600:
1509    case GK_R700:
1510    case GK_EVERGREEN:
1511    case GK_NORTHERN_ISLANDS:
1512      DescriptionString = DescriptionStringR600;
1513      break;
1514    case GK_R600_DOUBLE_OPS:
1515    case GK_R700_DOUBLE_OPS:
1516    case GK_EVERGREEN_DOUBLE_OPS:
1517    case GK_CAYMAN:
1518      DescriptionString = DescriptionStringR600DoubleOps;
1519      break;
1520    case GK_SOUTHERN_ISLANDS:
1521      DescriptionString = DescriptionStringSI;
1522      break;
1523    }
1524
1525    return true;
1526  }
1527};
1528
1529} // end anonymous namespace
1530
1531namespace {
1532// Namespace for x86 abstract base class
1533const Builtin::Info BuiltinInfo[] = {
1534#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1535#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1536                                              ALL_LANGUAGES },
1537#include "clang/Basic/BuiltinsX86.def"
1538};
1539
1540static const char* const GCCRegNames[] = {
1541  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1542  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1543  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1544  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1545  "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1546  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1547  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1548  "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1549  "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1550};
1551
1552const TargetInfo::AddlRegName AddlRegNames[] = {
1553  { { "al", "ah", "eax", "rax" }, 0 },
1554  { { "bl", "bh", "ebx", "rbx" }, 3 },
1555  { { "cl", "ch", "ecx", "rcx" }, 2 },
1556  { { "dl", "dh", "edx", "rdx" }, 1 },
1557  { { "esi", "rsi" }, 4 },
1558  { { "edi", "rdi" }, 5 },
1559  { { "esp", "rsp" }, 7 },
1560  { { "ebp", "rbp" }, 6 },
1561};
1562
1563// X86 target abstract base class; x86-32 and x86-64 are very close, so
1564// most of the implementation can be shared.
1565class X86TargetInfo : public TargetInfo {
1566  enum X86SSEEnum {
1567    NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1568  } SSELevel;
1569  enum MMX3DNowEnum {
1570    NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1571  } MMX3DNowLevel;
1572  enum XOPEnum {
1573    NoXOP,
1574    SSE4A,
1575    FMA4,
1576    XOP
1577  } XOPLevel;
1578
1579  bool HasAES;
1580  bool HasPCLMUL;
1581  bool HasLZCNT;
1582  bool HasRDRND;
1583  bool HasBMI;
1584  bool HasBMI2;
1585  bool HasPOPCNT;
1586  bool HasRTM;
1587  bool HasPRFCHW;
1588  bool HasRDSEED;
1589  bool HasFMA;
1590  bool HasF16C;
1591  bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
1592  bool HasSHA;
1593
1594  /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1595  ///
1596  /// Each enumeration represents a particular CPU supported by Clang. These
1597  /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1598  enum CPUKind {
1599    CK_Generic,
1600
1601    /// \name i386
1602    /// i386-generation processors.
1603    //@{
1604    CK_i386,
1605    //@}
1606
1607    /// \name i486
1608    /// i486-generation processors.
1609    //@{
1610    CK_i486,
1611    CK_WinChipC6,
1612    CK_WinChip2,
1613    CK_C3,
1614    //@}
1615
1616    /// \name i586
1617    /// i586-generation processors, P5 microarchitecture based.
1618    //@{
1619    CK_i586,
1620    CK_Pentium,
1621    CK_PentiumMMX,
1622    //@}
1623
1624    /// \name i686
1625    /// i686-generation processors, P6 / Pentium M microarchitecture based.
1626    //@{
1627    CK_i686,
1628    CK_PentiumPro,
1629    CK_Pentium2,
1630    CK_Pentium3,
1631    CK_Pentium3M,
1632    CK_PentiumM,
1633    CK_C3_2,
1634
1635    /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1636    /// Clang however has some logic to suport this.
1637    // FIXME: Warn, deprecate, and potentially remove this.
1638    CK_Yonah,
1639    //@}
1640
1641    /// \name Netburst
1642    /// Netburst microarchitecture based processors.
1643    //@{
1644    CK_Pentium4,
1645    CK_Pentium4M,
1646    CK_Prescott,
1647    CK_Nocona,
1648    //@}
1649
1650    /// \name Core
1651    /// Core microarchitecture based processors.
1652    //@{
1653    CK_Core2,
1654
1655    /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1656    /// codename which GCC no longer accepts as an option to -march, but Clang
1657    /// has some logic for recognizing it.
1658    // FIXME: Warn, deprecate, and potentially remove this.
1659    CK_Penryn,
1660    //@}
1661
1662    /// \name Atom
1663    /// Atom processors
1664    //@{
1665    CK_Atom,
1666    CK_Silvermont,
1667    //@}
1668
1669    /// \name Nehalem
1670    /// Nehalem microarchitecture based processors.
1671    //@{
1672    CK_Corei7,
1673    CK_Corei7AVX,
1674    CK_CoreAVXi,
1675    CK_CoreAVX2,
1676    //@}
1677
1678    /// \name Knights Landing
1679    /// Knights Landing processor.
1680    CK_KNL,
1681
1682    /// \name K6
1683    /// K6 architecture processors.
1684    //@{
1685    CK_K6,
1686    CK_K6_2,
1687    CK_K6_3,
1688    //@}
1689
1690    /// \name K7
1691    /// K7 architecture processors.
1692    //@{
1693    CK_Athlon,
1694    CK_AthlonThunderbird,
1695    CK_Athlon4,
1696    CK_AthlonXP,
1697    CK_AthlonMP,
1698    //@}
1699
1700    /// \name K8
1701    /// K8 architecture processors.
1702    //@{
1703    CK_Athlon64,
1704    CK_Athlon64SSE3,
1705    CK_AthlonFX,
1706    CK_K8,
1707    CK_K8SSE3,
1708    CK_Opteron,
1709    CK_OpteronSSE3,
1710    CK_AMDFAM10,
1711    //@}
1712
1713    /// \name Bobcat
1714    /// Bobcat architecture processors.
1715    //@{
1716    CK_BTVER1,
1717    CK_BTVER2,
1718    //@}
1719
1720    /// \name Bulldozer
1721    /// Bulldozer architecture processors.
1722    //@{
1723    CK_BDVER1,
1724    CK_BDVER2,
1725    //@}
1726
1727    /// This specification is deprecated and will be removed in the future.
1728    /// Users should prefer \see CK_K8.
1729    // FIXME: Warn on this when the CPU is set to it.
1730    CK_x86_64,
1731    //@}
1732
1733    /// \name Geode
1734    /// Geode processors.
1735    //@{
1736    CK_Geode
1737    //@}
1738  } CPU;
1739
1740  enum FPMathKind {
1741    FP_Default,
1742    FP_SSE,
1743    FP_387
1744  } FPMath;
1745
1746public:
1747  X86TargetInfo(const llvm::Triple &Triple)
1748      : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1749        XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1750        HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1751        HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasFMA(false),
1752        HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
1753        HasAVX512PF(false), HasSHA(false), CPU(CK_Generic), FPMath(FP_Default) {
1754    BigEndian = false;
1755    LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1756  }
1757  virtual unsigned getFloatEvalMethod() const {
1758    // X87 evaluates with 80 bits "long double" precision.
1759    return SSELevel == NoSSE ? 2 : 0;
1760  }
1761  virtual void getTargetBuiltins(const Builtin::Info *&Records,
1762                                 unsigned &NumRecords) const {
1763    Records = BuiltinInfo;
1764    NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1765  }
1766  virtual void getGCCRegNames(const char * const *&Names,
1767                              unsigned &NumNames) const {
1768    Names = GCCRegNames;
1769    NumNames = llvm::array_lengthof(GCCRegNames);
1770  }
1771  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1772                                unsigned &NumAliases) const {
1773    Aliases = 0;
1774    NumAliases = 0;
1775  }
1776  virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1777                                  unsigned &NumNames) const {
1778    Names = AddlRegNames;
1779    NumNames = llvm::array_lengthof(AddlRegNames);
1780  }
1781  virtual bool validateAsmConstraint(const char *&Name,
1782                                     TargetInfo::ConstraintInfo &info) const;
1783  virtual std::string convertConstraint(const char *&Constraint) const;
1784  virtual const char *getClobbers() const {
1785    return "~{dirflag},~{fpsr},~{flags}";
1786  }
1787  virtual void getTargetDefines(const LangOptions &Opts,
1788                                MacroBuilder &Builder) const;
1789  static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1790                          bool Enabled);
1791  static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1792                          bool Enabled);
1793  static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1794                          bool Enabled);
1795  virtual void setFeatureEnabled(llvm::StringMap<bool> &Features,
1796                                 StringRef Name, bool Enabled) const {
1797    setFeatureEnabledImpl(Features, Name, Enabled);
1798  }
1799  // This exists purely to cut down on the number of virtual calls in
1800  // getDefaultFeatures which calls this repeatedly.
1801  static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1802                                    StringRef Name, bool Enabled);
1803  virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1804  virtual bool hasFeature(StringRef Feature) const;
1805  virtual bool HandleTargetFeatures(std::vector<std::string> &Features,
1806                                    DiagnosticsEngine &Diags);
1807  virtual const char* getABI() const {
1808    if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1809      return "avx";
1810    else if (getTriple().getArch() == llvm::Triple::x86 &&
1811             MMX3DNowLevel == NoMMX3DNow)
1812      return "no-mmx";
1813    return "";
1814  }
1815  virtual bool setCPU(const std::string &Name) {
1816    CPU = llvm::StringSwitch<CPUKind>(Name)
1817      .Case("i386", CK_i386)
1818      .Case("i486", CK_i486)
1819      .Case("winchip-c6", CK_WinChipC6)
1820      .Case("winchip2", CK_WinChip2)
1821      .Case("c3", CK_C3)
1822      .Case("i586", CK_i586)
1823      .Case("pentium", CK_Pentium)
1824      .Case("pentium-mmx", CK_PentiumMMX)
1825      .Case("i686", CK_i686)
1826      .Case("pentiumpro", CK_PentiumPro)
1827      .Case("pentium2", CK_Pentium2)
1828      .Case("pentium3", CK_Pentium3)
1829      .Case("pentium3m", CK_Pentium3M)
1830      .Case("pentium-m", CK_PentiumM)
1831      .Case("c3-2", CK_C3_2)
1832      .Case("yonah", CK_Yonah)
1833      .Case("pentium4", CK_Pentium4)
1834      .Case("pentium4m", CK_Pentium4M)
1835      .Case("prescott", CK_Prescott)
1836      .Case("nocona", CK_Nocona)
1837      .Case("core2", CK_Core2)
1838      .Case("penryn", CK_Penryn)
1839      .Case("atom", CK_Atom)
1840      .Case("slm", CK_Silvermont)
1841      .Case("corei7", CK_Corei7)
1842      .Case("corei7-avx", CK_Corei7AVX)
1843      .Case("core-avx-i", CK_CoreAVXi)
1844      .Case("core-avx2", CK_CoreAVX2)
1845      .Case("knl", CK_KNL)
1846      .Case("k6", CK_K6)
1847      .Case("k6-2", CK_K6_2)
1848      .Case("k6-3", CK_K6_3)
1849      .Case("athlon", CK_Athlon)
1850      .Case("athlon-tbird", CK_AthlonThunderbird)
1851      .Case("athlon-4", CK_Athlon4)
1852      .Case("athlon-xp", CK_AthlonXP)
1853      .Case("athlon-mp", CK_AthlonMP)
1854      .Case("athlon64", CK_Athlon64)
1855      .Case("athlon64-sse3", CK_Athlon64SSE3)
1856      .Case("athlon-fx", CK_AthlonFX)
1857      .Case("k8", CK_K8)
1858      .Case("k8-sse3", CK_K8SSE3)
1859      .Case("opteron", CK_Opteron)
1860      .Case("opteron-sse3", CK_OpteronSSE3)
1861      .Case("amdfam10", CK_AMDFAM10)
1862      .Case("btver1", CK_BTVER1)
1863      .Case("btver2", CK_BTVER2)
1864      .Case("bdver1", CK_BDVER1)
1865      .Case("bdver2", CK_BDVER2)
1866      .Case("x86-64", CK_x86_64)
1867      .Case("geode", CK_Geode)
1868      .Default(CK_Generic);
1869
1870    // Perform any per-CPU checks necessary to determine if this CPU is
1871    // acceptable.
1872    // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1873    // invalid without explaining *why*.
1874    switch (CPU) {
1875    case CK_Generic:
1876      // No processor selected!
1877      return false;
1878
1879    case CK_i386:
1880    case CK_i486:
1881    case CK_WinChipC6:
1882    case CK_WinChip2:
1883    case CK_C3:
1884    case CK_i586:
1885    case CK_Pentium:
1886    case CK_PentiumMMX:
1887    case CK_i686:
1888    case CK_PentiumPro:
1889    case CK_Pentium2:
1890    case CK_Pentium3:
1891    case CK_Pentium3M:
1892    case CK_PentiumM:
1893    case CK_Yonah:
1894    case CK_C3_2:
1895    case CK_Pentium4:
1896    case CK_Pentium4M:
1897    case CK_Prescott:
1898    case CK_K6:
1899    case CK_K6_2:
1900    case CK_K6_3:
1901    case CK_Athlon:
1902    case CK_AthlonThunderbird:
1903    case CK_Athlon4:
1904    case CK_AthlonXP:
1905    case CK_AthlonMP:
1906    case CK_Geode:
1907      // Only accept certain architectures when compiling in 32-bit mode.
1908      if (getTriple().getArch() != llvm::Triple::x86)
1909        return false;
1910
1911      // Fallthrough
1912    case CK_Nocona:
1913    case CK_Core2:
1914    case CK_Penryn:
1915    case CK_Atom:
1916    case CK_Silvermont:
1917    case CK_Corei7:
1918    case CK_Corei7AVX:
1919    case CK_CoreAVXi:
1920    case CK_CoreAVX2:
1921    case CK_KNL:
1922    case CK_Athlon64:
1923    case CK_Athlon64SSE3:
1924    case CK_AthlonFX:
1925    case CK_K8:
1926    case CK_K8SSE3:
1927    case CK_Opteron:
1928    case CK_OpteronSSE3:
1929    case CK_AMDFAM10:
1930    case CK_BTVER1:
1931    case CK_BTVER2:
1932    case CK_BDVER1:
1933    case CK_BDVER2:
1934    case CK_x86_64:
1935      return true;
1936    }
1937    llvm_unreachable("Unhandled CPU kind");
1938  }
1939
1940  virtual bool setFPMath(StringRef Name);
1941
1942  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1943    // We accept all non-ARM calling conventions
1944    return (CC == CC_X86ThisCall ||
1945            CC == CC_X86FastCall ||
1946            CC == CC_X86StdCall ||
1947            CC == CC_C ||
1948            CC == CC_X86Pascal ||
1949            CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
1950  }
1951
1952  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
1953    return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
1954  }
1955};
1956
1957bool X86TargetInfo::setFPMath(StringRef Name) {
1958  if (Name == "387") {
1959    FPMath = FP_387;
1960    return true;
1961  }
1962  if (Name == "sse") {
1963    FPMath = FP_SSE;
1964    return true;
1965  }
1966  return false;
1967}
1968
1969void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1970  // FIXME: This *really* should not be here.
1971
1972  // X86_64 always has SSE2.
1973  if (getTriple().getArch() == llvm::Triple::x86_64)
1974    setFeatureEnabledImpl(Features, "sse2", true);
1975
1976  switch (CPU) {
1977  case CK_Generic:
1978  case CK_i386:
1979  case CK_i486:
1980  case CK_i586:
1981  case CK_Pentium:
1982  case CK_i686:
1983  case CK_PentiumPro:
1984    break;
1985  case CK_PentiumMMX:
1986  case CK_Pentium2:
1987    setFeatureEnabledImpl(Features, "mmx", true);
1988    break;
1989  case CK_Pentium3:
1990  case CK_Pentium3M:
1991    setFeatureEnabledImpl(Features, "sse", true);
1992    break;
1993  case CK_PentiumM:
1994  case CK_Pentium4:
1995  case CK_Pentium4M:
1996  case CK_x86_64:
1997    setFeatureEnabledImpl(Features, "sse2", true);
1998    break;
1999  case CK_Yonah:
2000  case CK_Prescott:
2001  case CK_Nocona:
2002    setFeatureEnabledImpl(Features, "sse3", true);
2003    break;
2004  case CK_Core2:
2005    setFeatureEnabledImpl(Features, "ssse3", true);
2006    break;
2007  case CK_Penryn:
2008    setFeatureEnabledImpl(Features, "sse4.1", true);
2009    break;
2010  case CK_Atom:
2011    setFeatureEnabledImpl(Features, "ssse3", true);
2012    break;
2013  case CK_Silvermont:
2014    setFeatureEnabledImpl(Features, "sse4.2", true);
2015    setFeatureEnabledImpl(Features, "aes", true);
2016    setFeatureEnabledImpl(Features, "pclmul", true);
2017    break;
2018  case CK_Corei7:
2019    setFeatureEnabledImpl(Features, "sse4.2", true);
2020    break;
2021  case CK_Corei7AVX:
2022    setFeatureEnabledImpl(Features, "avx", true);
2023    setFeatureEnabledImpl(Features, "aes", true);
2024    setFeatureEnabledImpl(Features, "pclmul", true);
2025    break;
2026  case CK_CoreAVXi:
2027    setFeatureEnabledImpl(Features, "avx", true);
2028    setFeatureEnabledImpl(Features, "aes", true);
2029    setFeatureEnabledImpl(Features, "pclmul", true);
2030    setFeatureEnabledImpl(Features, "rdrnd", true);
2031    setFeatureEnabledImpl(Features, "f16c", true);
2032    break;
2033  case CK_CoreAVX2:
2034    setFeatureEnabledImpl(Features, "avx2", true);
2035    setFeatureEnabledImpl(Features, "aes", true);
2036    setFeatureEnabledImpl(Features, "pclmul", true);
2037    setFeatureEnabledImpl(Features, "lzcnt", true);
2038    setFeatureEnabledImpl(Features, "rdrnd", true);
2039    setFeatureEnabledImpl(Features, "f16c", true);
2040    setFeatureEnabledImpl(Features, "bmi", true);
2041    setFeatureEnabledImpl(Features, "bmi2", true);
2042    setFeatureEnabledImpl(Features, "rtm", true);
2043    setFeatureEnabledImpl(Features, "fma", true);
2044    break;
2045  case CK_KNL:
2046    setFeatureEnabledImpl(Features, "avx512f", true);
2047    setFeatureEnabledImpl(Features, "avx512cd", true);
2048    setFeatureEnabledImpl(Features, "avx512er", true);
2049    setFeatureEnabledImpl(Features, "avx512pf", true);
2050    setFeatureEnabledImpl(Features, "aes", true);
2051    setFeatureEnabledImpl(Features, "pclmul", true);
2052    setFeatureEnabledImpl(Features, "lzcnt", true);
2053    setFeatureEnabledImpl(Features, "rdrnd", true);
2054    setFeatureEnabledImpl(Features, "f16c", true);
2055    setFeatureEnabledImpl(Features, "bmi", true);
2056    setFeatureEnabledImpl(Features, "bmi2", true);
2057    setFeatureEnabledImpl(Features, "rtm", true);
2058    setFeatureEnabledImpl(Features, "fma", true);
2059    break;
2060  case CK_K6:
2061  case CK_WinChipC6:
2062    setFeatureEnabledImpl(Features, "mmx", true);
2063    break;
2064  case CK_K6_2:
2065  case CK_K6_3:
2066  case CK_WinChip2:
2067  case CK_C3:
2068    setFeatureEnabledImpl(Features, "3dnow", true);
2069    break;
2070  case CK_Athlon:
2071  case CK_AthlonThunderbird:
2072  case CK_Geode:
2073    setFeatureEnabledImpl(Features, "3dnowa", true);
2074    break;
2075  case CK_Athlon4:
2076  case CK_AthlonXP:
2077  case CK_AthlonMP:
2078    setFeatureEnabledImpl(Features, "sse", true);
2079    setFeatureEnabledImpl(Features, "3dnowa", true);
2080    break;
2081  case CK_K8:
2082  case CK_Opteron:
2083  case CK_Athlon64:
2084  case CK_AthlonFX:
2085    setFeatureEnabledImpl(Features, "sse2", true);
2086    setFeatureEnabledImpl(Features, "3dnowa", true);
2087    break;
2088  case CK_K8SSE3:
2089  case CK_OpteronSSE3:
2090  case CK_Athlon64SSE3:
2091    setFeatureEnabledImpl(Features, "sse3", true);
2092    setFeatureEnabledImpl(Features, "3dnowa", true);
2093    break;
2094  case CK_AMDFAM10:
2095    setFeatureEnabledImpl(Features, "sse3", true);
2096    setFeatureEnabledImpl(Features, "sse4a", true);
2097    setFeatureEnabledImpl(Features, "3dnowa", true);
2098    setFeatureEnabledImpl(Features, "lzcnt", true);
2099    setFeatureEnabledImpl(Features, "popcnt", true);
2100    break;
2101  case CK_BTVER1:
2102    setFeatureEnabledImpl(Features, "ssse3", true);
2103    setFeatureEnabledImpl(Features, "sse4a", true);
2104    setFeatureEnabledImpl(Features, "lzcnt", true);
2105    setFeatureEnabledImpl(Features, "popcnt", true);
2106    break;
2107  case CK_BTVER2:
2108    setFeatureEnabledImpl(Features, "avx", true);
2109    setFeatureEnabledImpl(Features, "sse4a", true);
2110    setFeatureEnabledImpl(Features, "lzcnt", true);
2111    setFeatureEnabledImpl(Features, "aes", true);
2112    setFeatureEnabledImpl(Features, "pclmul", true);
2113    setFeatureEnabledImpl(Features, "bmi", true);
2114    setFeatureEnabledImpl(Features, "f16c", true);
2115    break;
2116  case CK_BDVER1:
2117    setFeatureEnabledImpl(Features, "xop", true);
2118    setFeatureEnabledImpl(Features, "lzcnt", true);
2119    setFeatureEnabledImpl(Features, "aes", true);
2120    setFeatureEnabledImpl(Features, "pclmul", true);
2121    break;
2122  case CK_BDVER2:
2123    setFeatureEnabledImpl(Features, "xop", true);
2124    setFeatureEnabledImpl(Features, "lzcnt", true);
2125    setFeatureEnabledImpl(Features, "aes", true);
2126    setFeatureEnabledImpl(Features, "pclmul", true);
2127    setFeatureEnabledImpl(Features, "bmi", true);
2128    setFeatureEnabledImpl(Features, "fma", true);
2129    setFeatureEnabledImpl(Features, "f16c", true);
2130    break;
2131  case CK_C3_2:
2132    setFeatureEnabledImpl(Features, "sse", true);
2133    break;
2134  }
2135}
2136
2137void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2138                                X86SSEEnum Level, bool Enabled) {
2139  if (Enabled) {
2140    switch (Level) {
2141    case AVX512F:
2142      Features["avx512f"] = true;
2143    case AVX2:
2144      Features["avx2"] = true;
2145    case AVX:
2146      Features["avx"] = true;
2147    case SSE42:
2148      Features["sse4.2"] = true;
2149    case SSE41:
2150      Features["sse4.1"] = true;
2151    case SSSE3:
2152      Features["ssse3"] = true;
2153    case SSE3:
2154      Features["sse3"] = true;
2155    case SSE2:
2156      Features["sse2"] = true;
2157    case SSE1:
2158      Features["sse"] = true;
2159    case NoSSE:
2160      break;
2161    }
2162    return;
2163  }
2164
2165  switch (Level) {
2166  case NoSSE:
2167  case SSE1:
2168    Features["sse"] = false;
2169  case SSE2:
2170    Features["sse2"] = Features["pclmul"] = Features["aes"] =
2171      Features["sha"] = false;
2172  case SSE3:
2173    Features["sse3"] = false;
2174    setXOPLevel(Features, NoXOP, false);
2175  case SSSE3:
2176    Features["ssse3"] = false;
2177  case SSE41:
2178    Features["sse4.1"] = false;
2179  case SSE42:
2180    Features["sse4.2"] = false;
2181  case AVX:
2182    Features["fma"] = Features["avx"] = Features["f16c"] = false;
2183    setXOPLevel(Features, FMA4, false);
2184  case AVX2:
2185    Features["avx2"] = false;
2186  case AVX512F:
2187    Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2188      Features["avx512pf"] = false;
2189  }
2190}
2191
2192void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2193                                MMX3DNowEnum Level, bool Enabled) {
2194  if (Enabled) {
2195    switch (Level) {
2196    case AMD3DNowAthlon:
2197      Features["3dnowa"] = true;
2198    case AMD3DNow:
2199      Features["3dnow"] = true;
2200    case MMX:
2201      Features["mmx"] = true;
2202    case NoMMX3DNow:
2203      break;
2204    }
2205    return;
2206  }
2207
2208  switch (Level) {
2209  case NoMMX3DNow:
2210  case MMX:
2211    Features["mmx"] = false;
2212  case AMD3DNow:
2213    Features["3dnow"] = false;
2214  case AMD3DNowAthlon:
2215    Features["3dnowa"] = false;
2216  }
2217}
2218
2219void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2220                                bool Enabled) {
2221  if (Enabled) {
2222    switch (Level) {
2223    case XOP:
2224      Features["xop"] = true;
2225    case FMA4:
2226      Features["fma4"] = true;
2227      setSSELevel(Features, AVX, true);
2228    case SSE4A:
2229      Features["sse4a"] = true;
2230      setSSELevel(Features, SSE3, true);
2231    case NoXOP:
2232      break;
2233    }
2234    return;
2235  }
2236
2237  switch (Level) {
2238  case NoXOP:
2239  case SSE4A:
2240    Features["sse4a"] = false;
2241  case FMA4:
2242    Features["fma4"] = false;
2243  case XOP:
2244    Features["xop"] = false;
2245  }
2246}
2247
2248void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2249                                          StringRef Name, bool Enabled) {
2250  // FIXME: This *really* should not be here.  We need some way of translating
2251  // options into llvm subtarget features.
2252  if (Name == "sse4")
2253    Name = "sse4.2";
2254
2255  Features[Name] = Enabled;
2256
2257  if (Name == "mmx") {
2258    setMMXLevel(Features, MMX, Enabled);
2259  } else if (Name == "sse") {
2260    setSSELevel(Features, SSE1, Enabled);
2261  } else if (Name == "sse2") {
2262    setSSELevel(Features, SSE2, Enabled);
2263  } else if (Name == "sse3") {
2264    setSSELevel(Features, SSE3, Enabled);
2265  } else if (Name == "ssse3") {
2266    setSSELevel(Features, SSSE3, Enabled);
2267  } else if (Name == "sse4.2") {
2268    setSSELevel(Features, SSE42, Enabled);
2269  } else if (Name == "sse4.1") {
2270    setSSELevel(Features, SSE41, Enabled);
2271  } else if (Name == "3dnow") {
2272    setMMXLevel(Features, AMD3DNow, Enabled);
2273  } else if (Name == "3dnowa") {
2274    setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2275  } else if (Name == "aes") {
2276    if (Enabled)
2277      setSSELevel(Features, SSE2, Enabled);
2278  } else if (Name == "pclmul") {
2279    if (Enabled)
2280      setSSELevel(Features, SSE2, Enabled);
2281  } else if (Name == "avx") {
2282    setSSELevel(Features, AVX, Enabled);
2283  } else if (Name == "avx2") {
2284    setSSELevel(Features, AVX2, Enabled);
2285  } else if (Name == "avx512f") {
2286    setSSELevel(Features, AVX512F, Enabled);
2287  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
2288    if (Enabled)
2289      setSSELevel(Features, AVX512F, Enabled);
2290  } else if (Name == "fma") {
2291    if (Enabled)
2292      setSSELevel(Features, AVX, Enabled);
2293  } else if (Name == "fma4") {
2294    setXOPLevel(Features, FMA4, Enabled);
2295  } else if (Name == "xop") {
2296    setXOPLevel(Features, XOP, Enabled);
2297  } else if (Name == "sse4a") {
2298    setXOPLevel(Features, SSE4A, Enabled);
2299  } else if (Name == "f16c") {
2300    if (Enabled)
2301      setSSELevel(Features, AVX, Enabled);
2302  } else if (Name == "sha") {
2303    if (Enabled)
2304      setSSELevel(Features, SSE2, Enabled);
2305  }
2306}
2307
2308/// HandleTargetOptions - Perform initialization based on the user
2309/// configured set of features.
2310bool X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features,
2311                                         DiagnosticsEngine &Diags) {
2312  // Remember the maximum enabled sselevel.
2313  for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2314    // Ignore disabled features.
2315    if (Features[i][0] == '-')
2316      continue;
2317
2318    StringRef Feature = StringRef(Features[i]).substr(1);
2319
2320    if (Feature == "aes") {
2321      HasAES = true;
2322      continue;
2323    }
2324
2325    if (Feature == "pclmul") {
2326      HasPCLMUL = true;
2327      continue;
2328    }
2329
2330    if (Feature == "lzcnt") {
2331      HasLZCNT = true;
2332      continue;
2333    }
2334
2335    if (Feature == "rdrnd") {
2336      HasRDRND = true;
2337      continue;
2338    }
2339
2340    if (Feature == "bmi") {
2341      HasBMI = true;
2342      continue;
2343    }
2344
2345    if (Feature == "bmi2") {
2346      HasBMI2 = true;
2347      continue;
2348    }
2349
2350    if (Feature == "popcnt") {
2351      HasPOPCNT = true;
2352      continue;
2353    }
2354
2355    if (Feature == "rtm") {
2356      HasRTM = true;
2357      continue;
2358    }
2359
2360    if (Feature == "prfchw") {
2361      HasPRFCHW = true;
2362      continue;
2363    }
2364
2365    if (Feature == "rdseed") {
2366      HasRDSEED = true;
2367      continue;
2368    }
2369
2370    if (Feature == "fma") {
2371      HasFMA = true;
2372      continue;
2373    }
2374
2375    if (Feature == "f16c") {
2376      HasF16C = true;
2377      continue;
2378    }
2379
2380    if (Feature == "avx512cd") {
2381      HasAVX512CD = true;
2382      continue;
2383    }
2384
2385    if (Feature == "avx512er") {
2386      HasAVX512ER = true;
2387      continue;
2388    }
2389
2390    if (Feature == "avx512pf") {
2391      HasAVX512PF = true;
2392      continue;
2393    }
2394
2395    if (Feature == "sha") {
2396      HasSHA = true;
2397      continue;
2398    }
2399
2400    assert(Features[i][0] == '+' && "Invalid target feature!");
2401    X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2402      .Case("avx512f", AVX512F)
2403      .Case("avx2", AVX2)
2404      .Case("avx", AVX)
2405      .Case("sse4.2", SSE42)
2406      .Case("sse4.1", SSE41)
2407      .Case("ssse3", SSSE3)
2408      .Case("sse3", SSE3)
2409      .Case("sse2", SSE2)
2410      .Case("sse", SSE1)
2411      .Default(NoSSE);
2412    SSELevel = std::max(SSELevel, Level);
2413
2414    MMX3DNowEnum ThreeDNowLevel =
2415      llvm::StringSwitch<MMX3DNowEnum>(Feature)
2416        .Case("3dnowa", AMD3DNowAthlon)
2417        .Case("3dnow", AMD3DNow)
2418        .Case("mmx", MMX)
2419        .Default(NoMMX3DNow);
2420    MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2421
2422    XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2423        .Case("xop", XOP)
2424        .Case("fma4", FMA4)
2425        .Case("sse4a", SSE4A)
2426        .Default(NoXOP);
2427    XOPLevel = std::max(XOPLevel, XLevel);
2428  }
2429
2430  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2431  // Can't do this earlier because we need to be able to explicitly enable
2432  // popcnt and still disable sse4.2.
2433  if (!HasPOPCNT && SSELevel >= SSE42 &&
2434      std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2435    HasPOPCNT = true;
2436    Features.push_back("+popcnt");
2437  }
2438
2439  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2440  // matches the selected sse level.
2441  if (FPMath == FP_SSE && SSELevel < SSE1) {
2442    Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2443    return false;
2444  } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2445    Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2446    return false;
2447  }
2448
2449  // Don't tell the backend if we're turning off mmx; it will end up disabling
2450  // SSE, which we don't want.
2451  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2452  // then enable MMX.
2453  std::vector<std::string>::iterator it;
2454  it = std::find(Features.begin(), Features.end(), "-mmx");
2455  if (it != Features.end())
2456    Features.erase(it);
2457  else if (SSELevel > NoSSE)
2458    MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2459  return true;
2460}
2461
2462/// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2463/// definitions for this particular subtarget.
2464void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2465                                     MacroBuilder &Builder) const {
2466  // Target identification.
2467  if (getTriple().getArch() == llvm::Triple::x86_64) {
2468    Builder.defineMacro("__amd64__");
2469    Builder.defineMacro("__amd64");
2470    Builder.defineMacro("__x86_64");
2471    Builder.defineMacro("__x86_64__");
2472  } else {
2473    DefineStd(Builder, "i386", Opts);
2474  }
2475
2476  // Subtarget options.
2477  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2478  // truly should be based on -mtune options.
2479  switch (CPU) {
2480  case CK_Generic:
2481    break;
2482  case CK_i386:
2483    // The rest are coming from the i386 define above.
2484    Builder.defineMacro("__tune_i386__");
2485    break;
2486  case CK_i486:
2487  case CK_WinChipC6:
2488  case CK_WinChip2:
2489  case CK_C3:
2490    defineCPUMacros(Builder, "i486");
2491    break;
2492  case CK_PentiumMMX:
2493    Builder.defineMacro("__pentium_mmx__");
2494    Builder.defineMacro("__tune_pentium_mmx__");
2495    // Fallthrough
2496  case CK_i586:
2497  case CK_Pentium:
2498    defineCPUMacros(Builder, "i586");
2499    defineCPUMacros(Builder, "pentium");
2500    break;
2501  case CK_Pentium3:
2502  case CK_Pentium3M:
2503  case CK_PentiumM:
2504    Builder.defineMacro("__tune_pentium3__");
2505    // Fallthrough
2506  case CK_Pentium2:
2507  case CK_C3_2:
2508    Builder.defineMacro("__tune_pentium2__");
2509    // Fallthrough
2510  case CK_PentiumPro:
2511    Builder.defineMacro("__tune_i686__");
2512    Builder.defineMacro("__tune_pentiumpro__");
2513    // Fallthrough
2514  case CK_i686:
2515    Builder.defineMacro("__i686");
2516    Builder.defineMacro("__i686__");
2517    // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2518    Builder.defineMacro("__pentiumpro");
2519    Builder.defineMacro("__pentiumpro__");
2520    break;
2521  case CK_Pentium4:
2522  case CK_Pentium4M:
2523    defineCPUMacros(Builder, "pentium4");
2524    break;
2525  case CK_Yonah:
2526  case CK_Prescott:
2527  case CK_Nocona:
2528    defineCPUMacros(Builder, "nocona");
2529    break;
2530  case CK_Core2:
2531  case CK_Penryn:
2532    defineCPUMacros(Builder, "core2");
2533    break;
2534  case CK_Atom:
2535    defineCPUMacros(Builder, "atom");
2536    break;
2537  case CK_Silvermont:
2538    defineCPUMacros(Builder, "slm");
2539    break;
2540  case CK_Corei7:
2541  case CK_Corei7AVX:
2542  case CK_CoreAVXi:
2543  case CK_CoreAVX2:
2544    defineCPUMacros(Builder, "corei7");
2545    break;
2546  case CK_KNL:
2547    defineCPUMacros(Builder, "knl");
2548    break;
2549  case CK_K6_2:
2550    Builder.defineMacro("__k6_2__");
2551    Builder.defineMacro("__tune_k6_2__");
2552    // Fallthrough
2553  case CK_K6_3:
2554    if (CPU != CK_K6_2) {  // In case of fallthrough
2555      // FIXME: GCC may be enabling these in cases where some other k6
2556      // architecture is specified but -m3dnow is explicitly provided. The
2557      // exact semantics need to be determined and emulated here.
2558      Builder.defineMacro("__k6_3__");
2559      Builder.defineMacro("__tune_k6_3__");
2560    }
2561    // Fallthrough
2562  case CK_K6:
2563    defineCPUMacros(Builder, "k6");
2564    break;
2565  case CK_Athlon:
2566  case CK_AthlonThunderbird:
2567  case CK_Athlon4:
2568  case CK_AthlonXP:
2569  case CK_AthlonMP:
2570    defineCPUMacros(Builder, "athlon");
2571    if (SSELevel != NoSSE) {
2572      Builder.defineMacro("__athlon_sse__");
2573      Builder.defineMacro("__tune_athlon_sse__");
2574    }
2575    break;
2576  case CK_K8:
2577  case CK_K8SSE3:
2578  case CK_x86_64:
2579  case CK_Opteron:
2580  case CK_OpteronSSE3:
2581  case CK_Athlon64:
2582  case CK_Athlon64SSE3:
2583  case CK_AthlonFX:
2584    defineCPUMacros(Builder, "k8");
2585    break;
2586  case CK_AMDFAM10:
2587    defineCPUMacros(Builder, "amdfam10");
2588    break;
2589  case CK_BTVER1:
2590    defineCPUMacros(Builder, "btver1");
2591    break;
2592  case CK_BTVER2:
2593    defineCPUMacros(Builder, "btver2");
2594    break;
2595  case CK_BDVER1:
2596    defineCPUMacros(Builder, "bdver1");
2597    break;
2598  case CK_BDVER2:
2599    defineCPUMacros(Builder, "bdver2");
2600    break;
2601  case CK_Geode:
2602    defineCPUMacros(Builder, "geode");
2603    break;
2604  }
2605
2606  // Target properties.
2607  Builder.defineMacro("__LITTLE_ENDIAN__");
2608  Builder.defineMacro("__REGISTER_PREFIX__", "");
2609
2610  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2611  // functions in glibc header files that use FP Stack inline asm which the
2612  // backend can't deal with (PR879).
2613  Builder.defineMacro("__NO_MATH_INLINES");
2614
2615  if (HasAES)
2616    Builder.defineMacro("__AES__");
2617
2618  if (HasPCLMUL)
2619    Builder.defineMacro("__PCLMUL__");
2620
2621  if (HasLZCNT)
2622    Builder.defineMacro("__LZCNT__");
2623
2624  if (HasRDRND)
2625    Builder.defineMacro("__RDRND__");
2626
2627  if (HasBMI)
2628    Builder.defineMacro("__BMI__");
2629
2630  if (HasBMI2)
2631    Builder.defineMacro("__BMI2__");
2632
2633  if (HasPOPCNT)
2634    Builder.defineMacro("__POPCNT__");
2635
2636  if (HasRTM)
2637    Builder.defineMacro("__RTM__");
2638
2639  if (HasPRFCHW)
2640    Builder.defineMacro("__PRFCHW__");
2641
2642  if (HasRDSEED)
2643    Builder.defineMacro("__RDSEED__");
2644
2645  switch (XOPLevel) {
2646  case XOP:
2647    Builder.defineMacro("__XOP__");
2648  case FMA4:
2649    Builder.defineMacro("__FMA4__");
2650  case SSE4A:
2651    Builder.defineMacro("__SSE4A__");
2652  case NoXOP:
2653    break;
2654  }
2655
2656  if (HasFMA)
2657    Builder.defineMacro("__FMA__");
2658
2659  if (HasF16C)
2660    Builder.defineMacro("__F16C__");
2661
2662  if (HasAVX512CD)
2663    Builder.defineMacro("__AVX512CD__");
2664  if (HasAVX512ER)
2665    Builder.defineMacro("__AVX512ER__");
2666  if (HasAVX512PF)
2667    Builder.defineMacro("__AVX512PF__");
2668
2669  if (HasSHA)
2670    Builder.defineMacro("__SHA__");
2671
2672  // Each case falls through to the previous one here.
2673  switch (SSELevel) {
2674  case AVX512F:
2675    Builder.defineMacro("__AVX512F__");
2676  case AVX2:
2677    Builder.defineMacro("__AVX2__");
2678  case AVX:
2679    Builder.defineMacro("__AVX__");
2680  case SSE42:
2681    Builder.defineMacro("__SSE4_2__");
2682  case SSE41:
2683    Builder.defineMacro("__SSE4_1__");
2684  case SSSE3:
2685    Builder.defineMacro("__SSSE3__");
2686  case SSE3:
2687    Builder.defineMacro("__SSE3__");
2688  case SSE2:
2689    Builder.defineMacro("__SSE2__");
2690    Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2691  case SSE1:
2692    Builder.defineMacro("__SSE__");
2693    Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2694  case NoSSE:
2695    break;
2696  }
2697
2698  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2699    switch (SSELevel) {
2700    case AVX512F:
2701    case AVX2:
2702    case AVX:
2703    case SSE42:
2704    case SSE41:
2705    case SSSE3:
2706    case SSE3:
2707    case SSE2:
2708      Builder.defineMacro("_M_IX86_FP", Twine(2));
2709      break;
2710    case SSE1:
2711      Builder.defineMacro("_M_IX86_FP", Twine(1));
2712      break;
2713    default:
2714      Builder.defineMacro("_M_IX86_FP", Twine(0));
2715    }
2716  }
2717
2718  // Each case falls through to the previous one here.
2719  switch (MMX3DNowLevel) {
2720  case AMD3DNowAthlon:
2721    Builder.defineMacro("__3dNOW_A__");
2722  case AMD3DNow:
2723    Builder.defineMacro("__3dNOW__");
2724  case MMX:
2725    Builder.defineMacro("__MMX__");
2726  case NoMMX3DNow:
2727    break;
2728  }
2729
2730  if (CPU >= CK_i486) {
2731    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2732    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2733    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2734  }
2735  if (CPU >= CK_i586)
2736    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2737}
2738
2739bool X86TargetInfo::hasFeature(StringRef Feature) const {
2740  return llvm::StringSwitch<bool>(Feature)
2741      .Case("aes", HasAES)
2742      .Case("avx", SSELevel >= AVX)
2743      .Case("avx2", SSELevel >= AVX2)
2744      .Case("avx512f", SSELevel >= AVX512F)
2745      .Case("avx512cd", HasAVX512CD)
2746      .Case("avx512er", HasAVX512ER)
2747      .Case("avx512pf", HasAVX512PF)
2748      .Case("bmi", HasBMI)
2749      .Case("bmi2", HasBMI2)
2750      .Case("fma", HasFMA)
2751      .Case("fma4", XOPLevel >= FMA4)
2752      .Case("lzcnt", HasLZCNT)
2753      .Case("rdrnd", HasRDRND)
2754      .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2755      .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2756      .Case("mmx", MMX3DNowLevel >= MMX)
2757      .Case("pclmul", HasPCLMUL)
2758      .Case("popcnt", HasPOPCNT)
2759      .Case("rtm", HasRTM)
2760      .Case("prfchw", HasPRFCHW)
2761      .Case("rdseed", HasRDSEED)
2762      .Case("sha", HasSHA)
2763      .Case("sse", SSELevel >= SSE1)
2764      .Case("sse2", SSELevel >= SSE2)
2765      .Case("sse3", SSELevel >= SSE3)
2766      .Case("ssse3", SSELevel >= SSSE3)
2767      .Case("sse4.1", SSELevel >= SSE41)
2768      .Case("sse4.2", SSELevel >= SSE42)
2769      .Case("sse4a", XOPLevel >= SSE4A)
2770      .Case("x86", true)
2771      .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2772      .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2773      .Case("xop", XOPLevel >= XOP)
2774      .Case("f16c", HasF16C)
2775      .Default(false);
2776}
2777
2778bool
2779X86TargetInfo::validateAsmConstraint(const char *&Name,
2780                                     TargetInfo::ConstraintInfo &Info) const {
2781  switch (*Name) {
2782  default: return false;
2783  case 'Y': // first letter of a pair:
2784    switch (*(Name+1)) {
2785    default: return false;
2786    case '0':  // First SSE register.
2787    case 't':  // Any SSE register, when SSE2 is enabled.
2788    case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2789    case 'm':  // any MMX register, when inter-unit moves enabled.
2790      break;   // falls through to setAllowsRegister.
2791  }
2792  case 'a': // eax.
2793  case 'b': // ebx.
2794  case 'c': // ecx.
2795  case 'd': // edx.
2796  case 'S': // esi.
2797  case 'D': // edi.
2798  case 'A': // edx:eax.
2799  case 'f': // any x87 floating point stack register.
2800  case 't': // top of floating point stack.
2801  case 'u': // second from top of floating point stack.
2802  case 'q': // Any register accessible as [r]l: a, b, c, and d.
2803  case 'y': // Any MMX register.
2804  case 'x': // Any SSE register.
2805  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2806  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2807  case 'l': // "Index" registers: any general register that can be used as an
2808            // index in a base+index memory access.
2809    Info.setAllowsRegister();
2810    return true;
2811  case 'C': // SSE floating point constant.
2812  case 'G': // x87 floating point constant.
2813  case 'e': // 32-bit signed integer constant for use with zero-extending
2814            // x86_64 instructions.
2815  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2816            // x86_64 instructions.
2817    return true;
2818  }
2819}
2820
2821
2822std::string
2823X86TargetInfo::convertConstraint(const char *&Constraint) const {
2824  switch (*Constraint) {
2825  case 'a': return std::string("{ax}");
2826  case 'b': return std::string("{bx}");
2827  case 'c': return std::string("{cx}");
2828  case 'd': return std::string("{dx}");
2829  case 'S': return std::string("{si}");
2830  case 'D': return std::string("{di}");
2831  case 'p': // address
2832    return std::string("im");
2833  case 't': // top of floating point stack.
2834    return std::string("{st}");
2835  case 'u': // second from top of floating point stack.
2836    return std::string("{st(1)}"); // second from top of floating point stack.
2837  default:
2838    return std::string(1, *Constraint);
2839  }
2840}
2841} // end anonymous namespace
2842
2843namespace {
2844// X86-32 generic target
2845class X86_32TargetInfo : public X86TargetInfo {
2846public:
2847  X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2848    DoubleAlign = LongLongAlign = 32;
2849    LongDoubleWidth = 96;
2850    LongDoubleAlign = 32;
2851    SuitableAlign = 128;
2852    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2853                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2854                        "a0:0:64-f80:32:32-n8:16:32-S128";
2855    SizeType = UnsignedInt;
2856    PtrDiffType = SignedInt;
2857    IntPtrType = SignedInt;
2858    RegParmMax = 3;
2859
2860    // Use fpret for all types.
2861    RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2862                             (1 << TargetInfo::Double) |
2863                             (1 << TargetInfo::LongDouble));
2864
2865    // x86-32 has atomics up to 8 bytes
2866    // FIXME: Check that we actually have cmpxchg8b before setting
2867    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2868    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2869  }
2870  virtual BuiltinVaListKind getBuiltinVaListKind() const {
2871    return TargetInfo::CharPtrBuiltinVaList;
2872  }
2873
2874  int getEHDataRegisterNumber(unsigned RegNo) const {
2875    if (RegNo == 0) return 0;
2876    if (RegNo == 1) return 2;
2877    return -1;
2878  }
2879  virtual bool validateInputSize(StringRef Constraint,
2880                                 unsigned Size) const {
2881    switch (Constraint[0]) {
2882    default: break;
2883    case 'a':
2884    case 'b':
2885    case 'c':
2886    case 'd':
2887      return Size <= 32;
2888    }
2889
2890    return true;
2891  }
2892};
2893} // end anonymous namespace
2894
2895namespace {
2896class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2897public:
2898  NetBSDI386TargetInfo(const llvm::Triple &Triple)
2899      : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
2900
2901  virtual unsigned getFloatEvalMethod() const {
2902    // NetBSD defaults to "double" rounding
2903    return 1;
2904  }
2905};
2906} // end anonymous namespace
2907
2908namespace {
2909class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2910public:
2911  OpenBSDI386TargetInfo(const llvm::Triple &Triple)
2912      : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
2913    SizeType = UnsignedLong;
2914    IntPtrType = SignedLong;
2915    PtrDiffType = SignedLong;
2916  }
2917};
2918} // end anonymous namespace
2919
2920namespace {
2921class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2922public:
2923  BitrigI386TargetInfo(const llvm::Triple &Triple)
2924      : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
2925    SizeType = UnsignedLong;
2926    IntPtrType = SignedLong;
2927    PtrDiffType = SignedLong;
2928  }
2929};
2930} // end anonymous namespace
2931
2932namespace {
2933class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2934public:
2935  DarwinI386TargetInfo(const llvm::Triple &Triple)
2936      : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
2937    LongDoubleWidth = 128;
2938    LongDoubleAlign = 128;
2939    SuitableAlign = 128;
2940    MaxVectorAlign = 256;
2941    SizeType = UnsignedLong;
2942    IntPtrType = SignedLong;
2943    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2944                        "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2945                        "a0:0:64-f80:128:128-n8:16:32-S128";
2946    HasAlignMac68kSupport = true;
2947  }
2948
2949};
2950} // end anonymous namespace
2951
2952namespace {
2953// x86-32 Windows target
2954class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2955public:
2956  WindowsX86_32TargetInfo(const llvm::Triple &Triple)
2957      : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
2958    TLSSupported = false;
2959    WCharType = UnsignedShort;
2960    DoubleAlign = LongLongAlign = 64;
2961    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2962                        "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2963                        "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2964  }
2965  virtual void getTargetDefines(const LangOptions &Opts,
2966                                MacroBuilder &Builder) const {
2967    WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2968  }
2969};
2970} // end anonymous namespace
2971
2972namespace {
2973
2974// x86-32 Windows Visual Studio target
2975class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2976public:
2977  VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
2978      : WindowsX86_32TargetInfo(Triple) {
2979    LongDoubleWidth = LongDoubleAlign = 64;
2980    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2981  }
2982  virtual void getTargetDefines(const LangOptions &Opts,
2983                                MacroBuilder &Builder) const {
2984    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
2985    WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
2986    // The value of the following reflects processor type.
2987    // 300=386, 400=486, 500=Pentium, 600=Blend (default)
2988    // We lost the original triple, so we use the default.
2989    Builder.defineMacro("_M_IX86", "600");
2990  }
2991};
2992} // end anonymous namespace
2993
2994namespace {
2995// x86-32 MinGW target
2996class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
2997public:
2998  MinGWX86_32TargetInfo(const llvm::Triple &Triple)
2999      : WindowsX86_32TargetInfo(Triple) {}
3000  virtual void getTargetDefines(const LangOptions &Opts,
3001                                MacroBuilder &Builder) const {
3002    WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3003    DefineStd(Builder, "WIN32", Opts);
3004    DefineStd(Builder, "WINNT", Opts);
3005    Builder.defineMacro("_X86_");
3006    Builder.defineMacro("__MSVCRT__");
3007    Builder.defineMacro("__MINGW32__");
3008
3009    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3010    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3011    if (Opts.MicrosoftExt)
3012      // Provide "as-is" __declspec.
3013      Builder.defineMacro("__declspec", "__declspec");
3014    else
3015      // Provide alias of __attribute__ like mingw32-gcc.
3016      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3017  }
3018};
3019} // end anonymous namespace
3020
3021namespace {
3022// x86-32 Cygwin target
3023class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3024public:
3025  CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3026      : X86_32TargetInfo(Triple) {
3027    TLSSupported = false;
3028    WCharType = UnsignedShort;
3029    DoubleAlign = LongLongAlign = 64;
3030    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3031                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3032                        "a0:0:64-f80:32:32-n8:16:32-S32";
3033  }
3034  virtual void getTargetDefines(const LangOptions &Opts,
3035                                MacroBuilder &Builder) const {
3036    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3037    Builder.defineMacro("_X86_");
3038    Builder.defineMacro("__CYGWIN__");
3039    Builder.defineMacro("__CYGWIN32__");
3040    DefineStd(Builder, "unix", Opts);
3041    if (Opts.CPlusPlus)
3042      Builder.defineMacro("_GNU_SOURCE");
3043  }
3044};
3045} // end anonymous namespace
3046
3047namespace {
3048// x86-32 Haiku target
3049class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3050public:
3051  HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3052    SizeType = UnsignedLong;
3053    IntPtrType = SignedLong;
3054    PtrDiffType = SignedLong;
3055    ProcessIDType = SignedLong;
3056    this->UserLabelPrefix = "";
3057    this->TLSSupported = false;
3058  }
3059  virtual void getTargetDefines(const LangOptions &Opts,
3060                                MacroBuilder &Builder) const {
3061    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3062    Builder.defineMacro("__INTEL__");
3063    Builder.defineMacro("__HAIKU__");
3064  }
3065};
3066} // end anonymous namespace
3067
3068// RTEMS Target
3069template<typename Target>
3070class RTEMSTargetInfo : public OSTargetInfo<Target> {
3071protected:
3072  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3073                            MacroBuilder &Builder) const {
3074    // RTEMS defines; list based off of gcc output
3075
3076    Builder.defineMacro("__rtems__");
3077    Builder.defineMacro("__ELF__");
3078  }
3079
3080public:
3081  RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3082    this->UserLabelPrefix = "";
3083
3084    switch (Triple.getArch()) {
3085    default:
3086    case llvm::Triple::x86:
3087      // this->MCountName = ".mcount";
3088      break;
3089    case llvm::Triple::mips:
3090    case llvm::Triple::mipsel:
3091    case llvm::Triple::ppc:
3092    case llvm::Triple::ppc64:
3093    case llvm::Triple::ppc64le:
3094      // this->MCountName = "_mcount";
3095      break;
3096    case llvm::Triple::arm:
3097      // this->MCountName = "__mcount";
3098      break;
3099    }
3100  }
3101};
3102
3103namespace {
3104// x86-32 RTEMS target
3105class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3106public:
3107  RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3108    SizeType = UnsignedLong;
3109    IntPtrType = SignedLong;
3110    PtrDiffType = SignedLong;
3111    this->UserLabelPrefix = "";
3112  }
3113  virtual void getTargetDefines(const LangOptions &Opts,
3114                                MacroBuilder &Builder) const {
3115    X86_32TargetInfo::getTargetDefines(Opts, Builder);
3116    Builder.defineMacro("__INTEL__");
3117    Builder.defineMacro("__rtems__");
3118  }
3119};
3120} // end anonymous namespace
3121
3122namespace {
3123// x86-64 generic target
3124class X86_64TargetInfo : public X86TargetInfo {
3125public:
3126  X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3127    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3128    LongDoubleWidth = 128;
3129    LongDoubleAlign = 128;
3130    LargeArrayMinWidth = 128;
3131    LargeArrayAlign = 128;
3132    SuitableAlign = 128;
3133    IntMaxType = SignedLong;
3134    UIntMaxType = UnsignedLong;
3135    Int64Type = SignedLong;
3136    RegParmMax = 6;
3137
3138    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3139                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3140                        "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3141
3142    // Use fpret only for long double.
3143    RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3144
3145    // Use fp2ret for _Complex long double.
3146    ComplexLongDoubleUsesFP2Ret = true;
3147
3148    // x86-64 has atomics up to 16 bytes.
3149    // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3150    // on CPUs with cmpxchg16b
3151    MaxAtomicPromoteWidth = 128;
3152    MaxAtomicInlineWidth = 64;
3153  }
3154  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3155    return TargetInfo::X86_64ABIBuiltinVaList;
3156  }
3157
3158  int getEHDataRegisterNumber(unsigned RegNo) const {
3159    if (RegNo == 0) return 0;
3160    if (RegNo == 1) return 1;
3161    return -1;
3162  }
3163
3164  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3165    return (CC == CC_C ||
3166            CC == CC_IntelOclBicc ||
3167            CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3168  }
3169
3170  virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3171    return CC_C;
3172  }
3173
3174};
3175} // end anonymous namespace
3176
3177namespace {
3178// x86-64 Windows target
3179class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3180public:
3181  WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3182      : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3183    TLSSupported = false;
3184    WCharType = UnsignedShort;
3185    LongWidth = LongAlign = 32;
3186    DoubleAlign = LongLongAlign = 64;
3187    IntMaxType = SignedLongLong;
3188    UIntMaxType = UnsignedLongLong;
3189    Int64Type = SignedLongLong;
3190    SizeType = UnsignedLongLong;
3191    PtrDiffType = SignedLongLong;
3192    IntPtrType = SignedLongLong;
3193    this->UserLabelPrefix = "";
3194  }
3195  virtual void getTargetDefines(const LangOptions &Opts,
3196                                MacroBuilder &Builder) const {
3197    WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3198    Builder.defineMacro("_WIN64");
3199  }
3200  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3201    return TargetInfo::CharPtrBuiltinVaList;
3202  }
3203  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3204    return (CC == CC_C ||
3205            CC == CC_IntelOclBicc ||
3206            CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3207  }
3208};
3209} // end anonymous namespace
3210
3211namespace {
3212// x86-64 Windows Visual Studio target
3213class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3214public:
3215  VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3216      : WindowsX86_64TargetInfo(Triple) {
3217    LongDoubleWidth = LongDoubleAlign = 64;
3218    LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3219  }
3220  virtual void getTargetDefines(const LangOptions &Opts,
3221                                MacroBuilder &Builder) const {
3222    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3223    WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3224    Builder.defineMacro("_M_X64");
3225    Builder.defineMacro("_M_AMD64");
3226  }
3227};
3228} // end anonymous namespace
3229
3230namespace {
3231// x86-64 MinGW target
3232class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3233public:
3234  MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3235      : WindowsX86_64TargetInfo(Triple) {}
3236  virtual void getTargetDefines(const LangOptions &Opts,
3237                                MacroBuilder &Builder) const {
3238    WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3239    DefineStd(Builder, "WIN64", Opts);
3240    Builder.defineMacro("__MSVCRT__");
3241    Builder.defineMacro("__MINGW32__");
3242    Builder.defineMacro("__MINGW64__");
3243
3244    // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3245    // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3246    if (Opts.MicrosoftExt)
3247      // Provide "as-is" __declspec.
3248      Builder.defineMacro("__declspec", "__declspec");
3249    else
3250      // Provide alias of __attribute__ like mingw32-gcc.
3251      Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3252  }
3253};
3254} // end anonymous namespace
3255
3256namespace {
3257class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3258public:
3259  DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3260      : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3261    Int64Type = SignedLongLong;
3262    MaxVectorAlign = 256;
3263  }
3264};
3265} // end anonymous namespace
3266
3267namespace {
3268class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3269public:
3270  OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3271      : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3272    IntMaxType = SignedLongLong;
3273    UIntMaxType = UnsignedLongLong;
3274    Int64Type = SignedLongLong;
3275  }
3276};
3277} // end anonymous namespace
3278
3279namespace {
3280class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3281public:
3282  BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3283      : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3284    IntMaxType = SignedLongLong;
3285    UIntMaxType = UnsignedLongLong;
3286    Int64Type = SignedLongLong;
3287  }
3288};
3289}
3290
3291namespace {
3292class AArch64TargetInfo : public TargetInfo {
3293  static const char * const GCCRegNames[];
3294  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3295
3296  enum FPUModeEnum {
3297    FPUMode,
3298    NeonMode
3299  };
3300
3301  unsigned FPU;
3302  static const Builtin::Info BuiltinInfo[];
3303
3304public:
3305  AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3306    BigEndian = false;
3307    LongWidth = LongAlign = 64;
3308    LongDoubleWidth = LongDoubleAlign = 128;
3309    PointerWidth = PointerAlign = 64;
3310    SuitableAlign = 128;
3311    DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3312                        "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3313                        "f128:128:128-n32:64-S128";
3314
3315    WCharType = UnsignedInt;
3316    LongDoubleFormat = &llvm::APFloat::IEEEquad;
3317
3318    // AArch64 backend supports 64-bit operations at the moment. In principle
3319    // 128-bit is possible if register-pairs are used.
3320    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3321
3322    TheCXXABI.set(TargetCXXABI::GenericAArch64);
3323  }
3324  virtual void getTargetDefines(const LangOptions &Opts,
3325                                MacroBuilder &Builder) const {
3326    // GCC defines theses currently
3327    Builder.defineMacro("__aarch64__");
3328    Builder.defineMacro("__AARCH64EL__");
3329
3330    // ACLE predefines. Many can only have one possible value on v8 AArch64.
3331
3332    // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3333    // which was intended to be compatible with a 64-bit implementation. They
3334    // will need updating when a real 64-bit ACLE exists. Particularly pressing
3335    // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3336    Builder.defineMacro("__ARM_ACLE",         "101");
3337    Builder.defineMacro("__ARM_ARCH",         "8");
3338    Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3339
3340    Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3341    Builder.defineMacro("__ARM_FEATURE_CLZ");
3342    Builder.defineMacro("__ARM_FEATURE_FMA");
3343
3344    // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3345    // 128-bit LDXP present, at which point this becomes 0x1f.
3346    Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3347
3348    // 0xe implies support for half, single and double precision operations.
3349    Builder.defineMacro("__ARM_FP", "0xe");
3350
3351    // PCS specifies this for SysV variants, which is all we support. Other ABIs
3352    // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3353    Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3354
3355    if (Opts.FastMath || Opts.FiniteMathOnly)
3356      Builder.defineMacro("__ARM_FP_FAST");
3357
3358    if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3359      Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3360
3361    Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3362                        Opts.ShortWChar ? "2" : "4");
3363
3364    Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3365                        Opts.ShortEnums ? "1" : "4");
3366
3367    if (BigEndian)
3368      Builder.defineMacro("__AARCH_BIG_ENDIAN");
3369
3370    if (FPU == NeonMode) {
3371      Builder.defineMacro("__AARCH_FEATURE_ADVSIMD");
3372
3373      // 64-bit NEON supports half, single and double precision operations.
3374      Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe");
3375    }
3376  }
3377  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3378                                 unsigned &NumRecords) const {
3379    Records = BuiltinInfo;
3380    NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3381  }
3382  virtual bool hasFeature(StringRef Feature) const {
3383    return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);
3384  }
3385
3386  virtual bool HandleTargetFeatures(std::vector<std::string> &Features,
3387                                    DiagnosticsEngine &Diags) {
3388    FPU = FPUMode;
3389    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3390      if (Features[i] == "+neon")
3391        FPU = NeonMode;
3392    }
3393    return true;
3394  }
3395
3396  virtual void getGCCRegNames(const char *const *&Names,
3397                              unsigned &NumNames) const;
3398  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3399                                unsigned &NumAliases) const;
3400
3401  virtual bool isCLZForZeroUndef() const { return false; }
3402
3403  virtual bool validateAsmConstraint(const char *&Name,
3404                                     TargetInfo::ConstraintInfo &Info) const {
3405    switch (*Name) {
3406    default: return false;
3407    case 'w': // An FP/SIMD vector register
3408      Info.setAllowsRegister();
3409      return true;
3410    case 'I': // Constant that can be used with an ADD instruction
3411    case 'J': // Constant that can be used with a SUB instruction
3412    case 'K': // Constant that can be used with a 32-bit logical instruction
3413    case 'L': // Constant that can be used with a 64-bit logical instruction
3414    case 'M': // Constant that can be used as a 32-bit MOV immediate
3415    case 'N': // Constant that can be used as a 64-bit MOV immediate
3416    case 'Y': // Floating point constant zero
3417    case 'Z': // Integer constant zero
3418      return true;
3419    case 'Q': // A memory reference with base register and no offset
3420      Info.setAllowsMemory();
3421      return true;
3422    case 'S': // A symbolic address
3423      Info.setAllowsRegister();
3424      return true;
3425    case 'U':
3426      // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3427      // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3428      // Usa: An absolute symbolic address
3429      // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3430      llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3431    }
3432  }
3433
3434  virtual const char *getClobbers() const {
3435    // There are no AArch64 clobbers shared by all asm statements.
3436    return "";
3437  }
3438
3439  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3440    return TargetInfo::AArch64ABIBuiltinVaList;
3441  }
3442};
3443
3444const char * const AArch64TargetInfo::GCCRegNames[] = {
3445  "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3446  "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3447  "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3448  "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3449
3450  "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3451  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3452  "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3453  "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3454
3455  "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3456  "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3457  "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3458  "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3459
3460  "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3461  "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3462  "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3463  "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3464
3465  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3466  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3467  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3468  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3469
3470  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3471  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3472  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3473  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3474
3475  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3476  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3477  "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3478  "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3479};
3480
3481void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3482                                       unsigned &NumNames) const {
3483  Names = GCCRegNames;
3484  NumNames = llvm::array_lengthof(GCCRegNames);
3485}
3486
3487const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3488  { { "x16" }, "ip0"},
3489  { { "x17" }, "ip1"},
3490  { { "x29" }, "fp" },
3491  { { "x30" }, "lr" }
3492};
3493
3494void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3495                                         unsigned &NumAliases) const {
3496  Aliases = GCCRegAliases;
3497  NumAliases = llvm::array_lengthof(GCCRegAliases);
3498
3499}
3500
3501const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3502#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3503#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3504                                              ALL_LANGUAGES },
3505#include "clang/Basic/BuiltinsAArch64.def"
3506};
3507
3508} // end anonymous namespace
3509
3510namespace {
3511class ARMTargetInfo : public TargetInfo {
3512  // Possible FPU choices.
3513  enum FPUMode {
3514    VFP2FPU = (1 << 0),
3515    VFP3FPU = (1 << 1),
3516    VFP4FPU = (1 << 2),
3517    NeonFPU = (1 << 3)
3518  };
3519
3520  static bool FPUModeIsVFP(FPUMode Mode) {
3521    return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3522  }
3523
3524  static const TargetInfo::GCCRegAlias GCCRegAliases[];
3525  static const char * const GCCRegNames[];
3526
3527  std::string ABI, CPU;
3528
3529  enum {
3530    FP_Default,
3531    FP_VFP,
3532    FP_Neon
3533  } FPMath;
3534
3535  unsigned FPU : 4;
3536
3537  unsigned IsAAPCS : 1;
3538  unsigned IsThumb : 1;
3539
3540  // Initialized via features.
3541  unsigned SoftFloat : 1;
3542  unsigned SoftFloatABI : 1;
3543
3544  static const Builtin::Info BuiltinInfo[];
3545
3546  static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3547    // On linux, binaries targeting old cpus call functions in libgcc to
3548    // perform atomic operations. The implementation in libgcc then calls into
3549    // the kernel which on armv6 and newer uses ldrex and strex. The net result
3550    // is that if we assume the kernel is at least as recent as the hardware,
3551    // it is safe to use atomic instructions on armv6 and newer.
3552    if (!T.isOSLinux() &&
3553        T.getOS() != llvm::Triple::FreeBSD &&
3554        T.getOS() != llvm::Triple::Bitrig)
3555      return false;
3556    StringRef ArchName = T.getArchName();
3557    if (T.getArch() == llvm::Triple::arm) {
3558      if (!ArchName.startswith("armv"))
3559        return false;
3560      StringRef VersionStr = ArchName.substr(4);
3561      unsigned Version;
3562      if (VersionStr.getAsInteger(10, Version))
3563        return false;
3564      return Version >= 6;
3565    }
3566    assert(T.getArch() == llvm::Triple::thumb);
3567    if (!ArchName.startswith("thumbv"))
3568      return false;
3569    StringRef VersionStr = ArchName.substr(6);
3570    unsigned Version;
3571    if (VersionStr.getAsInteger(10, Version))
3572      return false;
3573    return Version >= 7;
3574  }
3575
3576public:
3577  ARMTargetInfo(const llvm::Triple &Triple)
3578      : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3579        FPMath(FP_Default), IsAAPCS(true) {
3580    BigEndian = false;
3581    SizeType = UnsignedInt;
3582    PtrDiffType = SignedInt;
3583    // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3584    WCharType = UnsignedInt;
3585
3586    // {} in inline assembly are neon specifiers, not assembly variant
3587    // specifiers.
3588    NoAsmVariants = true;
3589
3590    // FIXME: Should we just treat this as a feature?
3591    IsThumb = getTriple().getArchName().startswith("thumb");
3592    if (IsThumb) {
3593      // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3594      // so set preferred for small types to 32.
3595      DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3596                           "i64:64:64-f32:32:32-f64:64:64-"
3597                           "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3598    } else {
3599      DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3600                           "i64:64:64-f32:32:32-f64:64:64-"
3601                           "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3602    }
3603
3604    // ARM targets default to using the ARM C++ ABI.
3605    TheCXXABI.set(TargetCXXABI::GenericARM);
3606
3607    // ARM has atomics up to 8 bytes
3608    MaxAtomicPromoteWidth = 64;
3609    if (shouldUseInlineAtomic(getTriple()))
3610      MaxAtomicInlineWidth = 64;
3611
3612    // Do force alignment of members that follow zero length bitfields.  If
3613    // the alignment of the zero-length bitfield is greater than the member
3614    // that follows it, `bar', `bar' will be aligned as the  type of the
3615    // zero length bitfield.
3616    UseZeroLengthBitfieldAlignment = true;
3617  }
3618  virtual const char *getABI() const { return ABI.c_str(); }
3619  virtual bool setABI(const std::string &Name) {
3620    ABI = Name;
3621
3622    // The defaults (above) are for AAPCS, check if we need to change them.
3623    //
3624    // FIXME: We need support for -meabi... we could just mangle it into the
3625    // name.
3626    if (Name == "apcs-gnu") {
3627      DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3628      // size_t is unsigned int on FreeBSD.
3629      if (getTriple().getOS() != llvm::Triple::FreeBSD)
3630        SizeType = UnsignedLong;
3631
3632      // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3633      WCharType = SignedInt;
3634
3635      // Do not respect the alignment of bit-field types when laying out
3636      // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3637      UseBitFieldTypeAlignment = false;
3638
3639      /// gcc forces the alignment to 4 bytes, regardless of the type of the
3640      /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3641      /// gcc.
3642      ZeroLengthBitfieldBoundary = 32;
3643
3644      IsAAPCS = false;
3645
3646      if (IsThumb) {
3647        // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3648        // so set preferred for small types to 32.
3649        DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3650                             "i64:32:64-f32:32:32-f64:32:64-"
3651                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3652      } else {
3653        DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3654                             "i64:32:64-f32:32:32-f64:32:64-"
3655                             "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3656      }
3657
3658      // FIXME: Override "preferred align" for double and long long.
3659    } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3660      // size_t is unsigned long on Darwin.
3661      if (getTriple().isOSDarwin())
3662        SizeType = UnsignedLong;
3663      IsAAPCS = true;
3664      // FIXME: Enumerated types are variable width in straight AAPCS.
3665    } else if (Name == "aapcs-linux") {
3666      IsAAPCS = true;
3667    } else
3668      return false;
3669
3670    return true;
3671  }
3672
3673  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3674    if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3675      Features["vfp2"] = true;
3676    else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3677             CPU == "cortex-a9-mp") {
3678      Features["vfp3"] = true;
3679      Features["neon"] = true;
3680    } else if (CPU == "swift" || CPU == "cortex-a5" ||
3681        CPU == "cortex-a7" || CPU == "cortex-a15") {
3682      Features["vfp4"] = true;
3683      Features["neon"] = true;
3684    }
3685  }
3686
3687  virtual bool HandleTargetFeatures(std::vector<std::string> &Features,
3688                                    DiagnosticsEngine &Diags) {
3689    FPU = 0;
3690    SoftFloat = SoftFloatABI = false;
3691    for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3692      if (Features[i] == "+soft-float")
3693        SoftFloat = true;
3694      else if (Features[i] == "+soft-float-abi")
3695        SoftFloatABI = true;
3696      else if (Features[i] == "+vfp2")
3697        FPU |= VFP2FPU;
3698      else if (Features[i] == "+vfp3")
3699        FPU |= VFP3FPU;
3700      else if (Features[i] == "+vfp4")
3701        FPU |= VFP4FPU;
3702      else if (Features[i] == "+neon")
3703        FPU |= NeonFPU;
3704    }
3705
3706    if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3707      Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3708      return false;
3709    }
3710
3711    if (FPMath == FP_Neon)
3712      Features.push_back("+neonfp");
3713    else if (FPMath == FP_VFP)
3714      Features.push_back("-neonfp");
3715
3716    // Remove front-end specific options which the backend handles differently.
3717    std::vector<std::string>::iterator it;
3718    it = std::find(Features.begin(), Features.end(), "+soft-float");
3719    if (it != Features.end())
3720      Features.erase(it);
3721    it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3722    if (it != Features.end())
3723      Features.erase(it);
3724    return true;
3725  }
3726
3727  virtual bool hasFeature(StringRef Feature) const {
3728    return llvm::StringSwitch<bool>(Feature)
3729        .Case("arm", true)
3730        .Case("softfloat", SoftFloat)
3731        .Case("thumb", IsThumb)
3732        .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3733        .Default(false);
3734  }
3735  // FIXME: Should we actually have some table instead of these switches?
3736  static const char *getCPUDefineSuffix(StringRef Name) {
3737    return llvm::StringSwitch<const char*>(Name)
3738      .Cases("arm8", "arm810", "4")
3739      .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3740      .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3741      .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3742      .Case("ep9312", "4T")
3743      .Cases("arm10tdmi", "arm1020t", "5T")
3744      .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3745      .Case("arm926ej-s", "5TEJ")
3746      .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3747      .Cases("xscale", "iwmmxt", "5TE")
3748      .Case("arm1136j-s", "6J")
3749      .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3750      .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3751      .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3752      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3753      .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A")
3754      .Cases("cortex-r4", "cortex-r5", "7R")
3755      .Case("cortex-a9-mp", "7F")
3756      .Case("swift", "7S")
3757      .Cases("cortex-m3", "cortex-m4", "7M")
3758      .Case("cortex-m0", "6M")
3759      .Case("cortex-a53", "8A")
3760      .Default(0);
3761  }
3762  static const char *getCPUProfile(StringRef Name) {
3763    return llvm::StringSwitch<const char*>(Name)
3764      .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
3765      .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A")
3766      .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3767      .Cases("cortex-r4", "cortex-r5", "R")
3768      .Default("");
3769  }
3770  virtual bool setCPU(const std::string &Name) {
3771    if (!getCPUDefineSuffix(Name))
3772      return false;
3773
3774    CPU = Name;
3775    return true;
3776  }
3777  virtual bool setFPMath(StringRef Name);
3778  virtual void getTargetDefines(const LangOptions &Opts,
3779                                MacroBuilder &Builder) const {
3780    // Target identification.
3781    Builder.defineMacro("__arm");
3782    Builder.defineMacro("__arm__");
3783
3784    // Target properties.
3785    Builder.defineMacro("__ARMEL__");
3786    Builder.defineMacro("__LITTLE_ENDIAN__");
3787    Builder.defineMacro("__REGISTER_PREFIX__", "");
3788
3789    StringRef CPUArch = getCPUDefineSuffix(CPU);
3790    Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3791    Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3792    StringRef CPUProfile = getCPUProfile(CPU);
3793    if (!CPUProfile.empty())
3794      Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3795
3796    // Subtarget options.
3797
3798    // FIXME: It's more complicated than this and we don't really support
3799    // interworking.
3800    if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3801      Builder.defineMacro("__THUMB_INTERWORK__");
3802
3803    if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3804      // M-class CPUs on Darwin follow AAPCS, but not EABI.
3805      if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3806        Builder.defineMacro("__ARM_EABI__");
3807      Builder.defineMacro("__ARM_PCS", "1");
3808
3809      if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3810        Builder.defineMacro("__ARM_PCS_VFP", "1");
3811    }
3812
3813    if (SoftFloat)
3814      Builder.defineMacro("__SOFTFP__");
3815
3816    if (CPU == "xscale")
3817      Builder.defineMacro("__XSCALE__");
3818
3819    bool IsARMv7 = CPUArch.startswith("7");
3820    if (IsThumb) {
3821      Builder.defineMacro("__THUMBEL__");
3822      Builder.defineMacro("__thumb__");
3823      if (CPUArch == "6T2" || IsARMv7)
3824        Builder.defineMacro("__thumb2__");
3825    }
3826
3827    // Note, this is always on in gcc, even though it doesn't make sense.
3828    Builder.defineMacro("__APCS_32__");
3829
3830    if (FPUModeIsVFP((FPUMode) FPU)) {
3831      Builder.defineMacro("__VFP_FP__");
3832      if (FPU & VFP2FPU)
3833        Builder.defineMacro("__ARM_VFPV2__");
3834      if (FPU & VFP3FPU)
3835        Builder.defineMacro("__ARM_VFPV3__");
3836      if (FPU & VFP4FPU)
3837        Builder.defineMacro("__ARM_VFPV4__");
3838    }
3839
3840    // This only gets set when Neon instructions are actually available, unlike
3841    // the VFP define, hence the soft float and arch check. This is subtly
3842    // different from gcc, we follow the intent which was that it should be set
3843    // when Neon instructions are actually available.
3844    if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3845      Builder.defineMacro("__ARM_NEON__");
3846
3847    if (CPUArch.startswith("8"))
3848      Builder.defineMacro("__ARM_FEATURE_CRC32");
3849  }
3850  virtual void getTargetBuiltins(const Builtin::Info *&Records,
3851                                 unsigned &NumRecords) const {
3852    Records = BuiltinInfo;
3853    NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3854  }
3855  virtual bool isCLZForZeroUndef() const { return false; }
3856  virtual BuiltinVaListKind getBuiltinVaListKind() const {
3857    return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3858  }
3859  virtual void getGCCRegNames(const char * const *&Names,
3860                              unsigned &NumNames) const;
3861  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3862                                unsigned &NumAliases) const;
3863  virtual bool validateAsmConstraint(const char *&Name,
3864                                     TargetInfo::ConstraintInfo &Info) const {
3865    switch (*Name) {
3866    default: break;
3867    case 'l': // r0-r7
3868    case 'h': // r8-r15
3869    case 'w': // VFP Floating point register single precision
3870    case 'P': // VFP Floating point register double precision
3871      Info.setAllowsRegister();
3872      return true;
3873    case 'Q': // A memory address that is a single base register.
3874      Info.setAllowsMemory();
3875      return true;
3876    case 'U': // a memory reference...
3877      switch (Name[1]) {
3878      case 'q': // ...ARMV4 ldrsb
3879      case 'v': // ...VFP load/store (reg+constant offset)
3880      case 'y': // ...iWMMXt load/store
3881      case 't': // address valid for load/store opaque types wider
3882                // than 128-bits
3883      case 'n': // valid address for Neon doubleword vector load/store
3884      case 'm': // valid address for Neon element and structure load/store
3885      case 's': // valid address for non-offset loads/stores of quad-word
3886                // values in four ARM registers
3887        Info.setAllowsMemory();
3888        Name++;
3889        return true;
3890      }
3891    }
3892    return false;
3893  }
3894  virtual std::string convertConstraint(const char *&Constraint) const {
3895    std::string R;
3896    switch (*Constraint) {
3897    case 'U':   // Two-character constraint; add "^" hint for later parsing.
3898      R = std::string("^") + std::string(Constraint, 2);
3899      Constraint++;
3900      break;
3901    case 'p': // 'p' should be translated to 'r' by default.
3902      R = std::string("r");
3903      break;
3904    default:
3905      return std::string(1, *Constraint);
3906    }
3907    return R;
3908  }
3909  virtual bool validateConstraintModifier(StringRef Constraint,
3910                                          const char Modifier,
3911                                          unsigned Size) const {
3912    bool isOutput = (Constraint[0] == '=');
3913    bool isInOut = (Constraint[0] == '+');
3914
3915    // Strip off constraint modifiers.
3916    while (Constraint[0] == '=' ||
3917           Constraint[0] == '+' ||
3918           Constraint[0] == '&')
3919      Constraint = Constraint.substr(1);
3920
3921    switch (Constraint[0]) {
3922    default: break;
3923    case 'r': {
3924      switch (Modifier) {
3925      default:
3926        return (isInOut || isOutput || Size <= 32);
3927      case 'q':
3928        // A register of size 32 cannot fit a vector type.
3929        return false;
3930      }
3931    }
3932    }
3933
3934    return true;
3935  }
3936  virtual const char *getClobbers() const {
3937    // FIXME: Is this really right?
3938    return "";
3939  }
3940
3941  virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3942    return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3943  }
3944
3945  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3946    if (RegNo == 0) return 0;
3947    if (RegNo == 1) return 1;
3948    return -1;
3949  }
3950};
3951
3952bool ARMTargetInfo::setFPMath(StringRef Name) {
3953  if (Name == "neon") {
3954    FPMath = FP_Neon;
3955    return true;
3956  } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
3957             Name == "vfp4") {
3958    FPMath = FP_VFP;
3959    return true;
3960  }
3961  return false;
3962}
3963
3964const char * const ARMTargetInfo::GCCRegNames[] = {
3965  // Integer registers
3966  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3967  "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3968
3969  // Float registers
3970  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3971  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3972  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3973  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3974
3975  // Double registers
3976  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3977  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3978  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3979  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3980
3981  // Quad registers
3982  "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3983  "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3984};
3985
3986void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3987                                   unsigned &NumNames) const {
3988  Names = GCCRegNames;
3989  NumNames = llvm::array_lengthof(GCCRegNames);
3990}
3991
3992const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3993  { { "a1" }, "r0" },
3994  { { "a2" }, "r1" },
3995  { { "a3" }, "r2" },
3996  { { "a4" }, "r3" },
3997  { { "v1" }, "r4" },
3998  { { "v2" }, "r5" },
3999  { { "v3" }, "r6" },
4000  { { "v4" }, "r7" },
4001  { { "v5" }, "r8" },
4002  { { "v6", "rfp" }, "r9" },
4003  { { "sl" }, "r10" },
4004  { { "fp" }, "r11" },
4005  { { "ip" }, "r12" },
4006  { { "r13" }, "sp" },
4007  { { "r14" }, "lr" },
4008  { { "r15" }, "pc" },
4009  // The S, D and Q registers overlap, but aren't really aliases; we
4010  // don't want to substitute one of these for a different-sized one.
4011};
4012
4013void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4014                                       unsigned &NumAliases) const {
4015  Aliases = GCCRegAliases;
4016  NumAliases = llvm::array_lengthof(GCCRegAliases);
4017}
4018
4019const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4020#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4021#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4022                                              ALL_LANGUAGES },
4023#include "clang/Basic/BuiltinsARM.def"
4024};
4025} // end anonymous namespace.
4026
4027namespace {
4028class DarwinARMTargetInfo :
4029  public DarwinTargetInfo<ARMTargetInfo> {
4030protected:
4031  virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4032                            MacroBuilder &Builder) const {
4033    getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4034  }
4035
4036public:
4037  DarwinARMTargetInfo(const llvm::Triple &Triple)
4038      : DarwinTargetInfo<ARMTargetInfo>(Triple) {
4039    HasAlignMac68kSupport = true;
4040    // iOS always has 64-bit atomic instructions.
4041    // FIXME: This should be based off of the target features in ARMTargetInfo.
4042    MaxAtomicInlineWidth = 64;
4043
4044    // Darwin on iOS uses a variant of the ARM C++ ABI.
4045    TheCXXABI.set(TargetCXXABI::iOS);
4046  }
4047};
4048} // end anonymous namespace.
4049
4050
4051namespace {
4052// Hexagon abstract base class
4053class HexagonTargetInfo : public TargetInfo {
4054  static const Builtin::Info BuiltinInfo[];
4055  static const char * const GCCRegNames[];
4056  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4057  std::string CPU;
4058public:
4059  HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4060    BigEndian = false;
4061    DescriptionString = ("e-p:32:32:32-"
4062                         "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4063                         "f64:64:64-f32:32:32-a0:0-n32");
4064
4065    // {} in inline assembly are packet specifiers, not assembly variant
4066    // specifiers.
4067    NoAsmVariants = true;
4068  }
4069
4070  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4071                                 unsigned &NumRecords) const {
4072    Records = BuiltinInfo;
4073    NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4074  }
4075
4076  virtual bool validateAsmConstraint(const char *&Name,
4077                                     TargetInfo::ConstraintInfo &Info) const {
4078    return true;
4079  }
4080
4081  virtual void getTargetDefines(const LangOptions &Opts,
4082                                MacroBuilder &Builder) const;
4083
4084  virtual bool hasFeature(StringRef Feature) const {
4085    return Feature == "hexagon";
4086  }
4087
4088  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4089    return TargetInfo::CharPtrBuiltinVaList;
4090  }
4091  virtual void getGCCRegNames(const char * const *&Names,
4092                              unsigned &NumNames) const;
4093  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4094                                unsigned &NumAliases) const;
4095  virtual const char *getClobbers() const {
4096    return "";
4097  }
4098
4099  static const char *getHexagonCPUSuffix(StringRef Name) {
4100    return llvm::StringSwitch<const char*>(Name)
4101      .Case("hexagonv4", "4")
4102      .Case("hexagonv5", "5")
4103      .Default(0);
4104  }
4105
4106  virtual bool setCPU(const std::string &Name) {
4107    if (!getHexagonCPUSuffix(Name))
4108      return false;
4109
4110    CPU = Name;
4111    return true;
4112  }
4113};
4114
4115void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4116                                MacroBuilder &Builder) const {
4117  Builder.defineMacro("qdsp6");
4118  Builder.defineMacro("__qdsp6", "1");
4119  Builder.defineMacro("__qdsp6__", "1");
4120
4121  Builder.defineMacro("hexagon");
4122  Builder.defineMacro("__hexagon", "1");
4123  Builder.defineMacro("__hexagon__", "1");
4124
4125  if(CPU == "hexagonv1") {
4126    Builder.defineMacro("__HEXAGON_V1__");
4127    Builder.defineMacro("__HEXAGON_ARCH__", "1");
4128    if(Opts.HexagonQdsp6Compat) {
4129      Builder.defineMacro("__QDSP6_V1__");
4130      Builder.defineMacro("__QDSP6_ARCH__", "1");
4131    }
4132  }
4133  else if(CPU == "hexagonv2") {
4134    Builder.defineMacro("__HEXAGON_V2__");
4135    Builder.defineMacro("__HEXAGON_ARCH__", "2");
4136    if(Opts.HexagonQdsp6Compat) {
4137      Builder.defineMacro("__QDSP6_V2__");
4138      Builder.defineMacro("__QDSP6_ARCH__", "2");
4139    }
4140  }
4141  else if(CPU == "hexagonv3") {
4142    Builder.defineMacro("__HEXAGON_V3__");
4143    Builder.defineMacro("__HEXAGON_ARCH__", "3");
4144    if(Opts.HexagonQdsp6Compat) {
4145      Builder.defineMacro("__QDSP6_V3__");
4146      Builder.defineMacro("__QDSP6_ARCH__", "3");
4147    }
4148  }
4149  else if(CPU == "hexagonv4") {
4150    Builder.defineMacro("__HEXAGON_V4__");
4151    Builder.defineMacro("__HEXAGON_ARCH__", "4");
4152    if(Opts.HexagonQdsp6Compat) {
4153      Builder.defineMacro("__QDSP6_V4__");
4154      Builder.defineMacro("__QDSP6_ARCH__", "4");
4155    }
4156  }
4157  else if(CPU == "hexagonv5") {
4158    Builder.defineMacro("__HEXAGON_V5__");
4159    Builder.defineMacro("__HEXAGON_ARCH__", "5");
4160    if(Opts.HexagonQdsp6Compat) {
4161      Builder.defineMacro("__QDSP6_V5__");
4162      Builder.defineMacro("__QDSP6_ARCH__", "5");
4163    }
4164  }
4165}
4166
4167const char * const HexagonTargetInfo::GCCRegNames[] = {
4168  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4169  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4170  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4171  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4172  "p0", "p1", "p2", "p3",
4173  "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4174};
4175
4176void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4177                                   unsigned &NumNames) const {
4178  Names = GCCRegNames;
4179  NumNames = llvm::array_lengthof(GCCRegNames);
4180}
4181
4182
4183const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4184  { { "sp" }, "r29" },
4185  { { "fp" }, "r30" },
4186  { { "lr" }, "r31" },
4187 };
4188
4189void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4190                                     unsigned &NumAliases) const {
4191  Aliases = GCCRegAliases;
4192  NumAliases = llvm::array_lengthof(GCCRegAliases);
4193}
4194
4195
4196const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4197#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4198#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4199                                              ALL_LANGUAGES },
4200#include "clang/Basic/BuiltinsHexagon.def"
4201};
4202}
4203
4204
4205namespace {
4206// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4207class SparcTargetInfo : public TargetInfo {
4208  static const TargetInfo::GCCRegAlias GCCRegAliases[];
4209  static const char * const GCCRegNames[];
4210  bool SoftFloat;
4211public:
4212  SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4213
4214  virtual bool HandleTargetFeatures(std::vector<std::string> &Features,
4215                                    DiagnosticsEngine &Diags) {
4216    SoftFloat = false;
4217    for (unsigned i = 0, e = Features.size(); i != e; ++i)
4218      if (Features[i] == "+soft-float")
4219        SoftFloat = true;
4220    return true;
4221  }
4222  virtual void getTargetDefines(const LangOptions &Opts,
4223                                MacroBuilder &Builder) const {
4224    DefineStd(Builder, "sparc", Opts);
4225    Builder.defineMacro("__REGISTER_PREFIX__", "");
4226
4227    if (SoftFloat)
4228      Builder.defineMacro("SOFT_FLOAT", "1");
4229  }
4230
4231  virtual bool hasFeature(StringRef Feature) const {
4232    return llvm::StringSwitch<bool>(Feature)
4233             .Case("softfloat", SoftFloat)
4234             .Case("sparc", true)
4235             .Default(false);
4236  }
4237
4238  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4239                                 unsigned &NumRecords) const {
4240    // FIXME: Implement!
4241  }
4242  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4243    return TargetInfo::VoidPtrBuiltinVaList;
4244  }
4245  virtual void getGCCRegNames(const char * const *&Names,
4246                              unsigned &NumNames) const;
4247  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4248                                unsigned &NumAliases) const;
4249  virtual bool validateAsmConstraint(const char *&Name,
4250                                     TargetInfo::ConstraintInfo &info) const {
4251    // FIXME: Implement!
4252    return false;
4253  }
4254  virtual const char *getClobbers() const {
4255    // FIXME: Implement!
4256    return "";
4257  }
4258};
4259
4260const char * const SparcTargetInfo::GCCRegNames[] = {
4261  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4262  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4263  "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4264  "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4265};
4266
4267void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4268                                     unsigned &NumNames) const {
4269  Names = GCCRegNames;
4270  NumNames = llvm::array_lengthof(GCCRegNames);
4271}
4272
4273const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4274  { { "g0" }, "r0" },
4275  { { "g1" }, "r1" },
4276  { { "g2" }, "r2" },
4277  { { "g3" }, "r3" },
4278  { { "g4" }, "r4" },
4279  { { "g5" }, "r5" },
4280  { { "g6" }, "r6" },
4281  { { "g7" }, "r7" },
4282  { { "o0" }, "r8" },
4283  { { "o1" }, "r9" },
4284  { { "o2" }, "r10" },
4285  { { "o3" }, "r11" },
4286  { { "o4" }, "r12" },
4287  { { "o5" }, "r13" },
4288  { { "o6", "sp" }, "r14" },
4289  { { "o7" }, "r15" },
4290  { { "l0" }, "r16" },
4291  { { "l1" }, "r17" },
4292  { { "l2" }, "r18" },
4293  { { "l3" }, "r19" },
4294  { { "l4" }, "r20" },
4295  { { "l5" }, "r21" },
4296  { { "l6" }, "r22" },
4297  { { "l7" }, "r23" },
4298  { { "i0" }, "r24" },
4299  { { "i1" }, "r25" },
4300  { { "i2" }, "r26" },
4301  { { "i3" }, "r27" },
4302  { { "i4" }, "r28" },
4303  { { "i5" }, "r29" },
4304  { { "i6", "fp" }, "r30" },
4305  { { "i7" }, "r31" },
4306};
4307
4308void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4309                                       unsigned &NumAliases) const {
4310  Aliases = GCCRegAliases;
4311  NumAliases = llvm::array_lengthof(GCCRegAliases);
4312}
4313
4314// SPARC v8 is the 32-bit mode selected by Triple::sparc.
4315class SparcV8TargetInfo : public SparcTargetInfo {
4316public:
4317  SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4318    // FIXME: Support Sparc quad-precision long double?
4319    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4320                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4321  }
4322
4323  virtual void getTargetDefines(const LangOptions &Opts,
4324                                MacroBuilder &Builder) const {
4325    SparcTargetInfo::getTargetDefines(Opts, Builder);
4326    Builder.defineMacro("__sparcv8");
4327  }
4328};
4329
4330// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4331class SparcV9TargetInfo : public SparcTargetInfo {
4332public:
4333  SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4334    // FIXME: Support Sparc quad-precision long double?
4335    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4336                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4337    // This is an LP64 platform.
4338    LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4339
4340    // OpenBSD uses long long for int64_t and intmax_t.
4341    if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4342      IntMaxType = SignedLongLong;
4343      UIntMaxType = UnsignedLongLong;
4344    } else {
4345      IntMaxType = SignedLong;
4346      UIntMaxType = UnsignedLong;
4347    }
4348    Int64Type = IntMaxType;
4349  }
4350
4351  virtual void getTargetDefines(const LangOptions &Opts,
4352                                MacroBuilder &Builder) const {
4353    SparcTargetInfo::getTargetDefines(Opts, Builder);
4354    Builder.defineMacro("__sparcv9");
4355    Builder.defineMacro("__arch64__");
4356    // Solaris and its derivative AuroraUX don't need these variants, but the
4357    // BSDs do.
4358    if (getTriple().getOS() != llvm::Triple::Solaris &&
4359        getTriple().getOS() != llvm::Triple::AuroraUX) {
4360      Builder.defineMacro("__sparc64__");
4361      Builder.defineMacro("__sparc_v9__");
4362      Builder.defineMacro("__sparcv9__");
4363    }
4364  }
4365};
4366
4367} // end anonymous namespace.
4368
4369namespace {
4370class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4371public:
4372  AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4373      : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4374    SizeType = UnsignedInt;
4375    PtrDiffType = SignedInt;
4376  }
4377};
4378class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4379public:
4380  SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4381      : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4382    SizeType = UnsignedInt;
4383    PtrDiffType = SignedInt;
4384  }
4385};
4386} // end anonymous namespace.
4387
4388namespace {
4389  class SystemZTargetInfo : public TargetInfo {
4390    static const char *const GCCRegNames[];
4391
4392  public:
4393    SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4394      TLSSupported = true;
4395      IntWidth = IntAlign = 32;
4396      LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4397      PointerWidth = PointerAlign = 64;
4398      LongDoubleWidth = 128;
4399      LongDoubleAlign = 64;
4400      LongDoubleFormat = &llvm::APFloat::IEEEquad;
4401      MinGlobalAlign = 16;
4402      DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4403       "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4404      MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4405    }
4406    virtual void getTargetDefines(const LangOptions &Opts,
4407                                  MacroBuilder &Builder) const {
4408      Builder.defineMacro("__s390__");
4409      Builder.defineMacro("__s390x__");
4410      Builder.defineMacro("__zarch__");
4411      Builder.defineMacro("__LONG_DOUBLE_128__");
4412    }
4413    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4414                                   unsigned &NumRecords) const {
4415      // FIXME: Implement.
4416      Records = 0;
4417      NumRecords = 0;
4418    }
4419
4420    virtual void getGCCRegNames(const char *const *&Names,
4421                                unsigned &NumNames) const;
4422    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4423                                  unsigned &NumAliases) const {
4424      // No aliases.
4425      Aliases = 0;
4426      NumAliases = 0;
4427    }
4428    virtual bool validateAsmConstraint(const char *&Name,
4429                                       TargetInfo::ConstraintInfo &info) const;
4430    virtual const char *getClobbers() const {
4431      // FIXME: Is this really right?
4432      return "";
4433    }
4434    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4435      return TargetInfo::SystemZBuiltinVaList;
4436    }
4437    virtual bool setCPU(const std::string &Name) {
4438      bool CPUKnown = llvm::StringSwitch<bool>(Name)
4439        .Case("z10", true)
4440        .Case("z196", true)
4441        .Case("zEC12", true)
4442        .Default(false);
4443
4444      // No need to store the CPU yet.  There aren't any CPU-specific
4445      // macros to define.
4446      return CPUKnown;
4447    }
4448  };
4449
4450  const char *const SystemZTargetInfo::GCCRegNames[] = {
4451    "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4452    "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4453    "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4454    "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4455  };
4456
4457  void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4458                                         unsigned &NumNames) const {
4459    Names = GCCRegNames;
4460    NumNames = llvm::array_lengthof(GCCRegNames);
4461  }
4462
4463  bool SystemZTargetInfo::
4464  validateAsmConstraint(const char *&Name,
4465                        TargetInfo::ConstraintInfo &Info) const {
4466    switch (*Name) {
4467    default:
4468      return false;
4469
4470    case 'a': // Address register
4471    case 'd': // Data register (equivalent to 'r')
4472    case 'f': // Floating-point register
4473      Info.setAllowsRegister();
4474      return true;
4475
4476    case 'I': // Unsigned 8-bit constant
4477    case 'J': // Unsigned 12-bit constant
4478    case 'K': // Signed 16-bit constant
4479    case 'L': // Signed 20-bit displacement (on all targets we support)
4480    case 'M': // 0x7fffffff
4481      return true;
4482
4483    case 'Q': // Memory with base and unsigned 12-bit displacement
4484    case 'R': // Likewise, plus an index
4485    case 'S': // Memory with base and signed 20-bit displacement
4486    case 'T': // Likewise, plus an index
4487      Info.setAllowsMemory();
4488      return true;
4489    }
4490  }
4491}
4492
4493namespace {
4494  class MSP430TargetInfo : public TargetInfo {
4495    static const char * const GCCRegNames[];
4496  public:
4497    MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4498      BigEndian = false;
4499      TLSSupported = false;
4500      IntWidth = 16; IntAlign = 16;
4501      LongWidth = 32; LongLongWidth = 64;
4502      LongAlign = LongLongAlign = 16;
4503      PointerWidth = 16; PointerAlign = 16;
4504      SuitableAlign = 16;
4505      SizeType = UnsignedInt;
4506      IntMaxType = SignedLongLong;
4507      UIntMaxType = UnsignedLongLong;
4508      IntPtrType = SignedInt;
4509      PtrDiffType = SignedInt;
4510      SigAtomicType = SignedLong;
4511      DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4512   }
4513    virtual void getTargetDefines(const LangOptions &Opts,
4514                                  MacroBuilder &Builder) const {
4515      Builder.defineMacro("MSP430");
4516      Builder.defineMacro("__MSP430__");
4517      // FIXME: defines for different 'flavours' of MCU
4518    }
4519    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4520                                   unsigned &NumRecords) const {
4521     // FIXME: Implement.
4522      Records = 0;
4523      NumRecords = 0;
4524    }
4525    virtual bool hasFeature(StringRef Feature) const {
4526      return Feature == "msp430";
4527    }
4528    virtual void getGCCRegNames(const char * const *&Names,
4529                                unsigned &NumNames) const;
4530    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4531                                  unsigned &NumAliases) const {
4532      // No aliases.
4533      Aliases = 0;
4534      NumAliases = 0;
4535    }
4536    virtual bool validateAsmConstraint(const char *&Name,
4537                                       TargetInfo::ConstraintInfo &info) const {
4538      // No target constraints for now.
4539      return false;
4540    }
4541    virtual const char *getClobbers() const {
4542      // FIXME: Is this really right?
4543      return "";
4544    }
4545    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4546      // FIXME: implement
4547      return TargetInfo::CharPtrBuiltinVaList;
4548   }
4549  };
4550
4551  const char * const MSP430TargetInfo::GCCRegNames[] = {
4552    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4553    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4554  };
4555
4556  void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4557                                        unsigned &NumNames) const {
4558    Names = GCCRegNames;
4559    NumNames = llvm::array_lengthof(GCCRegNames);
4560  }
4561}
4562
4563namespace {
4564
4565  // LLVM and Clang cannot be used directly to output native binaries for
4566  // target, but is used to compile C code to llvm bitcode with correct
4567  // type and alignment information.
4568  //
4569  // TCE uses the llvm bitcode as input and uses it for generating customized
4570  // target processor and program binary. TCE co-design environment is
4571  // publicly available in http://tce.cs.tut.fi
4572
4573  static const unsigned TCEOpenCLAddrSpaceMap[] = {
4574      3, // opencl_global
4575      4, // opencl_local
4576      5, // opencl_constant
4577      0, // cuda_device
4578      0, // cuda_constant
4579      0  // cuda_shared
4580  };
4581
4582  class TCETargetInfo : public TargetInfo{
4583  public:
4584    TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4585      TLSSupported = false;
4586      IntWidth = 32;
4587      LongWidth = LongLongWidth = 32;
4588      PointerWidth = 32;
4589      IntAlign = 32;
4590      LongAlign = LongLongAlign = 32;
4591      PointerAlign = 32;
4592      SuitableAlign = 32;
4593      SizeType = UnsignedInt;
4594      IntMaxType = SignedLong;
4595      UIntMaxType = UnsignedLong;
4596      IntPtrType = SignedInt;
4597      PtrDiffType = SignedInt;
4598      FloatWidth = 32;
4599      FloatAlign = 32;
4600      DoubleWidth = 32;
4601      DoubleAlign = 32;
4602      LongDoubleWidth = 32;
4603      LongDoubleAlign = 32;
4604      FloatFormat = &llvm::APFloat::IEEEsingle;
4605      DoubleFormat = &llvm::APFloat::IEEEsingle;
4606      LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4607      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4608                          "i16:16:32-i32:32:32-i64:32:32-"
4609                          "f32:32:32-f64:32:32-v64:32:32-"
4610                          "v128:32:32-a0:0:32-n32";
4611      AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4612      UseAddrSpaceMapMangling = true;
4613    }
4614
4615    virtual void getTargetDefines(const LangOptions &Opts,
4616                                  MacroBuilder &Builder) const {
4617      DefineStd(Builder, "tce", Opts);
4618      Builder.defineMacro("__TCE__");
4619      Builder.defineMacro("__TCE_V1__");
4620    }
4621    virtual bool hasFeature(StringRef Feature) const {
4622      return Feature == "tce";
4623    }
4624
4625    virtual void getTargetBuiltins(const Builtin::Info *&Records,
4626                                   unsigned &NumRecords) const {}
4627    virtual const char *getClobbers() const {
4628      return "";
4629    }
4630    virtual BuiltinVaListKind getBuiltinVaListKind() const {
4631      return TargetInfo::VoidPtrBuiltinVaList;
4632    }
4633    virtual void getGCCRegNames(const char * const *&Names,
4634                                unsigned &NumNames) const {}
4635    virtual bool validateAsmConstraint(const char *&Name,
4636                                       TargetInfo::ConstraintInfo &info) const {
4637      return true;
4638    }
4639    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4640                                  unsigned &NumAliases) const {}
4641  };
4642}
4643
4644namespace {
4645class MipsTargetInfoBase : public TargetInfo {
4646  static const Builtin::Info BuiltinInfo[];
4647  std::string CPU;
4648  bool IsMips16;
4649  bool IsMicromips;
4650  bool IsNan2008;
4651  bool IsSingleFloat;
4652  enum MipsFloatABI {
4653    HardFloat, SoftFloat
4654  } FloatABI;
4655  enum DspRevEnum {
4656    NoDSP, DSP1, DSP2
4657  } DspRev;
4658  bool HasMSA;
4659
4660protected:
4661  std::string ABI;
4662
4663public:
4664  MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4665                     const std::string &CPUStr)
4666      : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4667        IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
4668        DspRev(NoDSP), HasMSA(false), ABI(ABIStr) {}
4669
4670  virtual const char *getABI() const { return ABI.c_str(); }
4671  virtual bool setABI(const std::string &Name) = 0;
4672  virtual bool setCPU(const std::string &Name) {
4673    CPU = Name;
4674    return true;
4675  }
4676  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4677    Features[ABI] = true;
4678    Features[CPU] = true;
4679  }
4680
4681  virtual void getTargetDefines(const LangOptions &Opts,
4682                                MacroBuilder &Builder) const {
4683    DefineStd(Builder, "mips", Opts);
4684    Builder.defineMacro("_mips");
4685    Builder.defineMacro("__REGISTER_PREFIX__", "");
4686
4687    switch (FloatABI) {
4688    case HardFloat:
4689      Builder.defineMacro("__mips_hard_float", Twine(1));
4690      break;
4691    case SoftFloat:
4692      Builder.defineMacro("__mips_soft_float", Twine(1));
4693      break;
4694    }
4695
4696    if (IsSingleFloat)
4697      Builder.defineMacro("__mips_single_float", Twine(1));
4698
4699    if (IsMips16)
4700      Builder.defineMacro("__mips16", Twine(1));
4701
4702    if (IsMicromips)
4703      Builder.defineMacro("__mips_micromips", Twine(1));
4704
4705    if (IsNan2008)
4706      Builder.defineMacro("__mips_nan2008", Twine(1));
4707
4708    switch (DspRev) {
4709    default:
4710      break;
4711    case DSP1:
4712      Builder.defineMacro("__mips_dsp_rev", Twine(1));
4713      Builder.defineMacro("__mips_dsp", Twine(1));
4714      break;
4715    case DSP2:
4716      Builder.defineMacro("__mips_dsp_rev", Twine(2));
4717      Builder.defineMacro("__mips_dspr2", Twine(1));
4718      Builder.defineMacro("__mips_dsp", Twine(1));
4719      break;
4720    }
4721
4722    if (HasMSA)
4723      Builder.defineMacro("__mips_msa", Twine(1));
4724
4725    Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4726    Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4727    Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4728
4729    Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4730    Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4731  }
4732
4733  virtual void getTargetBuiltins(const Builtin::Info *&Records,
4734                                 unsigned &NumRecords) const {
4735    Records = BuiltinInfo;
4736    NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4737  }
4738  virtual bool hasFeature(StringRef Feature) const {
4739    return Feature == "mips";
4740  }
4741  virtual BuiltinVaListKind getBuiltinVaListKind() const {
4742    return TargetInfo::VoidPtrBuiltinVaList;
4743  }
4744  virtual void getGCCRegNames(const char * const *&Names,
4745                              unsigned &NumNames) const {
4746    static const char * const GCCRegNames[] = {
4747      // CPU register names
4748      // Must match second column of GCCRegAliases
4749      "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4750      "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4751      "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4752      "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4753      // Floating point register names
4754      "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4755      "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4756      "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4757      "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4758      // Hi/lo and condition register names
4759      "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4760      "$fcc5","$fcc6","$fcc7"
4761    };
4762    Names = GCCRegNames;
4763    NumNames = llvm::array_lengthof(GCCRegNames);
4764  }
4765  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4766                                unsigned &NumAliases) const = 0;
4767  virtual bool validateAsmConstraint(const char *&Name,
4768                                     TargetInfo::ConstraintInfo &Info) const {
4769    switch (*Name) {
4770    default:
4771      return false;
4772
4773    case 'r': // CPU registers.
4774    case 'd': // Equivalent to "r" unless generating MIPS16 code.
4775    case 'y': // Equivalent to "r", backwards compatibility only.
4776    case 'f': // floating-point registers.
4777    case 'c': // $25 for indirect jumps
4778    case 'l': // lo register
4779    case 'x': // hilo register pair
4780      Info.setAllowsRegister();
4781      return true;
4782    case 'R': // An address that can be used in a non-macro load or store
4783      Info.setAllowsMemory();
4784      return true;
4785    }
4786  }
4787
4788  virtual const char *getClobbers() const {
4789    // FIXME: Implement!
4790    return "";
4791  }
4792
4793  virtual bool HandleTargetFeatures(std::vector<std::string> &Features,
4794                                    DiagnosticsEngine &Diags) {
4795    IsMips16 = false;
4796    IsMicromips = false;
4797    IsNan2008 = false;
4798    IsSingleFloat = false;
4799    FloatABI = HardFloat;
4800    DspRev = NoDSP;
4801
4802    for (std::vector<std::string>::iterator it = Features.begin(),
4803         ie = Features.end(); it != ie; ++it) {
4804      if (*it == "+single-float")
4805        IsSingleFloat = true;
4806      else if (*it == "+soft-float")
4807        FloatABI = SoftFloat;
4808      else if (*it == "+mips16")
4809        IsMips16 = true;
4810      else if (*it == "+micromips")
4811        IsMicromips = true;
4812      else if (*it == "+dsp")
4813        DspRev = std::max(DspRev, DSP1);
4814      else if (*it == "+dspr2")
4815        DspRev = std::max(DspRev, DSP2);
4816      else if (*it == "+msa")
4817        HasMSA = true;
4818      else if (*it == "+nan2008")
4819        IsNan2008 = true;
4820    }
4821
4822    // Remove front-end specific options.
4823    std::vector<std::string>::iterator it =
4824      std::find(Features.begin(), Features.end(), "+soft-float");
4825    if (it != Features.end())
4826      Features.erase(it);
4827    it = std::find(Features.begin(), Features.end(), "+nan2008");
4828    if (it != Features.end())
4829      Features.erase(it);
4830
4831    return true;
4832  }
4833
4834  virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4835    if (RegNo == 0) return 4;
4836    if (RegNo == 1) return 5;
4837    return -1;
4838  }
4839};
4840
4841const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4842#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4843#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4844                                              ALL_LANGUAGES },
4845#include "clang/Basic/BuiltinsMips.def"
4846};
4847
4848class Mips32TargetInfoBase : public MipsTargetInfoBase {
4849public:
4850  Mips32TargetInfoBase(const llvm::Triple &Triple)
4851      : MipsTargetInfoBase(Triple, "o32", "mips32") {
4852    SizeType = UnsignedInt;
4853    PtrDiffType = SignedInt;
4854    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4855  }
4856  virtual bool setABI(const std::string &Name) {
4857    if ((Name == "o32") || (Name == "eabi")) {
4858      ABI = Name;
4859      return true;
4860    } else if (Name == "32") {
4861      ABI = "o32";
4862      return true;
4863    } else
4864      return false;
4865  }
4866  virtual void getTargetDefines(const LangOptions &Opts,
4867                                MacroBuilder &Builder) const {
4868    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4869
4870    if (ABI == "o32") {
4871      Builder.defineMacro("__mips_o32");
4872      Builder.defineMacro("_ABIO32", "1");
4873      Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4874    }
4875    else if (ABI == "eabi")
4876      Builder.defineMacro("__mips_eabi");
4877    else
4878      llvm_unreachable("Invalid ABI for Mips32.");
4879  }
4880  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4881                                unsigned &NumAliases) const {
4882    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4883      { { "at" },  "$1" },
4884      { { "v0" },  "$2" },
4885      { { "v1" },  "$3" },
4886      { { "a0" },  "$4" },
4887      { { "a1" },  "$5" },
4888      { { "a2" },  "$6" },
4889      { { "a3" },  "$7" },
4890      { { "t0" },  "$8" },
4891      { { "t1" },  "$9" },
4892      { { "t2" }, "$10" },
4893      { { "t3" }, "$11" },
4894      { { "t4" }, "$12" },
4895      { { "t5" }, "$13" },
4896      { { "t6" }, "$14" },
4897      { { "t7" }, "$15" },
4898      { { "s0" }, "$16" },
4899      { { "s1" }, "$17" },
4900      { { "s2" }, "$18" },
4901      { { "s3" }, "$19" },
4902      { { "s4" }, "$20" },
4903      { { "s5" }, "$21" },
4904      { { "s6" }, "$22" },
4905      { { "s7" }, "$23" },
4906      { { "t8" }, "$24" },
4907      { { "t9" }, "$25" },
4908      { { "k0" }, "$26" },
4909      { { "k1" }, "$27" },
4910      { { "gp" }, "$28" },
4911      { { "sp","$sp" }, "$29" },
4912      { { "fp","$fp" }, "$30" },
4913      { { "ra" }, "$31" }
4914    };
4915    Aliases = GCCRegAliases;
4916    NumAliases = llvm::array_lengthof(GCCRegAliases);
4917  }
4918};
4919
4920class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4921public:
4922  Mips32EBTargetInfo(const llvm::Triple &Triple)
4923      : Mips32TargetInfoBase(Triple) {
4924    DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4925                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4926  }
4927  virtual void getTargetDefines(const LangOptions &Opts,
4928                                MacroBuilder &Builder) const {
4929    DefineStd(Builder, "MIPSEB", Opts);
4930    Builder.defineMacro("_MIPSEB");
4931    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4932  }
4933};
4934
4935class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4936public:
4937  Mips32ELTargetInfo(const llvm::Triple &Triple)
4938      : Mips32TargetInfoBase(Triple) {
4939    BigEndian = false;
4940    DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4941                        "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4942  }
4943  virtual void getTargetDefines(const LangOptions &Opts,
4944                                MacroBuilder &Builder) const {
4945    DefineStd(Builder, "MIPSEL", Opts);
4946    Builder.defineMacro("_MIPSEL");
4947    Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4948  }
4949};
4950
4951class Mips64TargetInfoBase : public MipsTargetInfoBase {
4952  virtual void SetDescriptionString(const std::string &Name) = 0;
4953public:
4954  Mips64TargetInfoBase(const llvm::Triple &Triple)
4955      : MipsTargetInfoBase(Triple, "n64", "mips64") {
4956    LongWidth = LongAlign = 64;
4957    PointerWidth = PointerAlign = 64;
4958    LongDoubleWidth = LongDoubleAlign = 128;
4959    LongDoubleFormat = &llvm::APFloat::IEEEquad;
4960    if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4961      LongDoubleWidth = LongDoubleAlign = 64;
4962      LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4963    }
4964    SuitableAlign = 128;
4965    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4966  }
4967  virtual bool setABI(const std::string &Name) {
4968    SetDescriptionString(Name);
4969    if (Name == "n32") {
4970      LongWidth = LongAlign = 32;
4971      PointerWidth = PointerAlign = 32;
4972      ABI = Name;
4973      return true;
4974    } else if (Name == "n64") {
4975      ABI = Name;
4976      return true;
4977    } else if (Name == "64") {
4978      ABI = "n64";
4979      return true;
4980    } else
4981      return false;
4982  }
4983  virtual void getTargetDefines(const LangOptions &Opts,
4984                                MacroBuilder &Builder) const {
4985    MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4986
4987    Builder.defineMacro("__mips64");
4988    Builder.defineMacro("__mips64__");
4989
4990    if (ABI == "n32") {
4991      Builder.defineMacro("__mips_n32");
4992      Builder.defineMacro("_ABIN32", "2");
4993      Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4994    }
4995    else if (ABI == "n64") {
4996      Builder.defineMacro("__mips_n64");
4997      Builder.defineMacro("_ABI64", "3");
4998      Builder.defineMacro("_MIPS_SIM", "_ABI64");
4999    }
5000    else
5001      llvm_unreachable("Invalid ABI for Mips64.");
5002  }
5003  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5004                                unsigned &NumAliases) const {
5005    static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5006      { { "at" },  "$1" },
5007      { { "v0" },  "$2" },
5008      { { "v1" },  "$3" },
5009      { { "a0" },  "$4" },
5010      { { "a1" },  "$5" },
5011      { { "a2" },  "$6" },
5012      { { "a3" },  "$7" },
5013      { { "a4" },  "$8" },
5014      { { "a5" },  "$9" },
5015      { { "a6" }, "$10" },
5016      { { "a7" }, "$11" },
5017      { { "t0" }, "$12" },
5018      { { "t1" }, "$13" },
5019      { { "t2" }, "$14" },
5020      { { "t3" }, "$15" },
5021      { { "s0" }, "$16" },
5022      { { "s1" }, "$17" },
5023      { { "s2" }, "$18" },
5024      { { "s3" }, "$19" },
5025      { { "s4" }, "$20" },
5026      { { "s5" }, "$21" },
5027      { { "s6" }, "$22" },
5028      { { "s7" }, "$23" },
5029      { { "t8" }, "$24" },
5030      { { "t9" }, "$25" },
5031      { { "k0" }, "$26" },
5032      { { "k1" }, "$27" },
5033      { { "gp" }, "$28" },
5034      { { "sp","$sp" }, "$29" },
5035      { { "fp","$fp" }, "$30" },
5036      { { "ra" }, "$31" }
5037    };
5038    Aliases = GCCRegAliases;
5039    NumAliases = llvm::array_lengthof(GCCRegAliases);
5040  }
5041};
5042
5043class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5044  virtual void SetDescriptionString(const std::string &Name) {
5045    // Change DescriptionString only if ABI is n32.
5046    if (Name == "n32")
5047      DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5048                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5049                          "v64:64:64-n32:64-S128";
5050  }
5051public:
5052  Mips64EBTargetInfo(const llvm::Triple &Triple)
5053      : Mips64TargetInfoBase(Triple) {
5054    // Default ABI is n64.
5055    DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5056                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5057                        "v64:64:64-n32:64-S128";
5058  }
5059  virtual void getTargetDefines(const LangOptions &Opts,
5060                                MacroBuilder &Builder) const {
5061    DefineStd(Builder, "MIPSEB", Opts);
5062    Builder.defineMacro("_MIPSEB");
5063    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5064  }
5065};
5066
5067class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5068  virtual void SetDescriptionString(const std::string &Name) {
5069    // Change DescriptionString only if ABI is n32.
5070    if (Name == "n32")
5071      DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5072                          "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5073                          "-v64:64:64-n32:64-S128";
5074  }
5075public:
5076  Mips64ELTargetInfo(const llvm::Triple &Triple)
5077      : Mips64TargetInfoBase(Triple) {
5078    // Default ABI is n64.
5079    BigEndian = false;
5080    DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5081                        "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5082                        "v64:64:64-n32:64-S128";
5083  }
5084  virtual void getTargetDefines(const LangOptions &Opts,
5085                                MacroBuilder &Builder) const {
5086    DefineStd(Builder, "MIPSEL", Opts);
5087    Builder.defineMacro("_MIPSEL");
5088    Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5089  }
5090};
5091} // end anonymous namespace.
5092
5093namespace {
5094class PNaClTargetInfo : public TargetInfo {
5095public:
5096  PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5097    BigEndian = false;
5098    this->UserLabelPrefix = "";
5099    this->LongAlign = 32;
5100    this->LongWidth = 32;
5101    this->PointerAlign = 32;
5102    this->PointerWidth = 32;
5103    this->IntMaxType = TargetInfo::SignedLongLong;
5104    this->UIntMaxType = TargetInfo::UnsignedLongLong;
5105    this->Int64Type = TargetInfo::SignedLongLong;
5106    this->DoubleAlign = 64;
5107    this->LongDoubleWidth = 64;
5108    this->LongDoubleAlign = 64;
5109    this->SizeType = TargetInfo::UnsignedInt;
5110    this->PtrDiffType = TargetInfo::SignedInt;
5111    this->IntPtrType = TargetInfo::SignedInt;
5112    this->RegParmMax = 0; // Disallow regparm
5113    DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5114                        "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5115  }
5116
5117  void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5118  }
5119  virtual void getArchDefines(const LangOptions &Opts,
5120                              MacroBuilder &Builder) const {
5121    Builder.defineMacro("__le32__");
5122    Builder.defineMacro("__pnacl__");
5123  }
5124  virtual void getTargetDefines(const LangOptions &Opts,
5125                                MacroBuilder &Builder) const {
5126    Builder.defineMacro("__LITTLE_ENDIAN__");
5127    getArchDefines(Opts, Builder);
5128  }
5129  virtual bool hasFeature(StringRef Feature) const {
5130    return Feature == "pnacl";
5131  }
5132  virtual void getTargetBuiltins(const Builtin::Info *&Records,
5133                                 unsigned &NumRecords) const {
5134  }
5135  virtual BuiltinVaListKind getBuiltinVaListKind() const {
5136    return TargetInfo::PNaClABIBuiltinVaList;
5137  }
5138  virtual void getGCCRegNames(const char * const *&Names,
5139                              unsigned &NumNames) const;
5140  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5141                                unsigned &NumAliases) const;
5142  virtual bool validateAsmConstraint(const char *&Name,
5143                                     TargetInfo::ConstraintInfo &Info) const {
5144    return false;
5145  }
5146
5147  virtual const char *getClobbers() const {
5148    return "";
5149  }
5150};
5151
5152void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5153                                     unsigned &NumNames) const {
5154  Names = NULL;
5155  NumNames = 0;
5156}
5157
5158void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5159                                       unsigned &NumAliases) const {
5160  Aliases = NULL;
5161  NumAliases = 0;
5162}
5163} // end anonymous namespace.
5164
5165namespace {
5166  static const unsigned SPIRAddrSpaceMap[] = {
5167    1,    // opencl_global
5168    3,    // opencl_local
5169    2,    // opencl_constant
5170    0,    // cuda_device
5171    0,    // cuda_constant
5172    0     // cuda_shared
5173  };
5174  class SPIRTargetInfo : public TargetInfo {
5175  public:
5176    SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5177      assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5178        "SPIR target must use unknown OS");
5179      assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5180        "SPIR target must use unknown environment type");
5181      BigEndian = false;
5182      TLSSupported = false;
5183      LongWidth = LongAlign = 64;
5184      AddrSpaceMap = &SPIRAddrSpaceMap;
5185      UseAddrSpaceMapMangling = true;
5186      // Define available target features
5187      // These must be defined in sorted order!
5188      NoAsmVariants = true;
5189    }
5190    virtual void getTargetDefines(const LangOptions &Opts,
5191                                  MacroBuilder &Builder) const {
5192      DefineStd(Builder, "SPIR", Opts);
5193    }
5194    virtual bool hasFeature(StringRef Feature) const {
5195      return Feature == "spir";
5196    }
5197
5198    virtual void getTargetBuiltins(const Builtin::Info *&Records,
5199                                   unsigned &NumRecords) const {}
5200    virtual const char *getClobbers() const {
5201      return "";
5202    }
5203    virtual void getGCCRegNames(const char * const *&Names,
5204                                unsigned &NumNames) const {}
5205    virtual bool validateAsmConstraint(const char *&Name,
5206                                       TargetInfo::ConstraintInfo &info) const {
5207      return true;
5208    }
5209    virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5210                                  unsigned &NumAliases) const {}
5211    virtual BuiltinVaListKind getBuiltinVaListKind() const {
5212      return TargetInfo::VoidPtrBuiltinVaList;
5213    }
5214  };
5215
5216
5217  class SPIR32TargetInfo : public SPIRTargetInfo {
5218  public:
5219    SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5220      PointerWidth = PointerAlign = 32;
5221      SizeType     = TargetInfo::UnsignedInt;
5222      PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5223      DescriptionString
5224        = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5225          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5226          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5227          "v512:512:512-v1024:1024:1024";
5228    }
5229    virtual void getTargetDefines(const LangOptions &Opts,
5230                                  MacroBuilder &Builder) const {
5231      DefineStd(Builder, "SPIR32", Opts);
5232    }
5233  };
5234
5235  class SPIR64TargetInfo : public SPIRTargetInfo {
5236  public:
5237    SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5238      PointerWidth = PointerAlign = 64;
5239      SizeType     = TargetInfo::UnsignedLong;
5240      PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5241      DescriptionString
5242        = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5243          "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5244          "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5245          "v512:512:512-v1024:1024:1024";
5246    }
5247    virtual void getTargetDefines(const LangOptions &Opts,
5248                                  MacroBuilder &Builder) const {
5249      DefineStd(Builder, "SPIR64", Opts);
5250    }
5251  };
5252}
5253
5254namespace {
5255class XCoreTargetInfo : public TargetInfo {
5256  static const Builtin::Info BuiltinInfo[];
5257public:
5258  XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5259    BigEndian = false;
5260    NoAsmVariants = true;
5261    LongLongAlign = 32;
5262    SuitableAlign = 32;
5263    DoubleAlign = LongDoubleAlign = 32;
5264    UseZeroLengthBitfieldAlignment = true;
5265    DescriptionString = "e-p:32:32:32-a0:0:32-n32"
5266                        "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32"
5267                        "-f16:16:32-f32:32:32-f64:32:32";
5268  }
5269  virtual void getTargetDefines(const LangOptions &Opts,
5270                                MacroBuilder &Builder) const {
5271    Builder.defineMacro("__XS1B__");
5272  }
5273  virtual void getTargetBuiltins(const Builtin::Info *&Records,
5274                                 unsigned &NumRecords) const {
5275    Records = BuiltinInfo;
5276    NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
5277  }
5278  virtual BuiltinVaListKind getBuiltinVaListKind() const {
5279    return TargetInfo::VoidPtrBuiltinVaList;
5280  }
5281  virtual const char *getClobbers() const {
5282    return "";
5283  }
5284  virtual void getGCCRegNames(const char * const *&Names,
5285                              unsigned &NumNames) const {
5286    static const char * const GCCRegNames[] = {
5287      "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
5288      "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
5289    };
5290    Names = GCCRegNames;
5291    NumNames = llvm::array_lengthof(GCCRegNames);
5292  }
5293  virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5294                                unsigned &NumAliases) const {
5295    Aliases = NULL;
5296    NumAliases = 0;
5297  }
5298  virtual bool validateAsmConstraint(const char *&Name,
5299                                     TargetInfo::ConstraintInfo &Info) const {
5300    return false;
5301  }
5302};
5303
5304const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
5305#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5306#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5307                                              ALL_LANGUAGES },
5308#include "clang/Basic/BuiltinsXCore.def"
5309};
5310} // end anonymous namespace.
5311
5312
5313//===----------------------------------------------------------------------===//
5314// Driver code
5315//===----------------------------------------------------------------------===//
5316
5317static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5318  llvm::Triple::OSType os = Triple.getOS();
5319
5320  switch (Triple.getArch()) {
5321  default:
5322    return NULL;
5323
5324  case llvm::Triple::xcore:
5325    return new XCoreTargetInfo(Triple);
5326
5327  case llvm::Triple::hexagon:
5328    return new HexagonTargetInfo(Triple);
5329
5330  case llvm::Triple::aarch64:
5331    switch (os) {
5332    case llvm::Triple::Linux:
5333      return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5334    default:
5335      return new AArch64TargetInfo(Triple);
5336    }
5337
5338  case llvm::Triple::arm:
5339  case llvm::Triple::thumb:
5340    if (Triple.isOSDarwin())
5341      return new DarwinARMTargetInfo(Triple);
5342
5343    switch (os) {
5344    case llvm::Triple::Linux:
5345      return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5346    case llvm::Triple::FreeBSD:
5347      return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5348    case llvm::Triple::NetBSD:
5349      return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5350    case llvm::Triple::OpenBSD:
5351      return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5352    case llvm::Triple::Bitrig:
5353      return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5354    case llvm::Triple::RTEMS:
5355      return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5356    case llvm::Triple::NaCl:
5357      return new NaClTargetInfo<ARMTargetInfo>(Triple);
5358    default:
5359      return new ARMTargetInfo(Triple);
5360    }
5361
5362  case llvm::Triple::msp430:
5363    return new MSP430TargetInfo(Triple);
5364
5365  case llvm::Triple::mips:
5366    switch (os) {
5367    case llvm::Triple::Linux:
5368      return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5369    case llvm::Triple::RTEMS:
5370      return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5371    case llvm::Triple::FreeBSD:
5372      return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5373    case llvm::Triple::NetBSD:
5374      return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5375    default:
5376      return new Mips32EBTargetInfo(Triple);
5377    }
5378
5379  case llvm::Triple::mipsel:
5380    switch (os) {
5381    case llvm::Triple::Linux:
5382      return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5383    case llvm::Triple::RTEMS:
5384      return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5385    case llvm::Triple::FreeBSD:
5386      return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5387    case llvm::Triple::NetBSD:
5388      return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5389    case llvm::Triple::NaCl:
5390      return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
5391    default:
5392      return new Mips32ELTargetInfo(Triple);
5393    }
5394
5395  case llvm::Triple::mips64:
5396    switch (os) {
5397    case llvm::Triple::Linux:
5398      return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5399    case llvm::Triple::RTEMS:
5400      return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5401    case llvm::Triple::FreeBSD:
5402      return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5403    case llvm::Triple::NetBSD:
5404      return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5405    case llvm::Triple::OpenBSD:
5406      return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5407    default:
5408      return new Mips64EBTargetInfo(Triple);
5409    }
5410
5411  case llvm::Triple::mips64el:
5412    switch (os) {
5413    case llvm::Triple::Linux:
5414      return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5415    case llvm::Triple::RTEMS:
5416      return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5417    case llvm::Triple::FreeBSD:
5418      return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5419    case llvm::Triple::NetBSD:
5420      return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5421    case llvm::Triple::OpenBSD:
5422      return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5423    default:
5424      return new Mips64ELTargetInfo(Triple);
5425    }
5426
5427  case llvm::Triple::le32:
5428    switch (os) {
5429      case llvm::Triple::NaCl:
5430        return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5431      default:
5432        return NULL;
5433    }
5434
5435  case llvm::Triple::ppc:
5436    if (Triple.isOSDarwin())
5437      return new DarwinPPC32TargetInfo(Triple);
5438    switch (os) {
5439    case llvm::Triple::Linux:
5440      return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5441    case llvm::Triple::FreeBSD:
5442      return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5443    case llvm::Triple::NetBSD:
5444      return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5445    case llvm::Triple::OpenBSD:
5446      return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5447    case llvm::Triple::RTEMS:
5448      return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5449    default:
5450      return new PPC32TargetInfo(Triple);
5451    }
5452
5453  case llvm::Triple::ppc64:
5454    if (Triple.isOSDarwin())
5455      return new DarwinPPC64TargetInfo(Triple);
5456    switch (os) {
5457    case llvm::Triple::Linux:
5458      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5459    case llvm::Triple::Lv2:
5460      return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5461    case llvm::Triple::FreeBSD:
5462      return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5463    case llvm::Triple::NetBSD:
5464      return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5465    default:
5466      return new PPC64TargetInfo(Triple);
5467    }
5468
5469  case llvm::Triple::ppc64le:
5470    switch (os) {
5471    case llvm::Triple::Linux:
5472      return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5473    default:
5474      return new PPC64TargetInfo(Triple);
5475    }
5476
5477  case llvm::Triple::nvptx:
5478    return new NVPTX32TargetInfo(Triple);
5479  case llvm::Triple::nvptx64:
5480    return new NVPTX64TargetInfo(Triple);
5481
5482  case llvm::Triple::r600:
5483    return new R600TargetInfo(Triple);
5484
5485  case llvm::Triple::sparc:
5486    switch (os) {
5487    case llvm::Triple::Linux:
5488      return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5489    case llvm::Triple::AuroraUX:
5490      return new AuroraUXSparcV8TargetInfo(Triple);
5491    case llvm::Triple::Solaris:
5492      return new SolarisSparcV8TargetInfo(Triple);
5493    case llvm::Triple::NetBSD:
5494      return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5495    case llvm::Triple::OpenBSD:
5496      return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5497    case llvm::Triple::RTEMS:
5498      return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5499    default:
5500      return new SparcV8TargetInfo(Triple);
5501    }
5502
5503  case llvm::Triple::sparcv9:
5504    switch (os) {
5505    case llvm::Triple::Linux:
5506      return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5507    case llvm::Triple::AuroraUX:
5508      return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5509    case llvm::Triple::Solaris:
5510      return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5511    case llvm::Triple::NetBSD:
5512      return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5513    case llvm::Triple::OpenBSD:
5514      return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5515    case llvm::Triple::FreeBSD:
5516      return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5517    default:
5518      return new SparcV9TargetInfo(Triple);
5519    }
5520
5521  case llvm::Triple::systemz:
5522    switch (os) {
5523    case llvm::Triple::Linux:
5524      return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5525    default:
5526      return new SystemZTargetInfo(Triple);
5527    }
5528
5529  case llvm::Triple::tce:
5530    return new TCETargetInfo(Triple);
5531
5532  case llvm::Triple::x86:
5533    if (Triple.isOSDarwin())
5534      return new DarwinI386TargetInfo(Triple);
5535
5536    switch (os) {
5537    case llvm::Triple::AuroraUX:
5538      return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5539    case llvm::Triple::Linux:
5540      return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5541    case llvm::Triple::DragonFly:
5542      return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5543    case llvm::Triple::NetBSD:
5544      return new NetBSDI386TargetInfo(Triple);
5545    case llvm::Triple::OpenBSD:
5546      return new OpenBSDI386TargetInfo(Triple);
5547    case llvm::Triple::Bitrig:
5548      return new BitrigI386TargetInfo(Triple);
5549    case llvm::Triple::FreeBSD:
5550      return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5551    case llvm::Triple::KFreeBSD:
5552      return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5553    case llvm::Triple::Minix:
5554      return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5555    case llvm::Triple::Solaris:
5556      return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5557    case llvm::Triple::Cygwin:
5558      return new CygwinX86_32TargetInfo(Triple);
5559    case llvm::Triple::MinGW32:
5560      return new MinGWX86_32TargetInfo(Triple);
5561    case llvm::Triple::Win32:
5562      return new VisualStudioWindowsX86_32TargetInfo(Triple);
5563    case llvm::Triple::Haiku:
5564      return new HaikuX86_32TargetInfo(Triple);
5565    case llvm::Triple::RTEMS:
5566      return new RTEMSX86_32TargetInfo(Triple);
5567    case llvm::Triple::NaCl:
5568      return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5569    default:
5570      return new X86_32TargetInfo(Triple);
5571    }
5572
5573  case llvm::Triple::x86_64:
5574    if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5575      return new DarwinX86_64TargetInfo(Triple);
5576
5577    switch (os) {
5578    case llvm::Triple::AuroraUX:
5579      return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5580    case llvm::Triple::Linux:
5581      return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5582    case llvm::Triple::DragonFly:
5583      return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5584    case llvm::Triple::NetBSD:
5585      return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5586    case llvm::Triple::OpenBSD:
5587      return new OpenBSDX86_64TargetInfo(Triple);
5588    case llvm::Triple::Bitrig:
5589      return new BitrigX86_64TargetInfo(Triple);
5590    case llvm::Triple::FreeBSD:
5591      return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5592    case llvm::Triple::KFreeBSD:
5593      return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5594    case llvm::Triple::Solaris:
5595      return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5596    case llvm::Triple::MinGW32:
5597      return new MinGWX86_64TargetInfo(Triple);
5598    case llvm::Triple::Win32:   // This is what Triple.h supports now.
5599      return new VisualStudioWindowsX86_64TargetInfo(Triple);
5600    case llvm::Triple::NaCl:
5601      return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5602    default:
5603      return new X86_64TargetInfo(Triple);
5604    }
5605
5606    case llvm::Triple::spir: {
5607      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5608          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5609        return NULL;
5610      return new SPIR32TargetInfo(Triple);
5611    }
5612    case llvm::Triple::spir64: {
5613      if (Triple.getOS() != llvm::Triple::UnknownOS ||
5614          Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5615        return NULL;
5616      return new SPIR64TargetInfo(Triple);
5617    }
5618  }
5619}
5620
5621/// CreateTargetInfo - Return the target info object for the specified target
5622/// triple.
5623TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5624                                         TargetOptions *Opts) {
5625  llvm::Triple Triple(Opts->Triple);
5626
5627  // Construct the target
5628  OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5629  if (!Target) {
5630    Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5631    return 0;
5632  }
5633  Target->setTargetOpts(Opts);
5634
5635  // Set the target CPU if specified.
5636  if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5637    Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5638    return 0;
5639  }
5640
5641  // Set the target ABI if specified.
5642  if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5643    Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5644    return 0;
5645  }
5646
5647  // Set the target C++ ABI.
5648  if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5649    Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5650    return 0;
5651  }
5652
5653  // Set the fp math unit.
5654  if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
5655    Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
5656    return 0;
5657  }
5658
5659  // Compute the default target features, we need the target to handle this
5660  // because features may have dependencies on one another.
5661  llvm::StringMap<bool> Features;
5662  Target->getDefaultFeatures(Features);
5663
5664  // Apply the user specified deltas.
5665  for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
5666       I < N; ++I) {
5667    const char *Name = Opts->FeaturesAsWritten[I].c_str();
5668    // Apply the feature via the target.
5669    bool Enabled = Name[0] == '+';
5670    Target->setFeatureEnabled(Features, Name + 1, Enabled);
5671  }
5672
5673  // Add the features to the compile options.
5674  //
5675  // FIXME: If we are completely confident that we have the right set, we only
5676  // need to pass the minuses.
5677  Opts->Features.clear();
5678  for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5679         ie = Features.end(); it != ie; ++it)
5680    Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5681  if (!Target->HandleTargetFeatures(Opts->Features, Diags))
5682    return 0;
5683
5684  return Target.take();
5685}
5686