1/* ===-- clear_cache.c - Implement __clear_cache ---------------------------=== 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is dual licensed under the MIT and the University of Illinois Open 6 * Source Licenses. See LICENSE.TXT for details. 7 * 8 * ===----------------------------------------------------------------------=== 9 */ 10 11#include "int_lib.h" 12 13#if __APPLE__ 14 #include <libkern/OSCacheControl.h> 15#endif 16#if defined(__NetBSD__) && defined(__arm__) 17 #include <machine/sysarch.h> 18#endif 19 20#if defined(ANDROID) && defined(__mips__) 21 #include <sys/cachectl.h> 22#endif 23 24#if defined(ANDROID) && defined(__arm__) 25 #include <asm/unistd.h> 26#endif 27 28/* 29 * The compiler generates calls to __clear_cache() when creating 30 * trampoline functions on the stack for use with nested functions. 31 * It is expected to invalidate the instruction cache for the 32 * specified range. 33 */ 34 35COMPILER_RT_EXPORT void 36__clear_cache(void* start, void* end) 37{ 38#if __i386__ || __x86_64__ 39/* 40 * Intel processors have a unified instruction and data cache 41 * so there is nothing to do 42 */ 43#elif defined(__arm__) && !defined(__APPLE__) 44 #if defined(__NetBSD__) 45 struct arm_sync_icache_args arg; 46 47 arg.addr = (uintptr_t)start; 48 arg.len = (uintptr_t)end - (uintptr_t)start; 49 50 sysarch(ARM_SYNC_ICACHE, &arg); 51 #elif defined(ANDROID) 52 const register int start_reg __asm("r0") = (int) (intptr_t) start; 53 const register int end_reg __asm("r1") = (int) (intptr_t) end; 54 const register int flags __asm("r2") = 0; 55 const register int syscall_nr __asm("r7") = __ARM_NR_cacheflush; 56 __asm __volatile("svc 0x0" : "=r"(start_reg) 57 : "r"(syscall_nr), "r"(start_reg), "r"(end_reg), "r"(flags) : "r0"); 58 if (start_reg != 0) { 59 compilerrt_abort(); 60 } 61 #else 62 compilerrt_abort(); 63 #endif 64#elif defined(ANDROID) && defined(__mips__) 65 const uintptr_t start_int = (uintptr_t) start; 66 const uintptr_t end_int = (uintptr_t) end; 67 _flush_cache(start, (end_int - start_int), BCACHE); 68#elif defined(__aarch64__) && !defined(__APPLE__) 69 uint64_t xstart = (uint64_t)(uintptr_t) start; 70 uint64_t xend = (uint64_t)(uintptr_t) end; 71 72 // Get Cache Type Info 73 uint64_t ctr_el0; 74 __asm __volatile("mrs %0, ctr_el0" : "=r"(ctr_el0)); 75 76 /* 77 * dc & ic instructions must use 64bit registers so we don't use 78 * uintptr_t in case this runs in an IPL32 environment. 79 */ 80 const size_t dcache_line_size = 4 << ((ctr_el0 >> 16) & 15); 81 for (uint64_t addr = xstart; addr < xend; addr += dcache_line_size) 82 __asm __volatile("dc cvau, %0" :: "r"(addr)); 83 __asm __volatile("dsb ish"); 84 85 const size_t icache_line_size = 4 << ((ctr_el0 >> 0) & 15); 86 for (uint64_t addr = xstart; addr < xend; addr += icache_line_size) 87 __asm __volatile("ic ivau, %0" :: "r"(addr)); 88 __asm __volatile("isb sy"); 89#else 90 #if __APPLE__ 91 /* On Darwin, sys_icache_invalidate() provides this functionality */ 92 sys_icache_invalidate(start, end-start); 93 #else 94 compilerrt_abort(); 95 #endif 96#endif 97} 98 99