1#ifndef _ASM_X86_KVM_H 2#define _ASM_X86_KVM_H 3 4/* 5 * KVM x86 specific structures and definitions 6 * 7 */ 8 9#include <linux/types.h> 10#include <linux/ioctl.h> 11 12#define DE_VECTOR 0 13#define DB_VECTOR 1 14#define BP_VECTOR 3 15#define OF_VECTOR 4 16#define BR_VECTOR 5 17#define UD_VECTOR 6 18#define NM_VECTOR 7 19#define DF_VECTOR 8 20#define TS_VECTOR 10 21#define NP_VECTOR 11 22#define SS_VECTOR 12 23#define GP_VECTOR 13 24#define PF_VECTOR 14 25#define MF_VECTOR 16 26#define MC_VECTOR 18 27 28/* Select x86 specific features in <linux/kvm.h> */ 29#define __KVM_HAVE_PIT 30#define __KVM_HAVE_IOAPIC 31#define __KVM_HAVE_IRQ_LINE 32#define __KVM_HAVE_MSI 33#define __KVM_HAVE_USER_NMI 34#define __KVM_HAVE_GUEST_DEBUG 35#define __KVM_HAVE_MSIX 36#define __KVM_HAVE_MCE 37#define __KVM_HAVE_PIT_STATE2 38#define __KVM_HAVE_XEN_HVM 39#define __KVM_HAVE_VCPU_EVENTS 40#define __KVM_HAVE_DEBUGREGS 41#define __KVM_HAVE_XSAVE 42#define __KVM_HAVE_XCRS 43#define __KVM_HAVE_READONLY_MEM 44 45/* Architectural interrupt line count. */ 46#define KVM_NR_INTERRUPTS 256 47 48struct kvm_memory_alias { 49 __u32 slot; /* this has a different namespace than memory slots */ 50 __u32 flags; 51 __u64 guest_phys_addr; 52 __u64 memory_size; 53 __u64 target_phys_addr; 54}; 55 56/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ 57struct kvm_pic_state { 58 __u8 last_irr; /* edge detection */ 59 __u8 irr; /* interrupt request register */ 60 __u8 imr; /* interrupt mask register */ 61 __u8 isr; /* interrupt service register */ 62 __u8 priority_add; /* highest irq priority */ 63 __u8 irq_base; 64 __u8 read_reg_select; 65 __u8 poll; 66 __u8 special_mask; 67 __u8 init_state; 68 __u8 auto_eoi; 69 __u8 rotate_on_auto_eoi; 70 __u8 special_fully_nested_mode; 71 __u8 init4; /* true if 4 byte init */ 72 __u8 elcr; /* PIIX edge/trigger selection */ 73 __u8 elcr_mask; 74}; 75 76#define KVM_IOAPIC_NUM_PINS 24 77struct kvm_ioapic_state { 78 __u64 base_address; 79 __u32 ioregsel; 80 __u32 id; 81 __u32 irr; 82 __u32 pad; 83 union { 84 __u64 bits; 85 struct { 86 __u8 vector; 87 __u8 delivery_mode:3; 88 __u8 dest_mode:1; 89 __u8 delivery_status:1; 90 __u8 polarity:1; 91 __u8 remote_irr:1; 92 __u8 trig_mode:1; 93 __u8 mask:1; 94 __u8 reserve:7; 95 __u8 reserved[4]; 96 __u8 dest_id; 97 } fields; 98 } redirtbl[KVM_IOAPIC_NUM_PINS]; 99}; 100 101#define KVM_IRQCHIP_PIC_MASTER 0 102#define KVM_IRQCHIP_PIC_SLAVE 1 103#define KVM_IRQCHIP_IOAPIC 2 104#define KVM_NR_IRQCHIPS 3 105 106/* for KVM_GET_REGS and KVM_SET_REGS */ 107struct kvm_regs { 108 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 109 __u64 rax, rbx, rcx, rdx; 110 __u64 rsi, rdi, rsp, rbp; 111 __u64 r8, r9, r10, r11; 112 __u64 r12, r13, r14, r15; 113 __u64 rip, rflags; 114}; 115 116/* for KVM_GET_LAPIC and KVM_SET_LAPIC */ 117#define KVM_APIC_REG_SIZE 0x400 118struct kvm_lapic_state { 119 char regs[KVM_APIC_REG_SIZE]; 120}; 121 122struct kvm_segment { 123 __u64 base; 124 __u32 limit; 125 __u16 selector; 126 __u8 type; 127 __u8 present, dpl, db, s, l, g, avl; 128 __u8 unusable; 129 __u8 padding; 130}; 131 132struct kvm_dtable { 133 __u64 base; 134 __u16 limit; 135 __u16 padding[3]; 136}; 137 138 139/* for KVM_GET_SREGS and KVM_SET_SREGS */ 140struct kvm_sregs { 141 /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ 142 struct kvm_segment cs, ds, es, fs, gs, ss; 143 struct kvm_segment tr, ldt; 144 struct kvm_dtable gdt, idt; 145 __u64 cr0, cr2, cr3, cr4, cr8; 146 __u64 efer; 147 __u64 apic_base; 148 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 149}; 150 151/* for KVM_GET_FPU and KVM_SET_FPU */ 152struct kvm_fpu { 153 __u8 fpr[8][16]; 154 __u16 fcw; 155 __u16 fsw; 156 __u8 ftwx; /* in fxsave format */ 157 __u8 pad1; 158 __u16 last_opcode; 159 __u64 last_ip; 160 __u64 last_dp; 161 __u8 xmm[16][16]; 162 __u32 mxcsr; 163 __u32 pad2; 164}; 165 166struct kvm_msr_entry { 167 __u32 index; 168 __u32 reserved; 169 __u64 data; 170}; 171 172/* for KVM_GET_MSRS and KVM_SET_MSRS */ 173struct kvm_msrs { 174 __u32 nmsrs; /* number of msrs in entries */ 175 __u32 pad; 176 177 struct kvm_msr_entry entries[0]; 178}; 179 180/* for KVM_GET_MSR_INDEX_LIST */ 181struct kvm_msr_list { 182 __u32 nmsrs; /* number of msrs in entries */ 183 __u32 indices[0]; 184}; 185 186 187struct kvm_cpuid_entry { 188 __u32 function; 189 __u32 eax; 190 __u32 ebx; 191 __u32 ecx; 192 __u32 edx; 193 __u32 padding; 194}; 195 196/* for KVM_SET_CPUID */ 197struct kvm_cpuid { 198 __u32 nent; 199 __u32 padding; 200 struct kvm_cpuid_entry entries[0]; 201}; 202 203struct kvm_cpuid_entry2 { 204 __u32 function; 205 __u32 index; 206 __u32 flags; 207 __u32 eax; 208 __u32 ebx; 209 __u32 ecx; 210 __u32 edx; 211 __u32 padding[3]; 212}; 213 214#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX BIT(0) 215#define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1) 216#define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2) 217 218/* for KVM_SET_CPUID2 */ 219struct kvm_cpuid2 { 220 __u32 nent; 221 __u32 padding; 222 struct kvm_cpuid_entry2 entries[0]; 223}; 224 225/* for KVM_GET_PIT and KVM_SET_PIT */ 226struct kvm_pit_channel_state { 227 __u32 count; /* can be 65536 */ 228 __u16 latched_count; 229 __u8 count_latched; 230 __u8 status_latched; 231 __u8 status; 232 __u8 read_state; 233 __u8 write_state; 234 __u8 write_latch; 235 __u8 rw_mode; 236 __u8 mode; 237 __u8 bcd; 238 __u8 gate; 239 __s64 count_load_time; 240}; 241 242struct kvm_debug_exit_arch { 243 __u32 exception; 244 __u32 pad; 245 __u64 pc; 246 __u64 dr6; 247 __u64 dr7; 248}; 249 250#define KVM_GUESTDBG_USE_SW_BP 0x00010000 251#define KVM_GUESTDBG_USE_HW_BP 0x00020000 252#define KVM_GUESTDBG_INJECT_DB 0x00040000 253#define KVM_GUESTDBG_INJECT_BP 0x00080000 254 255/* for KVM_SET_GUEST_DEBUG */ 256struct kvm_guest_debug_arch { 257 __u64 debugreg[8]; 258}; 259 260struct kvm_pit_state { 261 struct kvm_pit_channel_state channels[3]; 262}; 263 264#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 265 266struct kvm_pit_state2 { 267 struct kvm_pit_channel_state channels[3]; 268 __u32 flags; 269 __u32 reserved[9]; 270}; 271 272struct kvm_reinject_control { 273 __u8 pit_reinject; 274 __u8 reserved[31]; 275}; 276 277/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */ 278#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 279#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 280#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 281 282/* Interrupt shadow states */ 283#define KVM_X86_SHADOW_INT_MOV_SS 0x01 284#define KVM_X86_SHADOW_INT_STI 0x02 285 286/* for KVM_GET/SET_VCPU_EVENTS */ 287struct kvm_vcpu_events { 288 struct { 289 __u8 injected; 290 __u8 nr; 291 __u8 has_error_code; 292 __u8 pad; 293 __u32 error_code; 294 } exception; 295 struct { 296 __u8 injected; 297 __u8 nr; 298 __u8 soft; 299 __u8 shadow; 300 } interrupt; 301 struct { 302 __u8 injected; 303 __u8 pending; 304 __u8 masked; 305 __u8 pad; 306 } nmi; 307 __u32 sipi_vector; 308 __u32 flags; 309 __u32 reserved[10]; 310}; 311 312/* for KVM_GET/SET_DEBUGREGS */ 313struct kvm_debugregs { 314 __u64 db[4]; 315 __u64 dr6; 316 __u64 dr7; 317 __u64 flags; 318 __u64 reserved[9]; 319}; 320 321/* for KVM_CAP_XSAVE */ 322struct kvm_xsave { 323 __u32 region[1024]; 324}; 325 326#define KVM_MAX_XCRS 16 327 328struct kvm_xcr { 329 __u32 xcr; 330 __u32 reserved; 331 __u64 value; 332}; 333 334struct kvm_xcrs { 335 __u32 nr_xcrs; 336 __u32 flags; 337 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 338 __u64 padding[16]; 339}; 340 341/* definition of registers in kvm_run */ 342struct kvm_sync_regs { 343}; 344 345#endif /* _ASM_X86_KVM_H */ 346