1224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 3224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * All rights reserved. 7224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 8224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Permission is hereby granted, free of charge, to any person obtaining a 9224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * copy of this software and associated documentation files (the "Software"), 10224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * to deal in the Software without restriction, including without limitation 11224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and/or sell copies of the Software, and to permit persons to whom the 13224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Software is furnished to do so, subject to the following conditions: 14224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 15224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The above copyright notice and this permission notice (including the next 16224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * paragraph) shall be included in all copies or substantial portions of the 17224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Software. 18224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 19224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * DEALINGS IN THE SOFTWARE. 26224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 27224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Authors: 28224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Kevin E. Martin <martin@valinux.com> 29224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Gareth Hughes <gareth@valinux.com> 30224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Keith Whitwell <keith@tungstengraphics.com> 31224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 32224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 33224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#ifndef __RADEON_DRM_H__ 34224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __RADEON_DRM_H__ 35224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 36224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#include <drm/drm.h> 37224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 38224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* WARNING: If you change any of these defines, make sure to change the 39224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * defines in the X server file (radeon_sarea.h) 40224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 41224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#ifndef __RADEON_SAREA_DEFINES__ 42224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define __RADEON_SAREA_DEFINES__ 43224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 44224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Old style state flags, required for sarea interface (1.1 and 1.2 45224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * clears) and 1.2 drm_vertex2 ioctl. 46224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 47224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_CONTEXT 0x00000001 48224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_VERTFMT 0x00000002 49224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_LINE 0x00000004 50224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_BUMPMAP 0x00000008 51224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_MASKS 0x00000010 52224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_VIEWPORT 0x00000020 53224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_SETUP 0x00000040 54224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TCL 0x00000080 55224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_MISC 0x00000100 56224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TEX0 0x00000200 57224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TEX1 0x00000400 58224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TEX2 0x00000800 59224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 60224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 61224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 62224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ 63224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_REQUIRE_QUIESCENCE 0x00010000 64224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ 65224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_ALL 0x003effff 66224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 67224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 68224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* New style per-packet identifiers for use in cmd_buffer ioctl with 69224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the RADEON_EMIT_PACKET command. Comments relate new packets to old 70224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * state bits and the packet size: 71224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 72224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_MISC 0 /* context/7 */ 73224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ 74224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ 75224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ 76224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ 77224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ 78224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ 79224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ 80224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ 81224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ 82224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ 83224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ 84224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ 85224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ 86224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ 87224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ 88224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ 89224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ 90224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ 91224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ 92224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ 93224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ 94224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ 95224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ 96224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ 97224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ 98224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ 99224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ 100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ 101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ 102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ 103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ 104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_VAP_CTL 32 /* vap/1 */ 105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ 106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ 107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ 108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ 109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ 110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ 111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ 112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ 113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ 114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ 115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ 116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ 117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ 118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ 119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ 120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ 121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ 122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ 123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ 124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ 125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ 126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ 127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ 128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ 129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ 130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ 131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ 132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ 133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_0 61 134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_1 63 136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_2 65 138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_3 67 140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_4 69 142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_FACES_5 71 144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_TEX_SIZE_0 73 146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_TEX_SIZE_1 74 147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_TEX_SIZE_2 75 148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_RB3D_BLENDCOLOR 76 149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CUBIC_FACES_0 78 151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 152224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CUBIC_FACES_1 80 153224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 154224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CUBIC_FACES_2 82 155224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 156224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TRI_PERF_CNTL 84 157224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_AFS_0 85 158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_AFS_1 86 159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_ATF_TFACTOR 87 160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCTLALL_0 88 161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCTLALL_1 89 162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCTLALL_2 90 163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCTLALL_3 91 164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCTLALL_4 92 165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_PP_TXCTLALL_5 93 166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R200_EMIT_VAP_PVS_CNTL 94 167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_MAX_STATE_PACKETS 95 168224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Commands understood by cmd_buffer ioctl. More can be added but 170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * obviously these can't be removed or changed: 171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_VECTORS 3 /* emit vector data */ 175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ 176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_PACKET3 5 /* emit hw packet */ 177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ 178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ 179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: 180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * doesn't make the cpu wait, just 181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the graphics hardware */ 182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ 183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef union { 185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int i; 186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, pad0, pad1, pad2; 188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } header; 189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, packet_id, pad0, pad1; 191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } packet; 192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, offset, stride, count; 194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } scalars; 195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, offset, stride, count; 197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } vectors; 198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, addr_lo, addr_hi, count; 200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } veclinear; 201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 202224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, buf_idx, pad0, pad1; 203224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } dma; 204224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 205224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, flags, pad0, pad1; 206224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } wait; 207224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_cmd_header_t; 208224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_WAIT_2D 0x1 210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_WAIT_3D 0x2 211224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Allowed parameters for R300_CMD_PACKET3 213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_PACKET3_CLEAR 0 215224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_PACKET3_RAW 1 216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Commands understood by cmd_buffer ioctl for R300. 218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The interface has not been stabilized, so some of these may be removed 219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * and eventually reordered before stabilization. 220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_PACKET0 1 222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_VPU 2 /* emit vertex program upload */ 223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_PACKET3 3 /* emit a packet3 */ 224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ 225224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_CP_DELAY 5 226224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_DMA_DISCARD 6 227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_WAIT 7 228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_WAIT_2D 0x1 229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_WAIT_3D 0x2 230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* these two defines are DOING IT WRONG - however 231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * we have userspace which relies on using these. 232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The wait interface is backwards compat new 233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * code should use the NEW_WAIT defines below 234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * THESE ARE NOT BIT FIELDS 235224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 236224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_WAIT_2D_CLEAN 0x3 237224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_WAIT_3D_CLEAN 0x4 238224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 239224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_NEW_WAIT_2D_3D 0x3 240224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 244224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_SCRATCH 8 245224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R300_CMD_R500FP 9 246224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 247224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef union { 248224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int u; 249224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 250224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, pad0, pad1, pad2; 251224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } header; 252224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 253224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, count, reglo, reghi; 254224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } packet0; 255224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 256224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, count, adrlo, adrhi; 257224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } vpu; 258224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 259224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, packet, pad0, pad1; 260224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } packet3; 261224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 262224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, packet; 263224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned short count; /* amount of packet2 to emit */ 264224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } delay; 265224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 266224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, buf_idx, pad0, pad1; 267224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } dma; 268224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 269224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, flags, pad0, pad1; 270224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } wait; 271224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 272224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, reg, n_bufs, flags; 273224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } scratch; 274224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct { 275224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned char cmd_type, count, adrlo, adrhi_flags; 276224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } r500fp; 277224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_r300_cmd_header_t; 278224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 279224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_FRONT 0x1 280224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_BACK 0x2 281224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_DEPTH 0x4 282224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_STENCIL 0x8 283224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CLEAR_FASTZ 0x80000000 284224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_USE_HIERZ 0x40000000 285224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_USE_COMP_ZBUF 0x20000000 286224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 287224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R500FP_CONSTANT_TYPE (1 << 1) 288224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R500FP_CONSTANT_CLAMP (1 << 2) 289224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 290224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Primitive types 291224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 292224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_POINTS 0x1 293224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_LINES 0x2 294224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_LINE_STRIP 0x3 295224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TRIANGLES 0x4 296224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TRIANGLE_FAN 0x5 297224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TRIANGLE_STRIP 0x6 298224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 299224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Vertex/indirect buffer size 300224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 301224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_BUFFER_SIZE 65536 302224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 303224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Byte offsets for indirect buffer data 304224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 305224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INDEX_PRIM_OFFSET 20 306224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 307224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SCRATCH_REG_OFFSET 32 308224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 309224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define R600_SCRATCH_REG_OFFSET 256 310224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 311224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_NR_SAREA_CLIPRECTS 12 312224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 313224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* There are 2 heaps (local/GART). Each region within a heap is a 314224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * minimum of 64k, and there are at most 64 of them per heap. 315224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 316224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_LOCAL_TEX_HEAP 0 317224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_GART_TEX_HEAP 1 318224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_NR_TEX_HEAPS 2 319224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_NR_TEX_REGIONS 64 320224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_LOG_TEX_GRANULARITY 16 321224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 322224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_MAX_TEXTURE_LEVELS 12 323224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_MAX_TEXTURE_UNITS 3 324224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 325224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_MAX_SURFACES 8 326224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 327224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Blits have strict offset rules. All blit offset must be aligned on 328224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * a 1K-byte boundary. 329224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 330224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_OFFSET_SHIFT 10 331224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 332224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 333224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 334224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#endif /* __RADEON_SAREA_DEFINES__ */ 335224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 336224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 337224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int red; 338224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int green; 339224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int blue; 340224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int alpha; 341224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} radeon_color_regs_t; 342224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 343224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 344224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Context state */ 345224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_misc; /* 0x1c14 */ 346224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_fog_color; 347224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int re_solid_color; 348224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_blendcntl; 349224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_depthoffset; 350224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_depthpitch; 351224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_zstencilcntl; 352224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 353224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_cntl; /* 0x1c38 */ 354224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_cntl; 355224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_coloroffset; 356224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int re_width_height; 357224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_colorpitch; 358224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_cntl; 359224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 360224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Vertex format state */ 361224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_coord_fmt; /* 0x1c50 */ 362224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 363224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Line state */ 364224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int re_line_pattern; /* 0x1cd0 */ 365224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int re_line_state; 366224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 367224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_line_width; /* 0x1db8 */ 368224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 369224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Bumpmap state */ 370224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_lum_matrix; /* 0x1d00 */ 371224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 372224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_rot_matrix_0; /* 0x1d58 */ 373224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_rot_matrix_1; 374224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 375224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Mask state */ 376224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_stencilrefmask; /* 0x1d7c */ 377224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_ropcntl; 378224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int rb3d_planemask; 379224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 380224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Viewport state */ 381224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_vport_xscale; /* 0x1d98 */ 382224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_vport_xoffset; 383224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_vport_yscale; 384224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_vport_yoffset; 385224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_vport_zscale; 386224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_vport_zoffset; 387224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 388224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Setup state */ 389224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_cntl_status; /* 0x2140 */ 390224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 391224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Misc state */ 392224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int re_top_left; /* 0x26c0 */ 393224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int re_misc; 394224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_context_regs_t; 395224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 396224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 397224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Zbias state */ 398224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_zbias_factor; /* 0x1dac */ 399224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int se_zbias_constant; 400224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_context2_regs_t; 401224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 402224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Setup registers for each texture unit 403224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 404224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 405224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_txfilter; 406224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_txformat; 407224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_txoffset; 408224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_txcblend; 409224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_txablend; 410224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_tfactor; 411224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int pp_border_color; 412224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_texture_regs_t; 413224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 414224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 415224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int start; 416224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int finish; 417224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int prim:8; 418224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int stateidx:8; 419224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ 420224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int vc_format; /* vertex format */ 421224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_prim_t; 422224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 423224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 424224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_context_regs_t context; 425224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 426224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_context2_regs_t context2; 427224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int dirty; 428224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_state_t; 429224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 430224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct { 431224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* The channel for communication of state information to the 432224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * kernel on firing a vertex buffer with either of the 433224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * obsoleted vertex/index ioctls. 434224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 435224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_context_regs_t context_state; 436224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 437224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int dirty; 438224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int vertsize; 439224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int vc_format; 440224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 441224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* The current cliprects, or a subset thereof. 442224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 443224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 444224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int nbox; 445224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 446224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Counters for client-side throttling of rendering clients. 447224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 448224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int last_frame; 449224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int last_dispatch; 450224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int last_clear; 451224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 452224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 453224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1]; 454224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 455224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int ctx_owner; 456224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pfState; /* number of 3d windows (0,1,2ormore) */ 457224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pfCurrentPage; /* which buffer is being displayed? */ 458224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int crtc2_base; /* CRTC2 frame offset */ 459224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int tiling_enabled; /* set by drm, read by 2d + 3d clients */ 460224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_sarea_t; 461224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 462224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* WARNING: If you change any of these defines, make sure to change the 463224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * defines in the Xserver file (xf86drmRadeon.h) 464224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 465224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * KW: actually it's illegal to change any of this (backwards compatibility). 466224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 467224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 468224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Radeon specific ioctls 469224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * The device specific ioctl range is 0x40 to 0x79. 470224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 471224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CP_INIT 0x00 472224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CP_START 0x01 473224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CP_STOP 0x02 474224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CP_RESET 0x03 475224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CP_IDLE 0x04 476224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_RESET 0x05 477224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_FULLSCREEN 0x06 478224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_SWAP 0x07 479224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CLEAR 0x08 480224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_VERTEX 0x09 481224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_INDICES 0x0A 482224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_NOT_USED 483224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_STIPPLE 0x0C 484224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_INDIRECT 0x0D 485224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_TEXTURE 0x0E 486224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_VERTEX2 0x0F 487224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CMDBUF 0x10 488224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GETPARAM 0x11 489224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_FLIP 0x12 490224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_ALLOC 0x13 491224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_FREE 0x14 492224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_INIT_HEAP 0x15 493224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_IRQ_EMIT 0x16 494224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_IRQ_WAIT 0x17 495224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CP_RESUME 0x18 496224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_SETPARAM 0x19 497224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_SURF_ALLOC 0x1a 498224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_SURF_FREE 0x1b 499224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* KMS ioctl */ 500224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_INFO 0x1c 501224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_CREATE 0x1d 502224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_MMAP 0x1e 503224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_PREAD 0x21 504224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_PWRITE 0x22 505224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_SET_DOMAIN 0x23 506224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_WAIT_IDLE 0x24 507224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_CS 0x26 508224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_INFO 0x27 509224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_SET_TILING 0x28 510224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_GET_TILING 0x29 511224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_BUSY 0x2a 512224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_GEM_VA 0x2b 513224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 514224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 515224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) 516224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 517224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 518224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 519224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) 520224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 521224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) 522224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 523224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 524224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 525224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 526224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 527224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 528224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 529224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 530224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 531224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) 532224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 533224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 534224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 535224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 536224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 537224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 538224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 539224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 540224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 541224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* KMS */ 542224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 543224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 544224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 545224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 546224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 547224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 548224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 549224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 550224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 551224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 552224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 553224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 554224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 555224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 556224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_init { 557224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum { 558224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_INIT_CP = 0x01, 559224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_CLEANUP_CP = 0x02, 560224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_INIT_R200_CP = 0x03, 561224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_INIT_R300_CP = 0x04, 562224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_INIT_R600_CP = 0x05 563224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } func; 564224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long sarea_priv_offset; 565224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int is_pci; 566224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int cp_mode; 567224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int gart_size; 568224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int ring_size; 569224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int usec_timeout; 570224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 571224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int fb_bpp; 572224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int front_offset, front_pitch; 573224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int back_offset, back_pitch; 574224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_bpp; 575224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_offset, depth_pitch; 576224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 577224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long fb_offset; 578224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long mmio_offset; 579224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long ring_offset; 580224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long ring_rptr_offset; 581224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long buffers_offset; 582224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned long gart_textures_offset; 583224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_init_t; 584224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 585224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_cp_stop { 586224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int flush; 587224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int idle; 588224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_cp_stop_t; 589224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 590224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_fullscreen { 591224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng enum { 592224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_INIT_FULLSCREEN = 0x01, 593224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng RADEON_CLEANUP_FULLSCREEN = 0x02 594224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng } func; 595224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_fullscreen_t; 596224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 597224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define CLEAR_X1 0 598224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define CLEAR_Y1 1 599224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define CLEAR_X2 2 600224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define CLEAR_Y2 3 601224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define CLEAR_DEPTH 4 602224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 603224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef union drm_radeon_clear_rect { 604224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng float f[5]; 605224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int ui[5]; 606224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_clear_rect_t; 607224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 608224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_clear { 609224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int flags; 610224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int clear_color; 611224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int clear_depth; 612224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int color_mask; 613224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int depth_mask; /* misnamed field: should be stencil */ 614224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_clear_rect_t __user *depth_boxes; 615224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_clear_t; 616224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 617224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_vertex { 618224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int prim; 619224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int idx; /* Index of vertex buffer */ 620224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int count; /* Number of vertices in buffer */ 621224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int discard; /* Client finished with buffer? */ 622224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_vertex_t; 623224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 624224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_indices { 625224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int prim; 626224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int idx; 627224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; 628224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int end; 629224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int discard; /* Client finished with buffer? */ 630224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_indices_t; 631224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 632224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices 633224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - allows multiple primitives and state changes in a single ioctl 634224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - supports driver change to emit native primitives 635224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 636224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_vertex2 { 637224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int idx; /* Index of vertex buffer */ 638224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int discard; /* Client finished with buffer? */ 639224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int nr_states; 640224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_state_t __user *state; 641224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int nr_prims; 642224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_prim_t __user *prim; 643224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_vertex2_t; 644224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 645224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* v1.3 - obsoletes drm_radeon_vertex2 646224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - allows arbitrarily large cliprect list 647224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - allows updating of tcl packet, vector and scalar state 648224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - allows memory-efficient description of state updates 649224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - allows state to be emitted without a primitive 650224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * (for clears, ctx switches) 651224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - allows more than one dma buffer to be referenced per ioctl 652224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - supports tcl driver 653224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * - may be extended in future versions with new cmd types, packets 654224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 655224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_cmd_buffer { 656224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int bufsz; 657224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng char __user *buf; 658224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int nbox; 659224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng struct drm_clip_rect __user *boxes; 660224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_cmd_buffer_t; 661224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 662224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_tex_image { 663224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int x, y; /* Blit coordinates */ 664224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int width, height; 665224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng const void __user *data; 666224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_tex_image_t; 667224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 668224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_texture { 669224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int offset; 670224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int pitch; 671224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int format; 672224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int width; /* Texture image coordinates */ 673224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int height; 674224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng drm_radeon_tex_image_t __user *image; 675224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_texture_t; 676224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 677224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_stipple { 678224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int __user *mask; 679224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_stipple_t; 680224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 681224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_indirect { 682224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int idx; 683224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; 684224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int end; 685224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int discard; 686224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_indirect_t; 687224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 688224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* enum for card type parameters */ 689224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CARD_PCI 0 690224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CARD_AGP 1 691224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CARD_PCIE 2 692224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 693224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1.3: An ioctl to get parameters that aren't available to the 3d 694224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * client any other way. 695224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 696224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ 697224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_LAST_FRAME 2 698224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_LAST_DISPATCH 3 699224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_LAST_CLEAR 4 700224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Added with DRM version 1.6. */ 701224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_IRQ_NR 5 702224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ 703224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Added with DRM version 1.8. */ 704224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 705224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_STATUS_HANDLE 8 706224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_SAREA_HANDLE 9 707224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_GART_TEX_HANDLE 10 708224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_SCRATCH_OFFSET 11 709224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_CARD_TYPE 12 710224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 711224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 712224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 713224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_DEVICE_ID 16 714224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ 715224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 716224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_getparam { 717224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int param; 718224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng void __user *value; 719224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_getparam_t; 720224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 721224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1.6: Set up a memory manager for regions of shared memory: 722224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 723224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_MEM_REGION_GART 1 724224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_MEM_REGION_FB 2 725224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 726224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_mem_alloc { 727224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 728224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int alignment; 729224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 730224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *region_offset; /* offset from start of fb or GART */ 731224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_mem_alloc_t; 732224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 733224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_mem_free { 734224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 735224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region_offset; 736224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_mem_free_t; 737224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 738224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_mem_init_heap { 739224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int region; 740224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int size; 741224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int start; 742224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_mem_init_heap_t; 743224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 744224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1.6: Userspace can request & wait on irq's: 745224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 746224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_irq_emit { 747224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int __user *irq_seq; 748224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_irq_emit_t; 749224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 750224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_irq_wait { 751224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng int irq_seq; 752224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_irq_wait_t; 753224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 754224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1.10: Clients tell the DRM where they think the framebuffer is located in 755224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the card's address space, via a new generic ioctl to set parameters 756224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 757224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 758224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_setparam { 759224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int param; 760224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng __s64 value; 761224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_setparam_t; 762224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 763224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ 764224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ 765224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ 766224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ 767224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ 768224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ 769224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 1.14: Clients can allocate/free a surface 770224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 771224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_surface_alloc { 772224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int address; 773224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int size; 774224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int flags; 775224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_surface_alloc_t; 776224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 777224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengtypedef struct drm_radeon_surface_free { 778224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng unsigned int address; 779224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng} drm_radeon_surface_free_t; 780224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 781224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_VBLANK_CRTC1 1 782224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define DRM_RADEON_VBLANK_CRTC2 2 783224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 784224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 785224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Kernel modesetting world below. 786224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 787224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_GEM_DOMAIN_CPU 0x1 788224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_GEM_DOMAIN_GTT 0x2 789224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_GEM_DOMAIN_VRAM 0x4 790224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 791224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_info { 792224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t gart_size; 793224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t vram_size; 794224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t vram_visible; 795224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 796224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 797224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_GEM_NO_BACKING_STORE 1 798224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 799224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_create { 800224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t size; 801224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t alignment; 802224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 803224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t initial_domain; 804224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t flags; 805224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 806224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 807224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_MACRO 0x1 808224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_MICRO 0x2 809224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_SWAP_16BIT 0x4 810224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_SWAP_32BIT 0x8 811224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* this object requires a surface when mapped - i.e. front buffer */ 812224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_SURFACE 0x10 813224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_MICRO_SQUARE 0x20 814224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_BANKW_SHIFT 8 815224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_BANKW_MASK 0xf 816224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_BANKH_SHIFT 12 817224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_BANKH_MASK 0xf 818224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 819224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 820224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 821224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 822224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 823224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 824224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 825224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_set_tiling { 826224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 827224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t tiling_flags; 828224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pitch; 829224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 830224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 831224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_get_tiling { 832224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 833224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t tiling_flags; 834224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pitch; 835224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 836224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 837224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_mmap { 838224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 839224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pad; 840224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t offset; 841224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t size; 842224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t addr_ptr; 843224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 844224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 845224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_set_domain { 846224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 847224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t read_domains; 848224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t write_domain; 849224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 850224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 851224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_wait_idle { 852224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 853224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pad; 854224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 855224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 856224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_busy { 857224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 858224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t domain; 859224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 860224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 861224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_pread { 862224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being read. */ 863224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 864224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pad; 865224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to read from */ 866224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t offset; 867224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to read */ 868224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t size; 869224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Pointer to write the data into. */ 870224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* void *, but pointers are not 32/64 compatible */ 871224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t data_ptr; 872224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 873224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 874224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_pwrite { 875224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Handle for the object being written to. */ 876224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 877224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pad; 878224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Offset into the object to write to */ 879224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t offset; 880224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Length of data to write */ 881224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t size; 882224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /** Pointer to read the data from. */ 883224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* void *, but pointers are not 32/64 compatible */ 884224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t data_ptr; 885224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 886224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 887224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VA_MAP 1 888224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VA_UNMAP 2 889224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 890224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VA_RESULT_OK 0 891224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VA_RESULT_ERROR 1 892224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VA_RESULT_VA_EXIST 2 893224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 894224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VM_PAGE_VALID (1 << 0) 895224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VM_PAGE_READABLE (1 << 1) 896224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VM_PAGE_WRITEABLE (1 << 2) 897224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VM_PAGE_SYSTEM (1 << 3) 898224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_VM_PAGE_SNOOPED (1 << 4) 899224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 900224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_gem_va { 901224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 902224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t operation; 903224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t vm_id; 904224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t flags; 905224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t offset; 906224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 907224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 908224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CHUNK_ID_RELOCS 0x01 909224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CHUNK_ID_IB 0x02 910224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CHUNK_ID_FLAGS 0x03 911224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CHUNK_ID_CONST_IB 0x04 912224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 913224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ 914224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_KEEP_TILING_FLAGS 0x01 915224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_USE_VM 0x02 916224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_END_OF_FRAME 0x04 /* a hint from userspace which CS is the last one */ 917224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */ 918224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_RING_GFX 0 919224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_RING_COMPUTE 1 920224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_RING_DMA 2 921224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_CS_RING_UVD 3 922224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */ 923224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0 = normal, + = higher priority, - = lower priority */ 924224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 925224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_cs_chunk { 926224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t chunk_id; 927224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t length_dw; 928224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t chunk_data; 929224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 930224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 931224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* drm_radeon_cs_reloc.flags */ 932224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 933224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_cs_reloc { 934224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t handle; 935224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t read_domains; 936224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t write_domain; 937224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t flags; 938224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 939224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 940224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_cs { 941224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t num_chunks; 942224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t cs_id; 943224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* this points to uint64_t * which point to cs chunks */ 944224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t chunks; 945224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* updates to the limits after this CS ioctl */ 946224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t gart_limit; 947224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t vram_limit; 948224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 949224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 950224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_DEVICE_ID 0x00 951224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_NUM_GB_PIPES 0x01 952224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_NUM_Z_PIPES 0x02 953224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_ACCEL_WORKING 0x03 954224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_CRTC_FROM_ID 0x04 955224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_ACCEL_WORKING2 0x05 956224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_TILING_CONFIG 0x06 957224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_WANT_HYPERZ 0x07 958224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_WANT_CMASK 0x08 /* get access to CMASK on r300 */ 959224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 960224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 961224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 962224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ 963224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ 964224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* virtual address start, va < start are reserved by the kernel */ 965224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_VA_START 0x0e 966224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* maximum size of ib using the virtual memory cs */ 967224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 968224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* max pipes - needed for compute shaders */ 969224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_MAX_PIPES 0x10 970224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ 971224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_TIMESTAMP 0x11 972224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* max shader engines (SE) - needed for geometry shaders, etc. */ 973224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_MAX_SE 0x12 974224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* max SH per SE */ 975224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_MAX_SH_PER_SE 0x13 976224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* fast fb access is enabled */ 977224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_FASTFB_WORKING 0x14 978224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* query if a RADEON_CS_RING_* submission is supported */ 979224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_RING_WORKING 0x15 980224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* SI tile mode array */ 981224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 982e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* query if CP DMA is supported on the compute ring */ 983e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 984e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* CIK macrotile mode array */ 985e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 986e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* query the number of render backends */ 987e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 988e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* max engine clock - needed for OpenCL */ 989e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define RADEON_INFO_MAX_SCLK 0x1a 990224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 991224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 992224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Chengstruct drm_radeon_info { 993224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t request; 994224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint32_t pad; 995224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng uint64_t value; 996224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng}; 997224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 998224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Those correspond to the tile index to use, this is to explicitly state 999224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * the API that is implicitly defined by the tile mode array. 1000224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 1001224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 1002224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_1D 13 1003224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_1D_SCANOUT 9 1004224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_2D_8BPP 14 1005224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_2D_16BPP 15 1006224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_2D_32BPP 16 1007224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_2D_64BPP 17 1008224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 1009224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 1010224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_1D 4 1011224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_2D 0 1012224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 1013224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 1014224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 1015224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 1016e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 1017e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl 1018224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#endif 1019