1224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 2224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * pci_regs.h 3224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 4224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * PCI standard defines 5224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 1994, Drew Eckhardt 6224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 7224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 8224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * For more information, please consult the following manuals (look at 9224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * http://www.pcisig.com/ for how to get them): 10224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 11224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * PCI BIOS Specification 12224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * PCI Local Bus Specification 13224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * PCI to PCI Bridge Specification 14224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * PCI System Design Guide 15224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 16e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * For HyperTransport information, please consult the following manuals 17e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * from http://www.hypertransport.org 18224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 19e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * The HyperTransport I/O Link Specification 20224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 21224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 22224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#ifndef LINUX_PCI_REGS_H 23224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define LINUX_PCI_REGS_H 24224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 25224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 26224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Under PCI, each device has 256 bytes of configuration address space, 27224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * of which the first 64 bytes are standardized as follows: 28224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 29224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STD_HEADER_SIZEOF 64 30224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VENDOR_ID 0x00 /* 16 bits */ 31224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_DEVICE_ID 0x02 /* 16 bits */ 32224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND 0x04 /* 16 bits */ 33224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 34224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 35224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 36224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 37224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 38224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 39224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 40e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 41224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 42224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 43224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ 44224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 45224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS 0x06 /* 16 bits */ 46224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ 47224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 48e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_STATUS_66MHZ 0x20 /* Support 66 MHz PCI 2.1 bus */ 49224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 50224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 51224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 52224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 53224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_DEVSEL_FAST 0x000 54224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_DEVSEL_MEDIUM 0x200 55224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_DEVSEL_SLOW 0x400 56224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 57224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 58224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 59224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 60224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 61224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 62224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ 63224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_REVISION_ID 0x08 /* Revision ID */ 64224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 65224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CLASS_DEVICE 0x0a /* Device class */ 66224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 67224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 68224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 69224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_HEADER_TYPE 0x0e /* 8 bits */ 70224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_HEADER_TYPE_NORMAL 0 71224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_HEADER_TYPE_BRIDGE 1 72224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_HEADER_TYPE_CARDBUS 2 73224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 74224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BIST 0x0f /* 8 bits */ 75224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BIST_CODE_MASK 0x0f /* Return result */ 76224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 77224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 78224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 79224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 80224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Base addresses specify locations in memory or I/O space. 81224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Decoded size can be determined by writing a value of 82224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 0xffffffff to the register, and reading it back. Only 83224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 1 bits are decoded. 84224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 85224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 86224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 87224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 88224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 89224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 90224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 91224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 92224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_SPACE_IO 0x01 93224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 94224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 95224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 96224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 97224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 98224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 99224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 100224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 101224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* bit 1 is reserved if address_space = 1 */ 102224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 103224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Header type 0 (normal devices) */ 104224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CARDBUS_CIS 0x28 105224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 106224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SUBSYSTEM_ID 0x2e 107224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 108224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ROM_ADDRESS_ENABLE 0x01 109224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 110224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 111224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 112224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 113224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x35-0x3b are reserved */ 114224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 115224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 116224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MIN_GNT 0x3e /* 8 bits */ 117224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MAX_LAT 0x3f /* 8 bits */ 118224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 119224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Header type 1 (PCI-to-PCI bridges) */ 120224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 121224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 122224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 123224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 124224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 125224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_LIMIT 0x1d 126224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 127224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_RANGE_TYPE_16 0x00 128224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_RANGE_TYPE_32 0x01 129224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ 130224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ 131224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 132224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 133224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MEMORY_LIMIT 0x22 134224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 135224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 136224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 137224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_MEMORY_LIMIT 0x26 138224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 139224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_RANGE_TYPE_32 0x00 140224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_RANGE_TYPE_64 0x01 141224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_RANGE_MASK (~0x0fUL) 142224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 143224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PREF_LIMIT_UPPER32 0x2c 144224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 145224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_IO_LIMIT_UPPER16 0x32 146224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x34 same as for htype 0 */ 147224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x35-0x3b is reserved */ 148224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 149224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x3c-0x3d are same as for htype 0 */ 150224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CONTROL 0x3e 151224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 152224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 153224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ 154224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 155224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 156224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 157224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 158224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 159224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Header type 2 (CardBus bridges) */ 160224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_CAPABILITY_LIST 0x14 161224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x15 reserved */ 162224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 163224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 164224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 165224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 166224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 167224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_MEMORY_BASE_0 0x1c 168224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_MEMORY_LIMIT_0 0x20 169224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_MEMORY_BASE_1 0x24 170224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_MEMORY_LIMIT_1 0x28 171224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_BASE_0 0x2c 172224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_BASE_0_HI 0x2e 173224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_LIMIT_0 0x30 174224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_LIMIT_0_HI 0x32 175224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_BASE_1 0x34 176224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_BASE_1_HI 0x36 177224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_LIMIT_1 0x38 178224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_LIMIT_1_HI 0x3a 179224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_IO_RANGE_MASK (~0x03UL) 180224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x3c-0x3d are same as for htype 0 */ 181224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CONTROL 0x3e 182224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 183224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_SERR 0x02 184224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_ISA 0x04 185224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_VGA 0x08 186224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 187224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 188224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 189224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 190224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 191224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 192224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 193224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_SUBSYSTEM_ID 0x42 194224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 195224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 0x48-0x7f reserved */ 196224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 197224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Capability lists */ 198224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 199224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_LIST_ID 0 /* Capability ID */ 200224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_PM 0x01 /* Power Management */ 201224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 202224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 203224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 204224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 205224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 206224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 207224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 208e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 209224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_DBG 0x0A /* Debug port */ 210224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 211e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 212224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 213224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 214224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 215e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 216224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 217224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 218224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 219224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_ID_MAX PCI_CAP_ID_AF 220224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 221224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 222224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_SIZEOF 4 223224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 224224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Power Management Registers */ 225224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 226224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_PMC 2 /* PM Capabilities Register */ 227224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 228224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 229224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 230224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 231224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxiliary power support mask */ 232224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 233224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 234224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 235224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 236224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 237224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 238224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 239224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 240224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 241224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ 242224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL 4 /* PM control and status register */ 243224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 244224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ 245224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 246224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 247224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 248224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 249224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 250224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 251224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 252224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_DATA_REGISTER 7 /* (??) */ 253224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PM_SIZEOF 8 254224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 255224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* AGP registers */ 256224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 257224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_VERSION 2 /* BCD version number */ 258224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_RFU 3 /* Rest of capability flags */ 259224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS 4 /* Status register */ 260224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 261224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 262224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 263224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 264224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 265224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 266224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 267224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND 8 /* Control register */ 268224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 269224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 270224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 271e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 272e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 273224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 274224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 275224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 276224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AGP_SIZEOF 12 277224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 278224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Vital Product Data */ 279224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 280224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */ 281224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ 282224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ 283224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ 284224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_VPD_SIZEOF 8 285224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 286224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Slot Identification */ 287224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 288224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SID_ESR 2 /* Expansion Slot Register */ 289224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 290224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 291224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 292224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 293224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Message Signalled Interrupts registers */ 294224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 295224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_FLAGS 2 /* Message Control */ 296224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ 297224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_FLAGS_QMASK 0x000e /* Maximum queue size available */ 298224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_FLAGS_QSIZE 0x0070 /* Message queue size configured */ 299224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_FLAGS_64BIT 0x0080 /* 64-bit addresses allowed */ 300224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */ 301224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_RFU 3 /* Rest of capability flags */ 302224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 303224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 304224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 305224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ 306224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ 307224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 308224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ 309224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ 310224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 311224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* MSI-X registers */ 312224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_FLAGS 2 /* Message Control */ 313224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ 314224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ 315224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */ 316224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_TABLE 4 /* Table offset */ 317224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_TABLE_BIR 0x00000007 /* BAR index */ 318224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* Offset into specified BAR */ 319224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */ 320224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_PBA_BIR 0x00000007 /* BAR index */ 321224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_PBA_OFFSET 0xfffffff8 /* Offset into specified BAR */ 322224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ 323224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 324e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* MSI-X Table entry format */ 325224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_ENTRY_SIZE 16 326224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_ENTRY_LOWER_ADDR 0 327224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_ENTRY_UPPER_ADDR 4 328224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_ENTRY_DATA 8 329224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 330224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 331224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 332224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* CompactPCI Hotswap Register */ 333224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 334224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_CSR 2 /* Control and Status Register */ 335224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */ 336224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */ 337224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */ 338224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_LOO 0x08 /* LED On / Off */ 339224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_PI 0x30 /* Programming Interface */ 340224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */ 341224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */ 342224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 343224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* PCI Advanced Feature registers */ 344224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 345224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_LENGTH 2 346224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_CAP 3 347224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_CAP_TP 0x01 348224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_CAP_FLR 0x02 349224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_CTRL 4 350224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_CTRL_FLR 0x01 351224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_STATUS 5 352224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_AF_STATUS_TP 0x01 353224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ 354224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 355224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* PCI-X registers (Type 0 (non-bridge) devices) */ 356224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 357224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD 2 /* Modes & Features */ 358224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 359224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 360224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */ 361224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */ 362224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */ 363224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */ 364224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */ 365224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Max # of outstanding split transactions */ 366224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */ 367224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */ 368224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */ 369224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */ 370224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */ 371224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */ 372224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */ 373224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */ 374224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */ 375e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 376224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS 4 /* PCI-X capabilities */ 377224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */ 378224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */ 379224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */ 380224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */ 381224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */ 382224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */ 383224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */ 384224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */ 385224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */ 386224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */ 387224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ 388224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ 389224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ 390224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_ECC_CSR 8 /* ECC control and status */ 391224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ 392224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ 393224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ 394224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 395224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* PCI-X registers (Type 1 (bridge) devices) */ 396224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 397224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_BRIDGE_SSTATUS 2 /* Secondary Status */ 398224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_64BIT 0x0001 /* Secondary AD interface is 64 bits */ 399224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_133MHZ 0x0002 /* 133 MHz capable */ 400224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_FREQ 0x03c0 /* Secondary Bus Mode and Frequency */ 401224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_VERS 0x3000 /* PCI-X Capability Version */ 402224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_V1 0x1000 /* Mode 2, not Mode 1 */ 403224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_V2 0x2000 /* Mode 1 or Modes 1 and 2 */ 404224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_266MHZ 0x4000 /* 266 MHz capable */ 405224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_SSTATUS_533MHZ 0x8000 /* 533 MHz capable */ 406224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_X_BRIDGE_STATUS 4 /* Bridge Status */ 407224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 408224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* PCI Bridge Subsystem ID registers */ 409224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 410e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_SSVID_VENDOR_ID 4 /* PCI Bridge subsystem vendor ID */ 411e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_SSVID_DEVICE_ID 6 /* PCI Bridge subsystem device ID */ 412224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 413224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* PCI Express capability registers */ 414224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 415224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_FLAGS 2 /* Capabilities register */ 416224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ 417224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ 418224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ 419224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ 420224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ 421224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ 422224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ 423e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ 424e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ 425224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ 426224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ 427224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ 428224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ 429224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCAP 4 /* Device capabilities */ 430e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ 431e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ 432e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 /* Extended tags */ 433e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */ 434e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_L1 0x00000e00 /* L1 Acceptable Latency */ 435e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 /* Attention Button Present */ 436e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_ATN_IND 0x00002000 /* Attention Indicator Present */ 437e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_PWR_IND 0x00004000 /* Power Indicator Present */ 438e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_RBER 0x00008000 /* Role-Based Error Reporting */ 439e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 /* Slot Power Limit Value */ 440e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 /* Slot Power Limit Scale */ 441224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */ 442224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL 8 /* Device Control */ 443224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */ 444224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ 445224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ 446224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ 447224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 448224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ 449224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ 450224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ 451224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ 452224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */ 453224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ 454224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */ 455224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVSTA 10 /* Device Status */ 456e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA_CED 0x0001 /* Correctable Error Detected */ 457e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA_NFED 0x0002 /* Non-Fatal Error Detected */ 458e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA_FED 0x0004 /* Fatal Error Detected */ 459e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */ 460e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */ 461e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */ 462224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP 12 /* Link Capabilities */ 463224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */ 464e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */ 465e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ 466224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ 467224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 468224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ 469224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ 470e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */ 471224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ 472224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 473224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ 474224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */ 475224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL 16 /* Link Control */ 476224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */ 477e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */ 478e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCTL_ASPM_L1 0x0002 /* L1 Enable */ 479224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ 480224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */ 481224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ 482224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */ 483224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */ 484e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 /* Enable clkreq */ 485224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */ 486224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */ 487e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Link Autonomous Bandwidth Interrupt Enable */ 488224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA 18 /* Link Status */ 489224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 490e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 491e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 492e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 493e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ 494e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ 495e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ 496e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ 497e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */ 498224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */ 499224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */ 500224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ 501224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ 502224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ 503224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ 504224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */ 505224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ 506224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ 507224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ 508224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */ 509224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */ 510224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */ 511224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */ 512224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ 513224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */ 514224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */ 515224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */ 516224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */ 517224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ 518224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL 24 /* Slot Control */ 519224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */ 520224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */ 521224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */ 522224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */ 523224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */ 524224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ 525224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */ 526e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 /* Attention Indicator on */ 527e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */ 528e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 /* Attention Indicator off */ 529224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */ 530e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 /* Power Indicator on */ 531e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 /* Power Indicator blinking */ 532e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 /* Power Indicator off */ 533224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */ 534e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_PWR_ON 0x0000 /* Power On */ 535e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */ 536224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */ 537224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */ 538224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA 26 /* Slot Status */ 539224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */ 540224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */ 541224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */ 542224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */ 543224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */ 544224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */ 545224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */ 546224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */ 547224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */ 548224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_RTCTL 28 /* Root Control */ 549e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ 550e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error */ 551e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ 552e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ 553e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ 554224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_RTCAP 30 /* Root Capabilities */ 555224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_RTSTA 32 /* Root Status */ 556e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ 557e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ 558224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 559e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * The Device Capabilities 2, Device Status 2, Device Control 2, 560e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * Link Capabilities 2, Link Status 2, Link Control 2, 561e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * Slot Capabilities 2, Slot Status 2, and Slot Control 2 registers 562e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * are only present on devices with PCIe Capability version 2. 563e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * Use pcie_capability_read_word() and similar interfaces to use them 564e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * safely. 565224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 566224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ 567e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ 568e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ 569e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ 570e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 571e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 572224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 573e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ 574e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 575e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ 576e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ 577e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ 578e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */ 579e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */ 580e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ 581e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */ 582224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ 583e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */ 584e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */ 585e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */ 586e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */ 587e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ 588224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ 589224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ 590e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ 591224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ 592e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ 593224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 594224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Extended Capabilities (PCI-X 2.0 and Express) */ 595224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 596224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 597224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 598224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 599224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 600224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 601224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 602224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 603224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 604224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 605224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 606224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 607224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 608224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 609e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 610224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 611224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 612224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 613224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 614224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 615224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 616224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 617224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 618e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 619e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 620e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 621e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 622e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 623e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 624224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 625224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 626224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID 627224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 628224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_DSN_SIZEOF 12 629224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 630224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 631224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Advanced Error Reporting */ 632224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 633224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 634224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 635224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ 636224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 637224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ 638224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ 639224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */ 640224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ 641224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */ 642224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ 643224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ 644224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ 645224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ 646224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ 647224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ 648224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ 649224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ 650224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ 651224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Same bits as above */ 652224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ 653224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Same bits as above */ 654224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */ 655224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */ 656224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */ 657224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ 658224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ 659224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ 660224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ 661224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ 662224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ 663224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ 664224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng /* Same bits as above */ 665224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ 666224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */ 667224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */ 668224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */ 669224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */ 670224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ 671224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ 672224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ 673224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Correctable Err Reporting Enable */ 674224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 675224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Non-fatal Err Reporting Enable */ 676224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 677224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Fatal Err Reporting Enable */ 678224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 679224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_STATUS 48 680224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ 681224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Multi ERR_COR Received */ 682224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 683e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* ERR_FATAL/NONFATAL Received */ 684224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 685e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* Multi ERR_FATAL/NONFATAL Received */ 686224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 687224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */ 688224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ 689224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ 690224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ 691224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 692224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Virtual Channel */ 693e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_PORT_CAP1 4 694e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ 695e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP1_LPEVCC 0x00000070 /* low prio extended VC count */ 696e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP1_ARB_SIZE 0x00000c00 697e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_PORT_CAP2 8 698e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP2_32_PHASE 0x00000002 699e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP2_64_PHASE 0x00000004 700e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP2_128_PHASE 0x00000008 701e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_CAP2_ARB_OFF 0xff000000 702224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VC_PORT_CTRL 12 703e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 704224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VC_PORT_STATUS 14 705e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_PORT_STATUS_TABLE 0x00000001 706224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VC_RES_CAP 16 707e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CAP_32_PHASE 0x00000002 708e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CAP_64_PHASE 0x00000004 709e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CAP_128_PHASE 0x00000008 710e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 711e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CAP_256_PHASE 0x00000020 712e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CAP_ARB_OFF 0xff000000 713224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VC_RES_CTRL 20 714e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 715e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 716e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CTRL_ID 0x07000000 717e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_CTRL_ENABLE 0x80000000 718224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VC_RES_STATUS 26 719e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_STATUS_TABLE 0x00000001 720e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VC_RES_STATUS_NEGO 0x00000002 721224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_VC_BASE_SIZEOF 0x10 722224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 723224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 724224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Power Budgeting */ 725224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DSR 4 /* Data Select Register */ 726224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA 8 /* Data Register */ 727224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ 728224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ 729224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ 730224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ 731224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ 732224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ 733224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_CAP 12 /* Capability */ 734224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ 735224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_PWR_SIZEOF 16 736224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 737224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ 738224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ 739224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 740224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 741224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 742224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 743224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* 744e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl * HyperTransport sub capability types 745224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * 746224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * Unfortunately there are both 3 bit and 5 bit capability types defined 747224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * in the HT spec, catering for that is a little messy. You probably don't 748224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * want to use these directly, just use pci_find_ht_capability() and it 749224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng * will do the right thing for you. 750224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng */ 751224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_3BIT_CAP_MASK 0xE0 752224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */ 753224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */ 754224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 755224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_5BIT_CAP_MASK 0xF8 756224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */ 757224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */ 758224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */ 759224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */ 760224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */ 761224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */ 762224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_FLAGS 0x02 /* Offset to flags */ 763224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */ 764224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */ 765224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */ 766224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */ 767224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */ 768224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */ 769224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */ 770224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */ 771224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ 772e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 HyperTransport configuration */ 773e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define HT_CAPTYPE_PM 0xE0 /* HyperTransport power management configuration */ 774224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ 775224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ 776224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 777224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Alternative Routing-ID Interpretation */ 778224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ 779224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */ 780224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ 781224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ 782224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ 783224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ 784224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ 785224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ 786224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ARI_SIZEOF 8 787224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 788224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Address Translation Service */ 789224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ 790224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ 791224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ 792224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_CTRL 0x06 /* ATS Control Register */ 793224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ 794224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ 795224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ 796224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_ATS_SIZEOF 8 797224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 798224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Page Request Interface */ 799224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_CTRL 0x04 /* PRI control register */ 800224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ 801224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ 802224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_STATUS 0x06 /* PRI status register */ 803224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ 804224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ 805224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ 806224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ 807224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ 808224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_PRI_SIZEOF 16 809224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 810e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* Process Address Space ID */ 811224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PASID_CAP 0x04 /* PASID feature register */ 812224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ 813e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ 814224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PASID_CTRL 0x06 /* PASID control register */ 815224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ 816224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ 817e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ 818224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_PASID_SIZEOF 8 819224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 820224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Single Root I/O Virtualization */ 821224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 822224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 823224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 824224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 825224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 826224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 827224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 828224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 829224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 830224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 831224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 832224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 833224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 834224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 835224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 836224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 837224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 838224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 839224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 840224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 841224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */ 842224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */ 843224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/ 844224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */ 845224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */ 846224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */ 847224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ 848224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ 849224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ 850224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_SRIOV_SIZEOF 64 851224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 852224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_LTR_MAX_SNOOP_LAT 0x4 853224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 854224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_LTR_VALUE_MASK 0x000003ff 855224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_LTR_SCALE_MASK 0x00001c00 856224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_LTR_SCALE_SHIFT 10 857224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_EXT_CAP_LTR_SIZEOF 8 858224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 859224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* Access Control Service */ 860224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ 861224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_SV 0x01 /* Source Validation */ 862224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_TB 0x02 /* Translation Blocking */ 863224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_RR 0x04 /* P2P Request Redirect */ 864224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ 865224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ 866224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_EC 0x20 /* P2P Egress Control */ 867224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ 868224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ 869224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ 870224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ 871224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 872e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl#define PCI_VSEC_HDR 4 /* extended cap - vendor-specific */ 873224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ 874224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 875e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* SATA capability */ 876224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SATA_REGS 4 /* SATA REGs specifier */ 877224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ 878224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ 879224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SATA_SIZEOF_SHORT 8 880224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_SATA_SIZEOF_LONG 16 881224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 882e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* Resizable BARs */ 883224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_REBAR_CTRL 8 /* control register */ 884224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ 885224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ 886224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 887e87eaf040ab639e94ed0a58ff0eac68d1d38fb0aEd Heyl/* Dynamic Power Allocation */ 888224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_DPA_CAP 4 /* capability register */ 889224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ 890224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ 891224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 892224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng/* TPH Requester */ 893224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_CAP 4 /* capability register */ 894224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ 895224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_LOC_NONE 0x000 /* no location */ 896224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_LOC_CAP 0x200 /* in capability */ 897224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ 898224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ 899224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ 900224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */ 901224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng 902224b54f69543a5c0ec18f99bd717d2b724582eb6Ben Cheng#endif /* LINUX_PCI_REGS_H */ 903