130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * SyncLink Multiprotocol Serial Adapter Driver 330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $ 530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Copyright (C) 1998-2000 by Microgate Corporation 730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Redistribution of this file is permitted under 930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * the terms of the GNU Public License (GPL) 1030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 1130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 1230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#ifndef _UAPI_SYNCLINK_H_ 1330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define _UAPI_SYNCLINK_H_ 1430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_H_VERSION 3.6 1530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 1630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#include <linux/types.h> 1730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 1830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT0 0x0001 1930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT1 0x0002 2030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT2 0x0004 2130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT3 0x0008 2230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT4 0x0010 2330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT5 0x0020 2430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT6 0x0040 2530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT7 0x0080 2630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT8 0x0100 2730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT9 0x0200 2830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT10 0x0400 2930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT11 0x0800 3030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT12 0x1000 3130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT13 0x2000 3230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT14 0x4000 3330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT15 0x8000 3430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT16 0x00010000 3530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT17 0x00020000 3630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT18 0x00040000 3730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT19 0x00080000 3830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT20 0x00100000 3930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT21 0x00200000 4030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT22 0x00400000 4130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT23 0x00800000 4230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT24 0x01000000 4330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT25 0x02000000 4430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT26 0x04000000 4530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT27 0x08000000 4630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT28 0x10000000 4730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT29 0x20000000 4830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT30 0x40000000 4930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define BIT31 0x80000000 5030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 5130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 5230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_MAX_FRAME_SIZE 65535 5330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MAX_ASYNC_TRANSMIT 4096 5430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MAX_ASYNC_BUFFER_SIZE 4096 5530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 5630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define ASYNC_PARITY_NONE 0 5730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define ASYNC_PARITY_EVEN 1 5830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define ASYNC_PARITY_ODD 2 5930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define ASYNC_PARITY_SPACE 3 6030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 6130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 6230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 6330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_UNDERRUN_FLAG 0x0002 6430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_UNDERRUN_CRC 0x0004 6530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_SHARE_ZERO 0x0010 6630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_AUTO_CTS 0x0020 6730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_AUTO_DCD 0x0040 6830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_AUTO_RTS 0x0080 6930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_RXC_DPLL 0x0100 7030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_RXC_BRG 0x0200 7130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_RXC_TXCPIN 0x8000 7230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_RXC_RXCPIN 0x0000 7330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_TXC_DPLL 0x0400 7430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_TXC_BRG 0x0800 7530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_TXC_TXCPIN 0x0000 7630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_TXC_RXCPIN 0x0008 7730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_DPLL_DIV8 0x1000 7830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_DPLL_DIV16 0x2000 7930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_DPLL_DIV32 0x0000 8030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_FLAG_HDLC_LOOPMODE 0x4000 8130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 8230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_CRC_NONE 0 8330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_CRC_16_CCITT 1 8430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_CRC_32_CCITT 2 8530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_CRC_MASK 0x00ff 8630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_CRC_RETURN_EX 0x8000 8730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 8830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define RX_OK 0 8930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define RX_CRC_ERROR 1 9030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 9130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_FLAGS 0 9230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_ALT_ZEROS_ONES 1 9330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_ZEROS 2 9430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_ONES 3 9530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_ALT_MARK_SPACE 4 9630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_SPACE 5 9730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_MARK 6 9830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_CUSTOM_8 0x10000000 9930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_TXIDLE_CUSTOM_16 0x20000000 10030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 10130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_NRZ 0 10230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_NRZB 1 10330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_NRZI_MARK 2 10430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_NRZI_SPACE 3 10530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE 10630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_BIPHASE_MARK 4 10730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_BIPHASE_SPACE 5 10830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_BIPHASE_LEVEL 6 10930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 11030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 11130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_LENGTH_8BITS 0 11230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_LENGTH_16BITS 1 11330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_LENGTH_32BITS 2 11430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_LENGTH_64BITS 3 11530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 11630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_PATTERN_NONE 0 11730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_PATTERN_ZEROS 1 11830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_PATTERN_FLAGS 2 11930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_PATTERN_10 3 12030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_PATTERN_01 4 12130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define HDLC_PREAMBLE_PATTERN_ONES 5 12230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 12330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_ASYNC 1 12430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_HDLC 2 12530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_MONOSYNC 3 12630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_BISYNC 4 12730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_RAW 6 12830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_BASE_CLOCK 7 12930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MODE_XSYNC 8 13030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 13130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_BUS_TYPE_ISA 1 13230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_BUS_TYPE_EISA 2 13330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_BUS_TYPE_PCI 5 13430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 13530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_MASK 0xf 13630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_DISABLE 0 13730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_RS232 1 13830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_V35 2 13930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_RS422 3 14030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_RTS_EN 0x10 14130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_LL 0x20 14230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_RL 0x40 14330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_INTERFACE_MSB_FIRST 0x80 14430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 14530692c65c4174412c90e79489e98ab85c1a7412fBen Chengtypedef struct _MGSL_PARAMS 14630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng{ 14730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Common */ 14830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 14930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long mode; /* Asynchronous or HDLC */ 15030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char loopback; /* internal loopback mode */ 15130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 15230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* HDLC Only */ 15330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 15430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned short flags; 15530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char encoding; /* NRZ, NRZI, etc. */ 15630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long clock_speed; /* external clock speed in bits per second */ 15730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ 15830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ 15930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char preamble_length; 16030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char preamble; 16130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 16230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng /* Async Only */ 16330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 16430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned long data_rate; /* bits per second */ 16530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char data_bits; /* 7 or 8 data bits */ 16630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char stop_bits; /* 1 or 2 stop bits */ 16730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng unsigned char parity; /* none, even, or odd */ 16830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 16930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng} MGSL_PARAMS, *PMGSL_PARAMS; 17030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 17130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MICROGATE_VENDOR_ID 0x13c0 17230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_DEVICE_ID 0x0010 17330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSCC_DEVICE_ID 0x0020 17430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_SCA_DEVICE_ID 0x0030 17530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_GT_DEVICE_ID 0x0070 17630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_GT4_DEVICE_ID 0x0080 17730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_AC_DEVICE_ID 0x0090 17830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SYNCLINK_GT2_DEVICE_ID 0x00A0 17930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MAX_SERIAL_NUMBER 30 18030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 18130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 18230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng** device diagnostics status 18330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng*/ 18430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 18530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_OK 0 18630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_AddressFailure 1 18730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_AddressConflict 2 18830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_IrqFailure 3 18930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_IrqConflict 4 19030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_DmaFailure 5 19130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_DmaConflict 6 19230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_PciAdapterNotFound 7 19330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_CantAssignPciResources 8 19430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_CantAssignPciMemAddr 9 19530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_CantAssignPciIoAddr 10 19630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_CantAssignPciIrq 11 19730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DiagStatus_MemoryError 12 19830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 19930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_DCD 0x01 /* Data Carrier Detect */ 20030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_TXD 0x02 /* Transmit Data */ 20130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_RI 0x04 /* Ring Indicator */ 20230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_RXD 0x08 /* Receive Data */ 20330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_CTS 0x10 /* Clear to Send */ 20430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_RTS 0x20 /* Request to Send */ 20530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_DSR 0x40 /* Data Set Ready */ 20630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define SerialSignal_DTR 0x80 /* Data Terminal Ready */ 20730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 20830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 20930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 21030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * Counters of the input lines (CTS, DSR, RI, CD) interrupts 21130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 21230692c65c4174412c90e79489e98ab85c1a7412fBen Chengstruct mgsl_icount { 21330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 cts, dsr, rng, dcd, tx, rx; 21430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 frame, parity, overrun, brk; 21530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 buf_overrun; 21630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 txok; 21730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 txunder; 21830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 txabort; 21930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 txtimeout; 22030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxshort; 22130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxlong; 22230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxabort; 22330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxover; 22430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxcrc; 22530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxok; 22630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 exithunt; 22730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 rxidle; 22830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng}; 22930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 23030692c65c4174412c90e79489e98ab85c1a7412fBen Chengstruct gpio_desc { 23130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 state; 23230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 smask; 23330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 dir; 23430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng __u32 dmask; 23530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng}; 23630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 23730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DEBUG_LEVEL_DATA 1 23830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DEBUG_LEVEL_ERROR 2 23930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DEBUG_LEVEL_INFO 3 24030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DEBUG_LEVEL_BH 4 24130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define DEBUG_LEVEL_ISR 5 24230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 24330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* 24430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng** Event bit flags for use with MgslWaitEvent 24530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng*/ 24630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 24730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_DsrActive 0x0001 24830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_DsrInactive 0x0002 24930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_Dsr 0x0003 25030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_CtsActive 0x0004 25130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_CtsInactive 0x0008 25230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_Cts 0x000c 25330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_DcdActive 0x0010 25430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_DcdInactive 0x0020 25530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_Dcd 0x0030 25630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_RiActive 0x0040 25730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_RiInactive 0x0080 25830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_Ri 0x00c0 25930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_ExitHuntMode 0x0100 26030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MgslEvent_IdleReceived 0x0200 26130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 26230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng/* Private IOCTL codes: 26330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * 26430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCSPARAMS set MGSL_PARAMS structure values 26530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values 26630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCSTXIDLE set current transmit idle mode 26730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCGTXIDLE get current transmit idle mode 26830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCTXENABLE enable or disable transmitter 26930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCRXENABLE enable or disable receiver 27030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCTXABORT abort transmitting frame (HDLC) 27130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCGSTATS return current statistics 27230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCWAITEVENT wait for specified event to occur 27330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_LOOPTXDONE transmit in HDLC LoopMode done 27430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCSIF set the serial interface type 27530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng * MGSL_IOCGIF get the serial interface type 27630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng */ 27730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_MAGIC_IOC 'm' 27830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) 27930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) 28030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) 28130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) 28230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) 28330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) 28430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) 28530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) 28630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) 28730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) 28830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) 28930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) 29030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) 29130692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) 29230692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) 29330692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) 29430692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19) 29530692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20) 29630692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21) 29730692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22) 29830692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 29930692c65c4174412c90e79489e98ab85c1a7412fBen Cheng 30030692c65c4174412c90e79489e98ab85c1a7412fBen Cheng#endif /* _UAPI_SYNCLINK_H_ */ 301