18584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===// 28584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// 38584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// The LLVM Compiler Infrastructure 48584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// 58584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// This file is distributed under the University of Illinois Open Source 68584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// License. See LICENSE.TXT for details. 78584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// 88584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen//===----------------------------------------------------------------------===// 98584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 108584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#ifndef lldb_ARMDefines_h_ 118584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#define lldb_ARMDefines_h_ 128584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 138584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// Common defintions for the ARM/Thumb Instruction Set Architecture. 148584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 158584c92dc30415ebab70ef19a1b108137fd60944Johnny Chennamespace lldb_private { 168584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 1741a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen// ARM shifter types 1841a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chentypedef enum 1941a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen{ 2041a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen SRType_LSL, 2141a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen SRType_LSR, 2241a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen SRType_ASR, 2341a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen SRType_ROR, 24e1f47bb8c6221abf3a2fe1571b09f208d71d025eGreg Clayton SRType_RRX, 25e1f47bb8c6221abf3a2fe1571b09f208d71d025eGreg Clayton SRType_Invalid 2641a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen} ARM_ShifterType; 2741a0a15df85a0d4b428c13dff8606a064f5d8dfeJohnny Chen 284302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen// ARM conditions // Meaning (integer) Meaning (floating-point) Condition flags 294302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_EQ 0x0 // Equal Equal Z == 1 304302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_NE 0x1 // Not equal Not equal, or unordered Z == 0 314302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_CS 0x2 // Carry set >, ==, or unordered C == 1 328584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#define COND_HS 0x2 334302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_CC 0x3 // Carry clear Less than C == 0 348584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#define COND_LO 0x3 354302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_MI 0x4 // Minus, negative Less than N == 1 364302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_PL 0x5 // Plus, positive or zero >, ==, or unordered N == 0 374302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_VS 0x6 // Overflow Unordered V == 1 384302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_VC 0x7 // No overflow Not unordered V == 0 394302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_HI 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 0 404302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1 414302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_GE 0xA // Greater than or equal Greater than or equal N == V 424302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_LT 0xB // Less than Less than, or unordered N != V 434302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V 444302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V 454302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any 468584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#define COND_UNCOND 0xF 478584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 484302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chenstatic inline const char *ARMCondCodeToString(uint32_t CC) 494302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen{ 504302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen switch (CC) { 514302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen default: assert(0 && "Unknown condition code"); 524302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_EQ: return "eq"; 534302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_NE: return "ne"; 544302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_HS: return "hs"; 554302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_LO: return "lo"; 564302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_MI: return "mi"; 574302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_PL: return "pl"; 584302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_VS: return "vs"; 594302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_VC: return "vc"; 604302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_HI: return "hi"; 614302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_LS: return "ls"; 624302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_GE: return "ge"; 634302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_LT: return "lt"; 644302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_GT: return "gt"; 654302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_LE: return "le"; 664302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen case COND_AL: return "al"; 674302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen } 684302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen} 694302f85ab6d8737c6b44541ffb006b52010596f4Johnny Chen 70338bf54a49633d90f3c5e808847470901f25dee9Johnny Chen// Bit positions for CPSR 7124348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_T_POS 5 7224348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_F_POS 6 7324348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_I_POS 7 7424348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_A_POS 8 7524348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_E_POS 9 7624348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_J_POS 24 7724348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_Q_POS 27 7824348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_V_POS 28 7924348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_C_POS 29 8024348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_Z_POS 30 8124348847b93337ad548032e046c71f37e647da26Johnny Chen#define CPSR_N_POS 31 82338bf54a49633d90f3c5e808847470901f25dee9Johnny Chen 83888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton// CPSR mode definitions 84888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_USR 0x10u 85888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_FIQ 0x11u 86888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_IRQ 0x12u 87888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_SVC 0x13u 88888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_ABT 0x17u 89888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_UND 0x1bu 90888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton#define CPSR_MODE_SYS 0x1fu 91888a7334344778d1a4edbd58b5852ae4d53ffed9Greg Clayton 928584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen// Masks for CPSR 93b9e8f6e7a374d9313f89193e90ae41ef91712e5bGreg Clayton#define MASK_CPSR_MODE_MASK (0x0000001fu) 94b9e8f6e7a374d9313f89193e90ae41ef91712e5bGreg Clayton#define MASK_CPSR_IT_MASK (0x0600fc00u) 9524348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_T (1u << CPSR_T_POS) 9624348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_F (1u << CPSR_F_POS) 9724348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_I (1u << CPSR_I_POS) 9824348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_A (1u << CPSR_A_POS) 9924348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_E (1u << CPSR_E_POS) 1008584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#define MASK_CPSR_GE_MASK (0x000f0000u) 10124348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_J (1u << CPSR_J_POS) 10224348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_Q (1u << CPSR_Q_POS) 10324348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_V (1u << CPSR_V_POS) 10424348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_C (1u << CPSR_C_POS) 10524348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_Z (1u << CPSR_Z_POS) 10624348847b93337ad548032e046c71f37e647da26Johnny Chen#define MASK_CPSR_N (1u << CPSR_N_POS) 1078584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 1088584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen} // namespace lldb_private 1098584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen 1108584c92dc30415ebab70ef19a1b108137fd60944Johnny Chen#endif // lldb_ARMDefines_h_ 111