1//===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef ARM_DWARF_Registers_h_
11#define ARM_DWARF_Registers_h_
12
13
14enum
15{
16    dwarf_r0 = 0,
17    dwarf_r1,
18    dwarf_r2,
19    dwarf_r3,
20    dwarf_r4,
21    dwarf_r5,
22    dwarf_r6,
23    dwarf_r7,
24    dwarf_r8,
25    dwarf_r9,
26    dwarf_r10,
27    dwarf_r11,
28    dwarf_r12,
29    dwarf_sp,
30    dwarf_lr,
31    dwarf_pc,
32    dwarf_cpsr,
33
34    dwarf_s0 = 64,
35    dwarf_s1,
36    dwarf_s2,
37    dwarf_s3,
38    dwarf_s4,
39    dwarf_s5,
40    dwarf_s6,
41    dwarf_s7,
42    dwarf_s8,
43    dwarf_s9,
44    dwarf_s10,
45    dwarf_s11,
46    dwarf_s12,
47    dwarf_s13,
48    dwarf_s14,
49    dwarf_s15,
50    dwarf_s16,
51    dwarf_s17,
52    dwarf_s18,
53    dwarf_s19,
54    dwarf_s20,
55    dwarf_s21,
56    dwarf_s22,
57    dwarf_s23,
58    dwarf_s24,
59    dwarf_s25,
60    dwarf_s26,
61    dwarf_s27,
62    dwarf_s28,
63    dwarf_s29,
64    dwarf_s30,
65    dwarf_s31,
66
67    // FPA Registers 0-7
68    dwarf_f0 = 96,
69    dwarf_f1,
70    dwarf_f2,
71    dwarf_f3,
72    dwarf_f4,
73    dwarf_f5,
74    dwarf_f6,
75    dwarf_f7,
76
77    // Intel wireless MMX general purpose registers 0 - 7
78    dwarf_wCGR0 = 104,
79    dwarf_wCGR1,
80    dwarf_wCGR2,
81    dwarf_wCGR3,
82    dwarf_wCGR4,
83    dwarf_wCGR5,
84    dwarf_wCGR6,
85    dwarf_wCGR7,
86
87    // XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7)
88    dwarf_ACC0 = 104,
89    dwarf_ACC1,
90    dwarf_ACC2,
91    dwarf_ACC3,
92    dwarf_ACC4,
93    dwarf_ACC5,
94    dwarf_ACC6,
95    dwarf_ACC7,
96
97    // Intel wireless MMX data registers 0 - 15
98    dwarf_wR0 = 112,
99    dwarf_wR1,
100    dwarf_wR2,
101    dwarf_wR3,
102    dwarf_wR4,
103    dwarf_wR5,
104    dwarf_wR6,
105    dwarf_wR7,
106    dwarf_wR8,
107    dwarf_wR9,
108    dwarf_wR10,
109    dwarf_wR11,
110    dwarf_wR12,
111    dwarf_wR13,
112    dwarf_wR14,
113    dwarf_wR15,
114
115    dwarf_spsr = 128,
116    dwarf_spsr_fiq,
117    dwarf_spsr_irq,
118    dwarf_spsr_abt,
119    dwarf_spsr_und,
120    dwarf_spsr_svc,
121
122    dwarf_r8_usr = 144,
123    dwarf_r9_usr,
124    dwarf_r10_usr,
125    dwarf_r11_usr,
126    dwarf_r12_usr,
127    dwarf_r13_usr,
128    dwarf_r14_usr,
129    dwarf_r8_fiq,
130    dwarf_r9_fiq,
131    dwarf_r10_fiq,
132    dwarf_r11_fiq,
133    dwarf_r12_fiq,
134    dwarf_r13_fiq,
135    dwarf_r14_fiq,
136    dwarf_r13_irq,
137    dwarf_r14_irq,
138    dwarf_r13_abt,
139    dwarf_r14_abt,
140    dwarf_r13_und,
141    dwarf_r14_und,
142    dwarf_r13_svc,
143    dwarf_r14_svc,
144
145    // Intel wireless MMX control register in co-processor 0 - 7
146    dwarf_wC0 = 192,
147    dwarf_wC1,
148    dwarf_wC2,
149    dwarf_wC3,
150    dwarf_wC4,
151    dwarf_wC5,
152    dwarf_wC6,
153    dwarf_wC7,
154
155    // VFP-v3/Neon
156    dwarf_d0 = 256,
157    dwarf_d1,
158    dwarf_d2,
159    dwarf_d3,
160    dwarf_d4,
161    dwarf_d5,
162    dwarf_d6,
163    dwarf_d7,
164    dwarf_d8,
165    dwarf_d9,
166    dwarf_d10,
167    dwarf_d11,
168    dwarf_d12,
169    dwarf_d13,
170    dwarf_d14,
171    dwarf_d15,
172    dwarf_d16,
173    dwarf_d17,
174    dwarf_d18,
175    dwarf_d19,
176    dwarf_d20,
177    dwarf_d21,
178    dwarf_d22,
179    dwarf_d23,
180    dwarf_d24,
181    dwarf_d25,
182    dwarf_d26,
183    dwarf_d27,
184    dwarf_d28,
185    dwarf_d29,
186    dwarf_d30,
187    dwarf_d31,
188
189    // Neon quadword registers
190    dwarf_q0 = 288,
191    dwarf_q1,
192    dwarf_q2,
193    dwarf_q3,
194    dwarf_q4,
195    dwarf_q5,
196    dwarf_q6,
197    dwarf_q7,
198    dwarf_q8,
199    dwarf_q9,
200    dwarf_q10,
201    dwarf_q11,
202    dwarf_q12,
203    dwarf_q13,
204    dwarf_q14,
205    dwarf_q15
206};
207
208#endif // ARM_DWARF_Registers_h_
209
210