DNBArchImplX86_64.cpp revision 36889adf3700165ae13e8defb7433f2ba80df697
1//===-- DNBArchImplX86_64.cpp -----------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Created by Greg Clayton on 6/25/07. 11// 12//===----------------------------------------------------------------------===// 13 14#if defined (__i386__) || defined (__x86_64__) 15 16#include <sys/cdefs.h> 17 18#include "MacOSX/x86_64/DNBArchImplX86_64.h" 19#include "DNBLog.h" 20#include "MachThread.h" 21#include "MachProcess.h" 22#include <mach/mach.h> 23#include <stdlib.h> 24 25#if defined (LLDB_DEBUGSERVER_RELEASE) || defined (LLDB_DEBUGSERVER_DEBUG) 26enum debugState { 27 debugStateUnknown, 28 debugStateOff, 29 debugStateOn 30}; 31 32static debugState sFPUDebugState = debugStateUnknown; 33static debugState sAVXForceState = debugStateUnknown; 34 35static bool DebugFPURegs () 36{ 37 if (sFPUDebugState == debugStateUnknown) 38 { 39 if (getenv("DNB_DEBUG_FPU_REGS")) 40 sFPUDebugState = debugStateOn; 41 else 42 sFPUDebugState = debugStateOff; 43 } 44 45 return (sFPUDebugState == debugStateOn); 46} 47 48static bool ForceAVXRegs () 49{ 50 if (sFPUDebugState == debugStateUnknown) 51 { 52 if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS")) 53 sAVXForceState = debugStateOn; 54 else 55 sAVXForceState = debugStateOff; 56 } 57 58 return (sAVXForceState == debugStateOn); 59} 60 61#define DEBUG_FPU_REGS (DebugFPURegs()) 62#define FORCE_AVX_REGS (ForceAVXRegs()) 63#else 64#define DEBUG_FPU_REGS (0) 65#define FORCE_AVX_REGS (0) 66#endif 67 68enum DNBArchImplX86_64::AVXPresence DNBArchImplX86_64::s_has_avx = DNBArchImplX86_64::kAVXUnknown; 69 70uint64_t 71DNBArchImplX86_64::GetPC(uint64_t failValue) 72{ 73 // Get program counter 74 if (GetGPRState(false) == KERN_SUCCESS) 75 return m_state.context.gpr.__rip; 76 return failValue; 77} 78 79kern_return_t 80DNBArchImplX86_64::SetPC(uint64_t value) 81{ 82 // Get program counter 83 kern_return_t err = GetGPRState(false); 84 if (err == KERN_SUCCESS) 85 { 86 m_state.context.gpr.__rip = value; 87 err = SetGPRState(); 88 } 89 return err == KERN_SUCCESS; 90} 91 92uint64_t 93DNBArchImplX86_64::GetSP(uint64_t failValue) 94{ 95 // Get stack pointer 96 if (GetGPRState(false) == KERN_SUCCESS) 97 return m_state.context.gpr.__rsp; 98 return failValue; 99} 100 101// Uncomment the value below to verify the values in the debugger. 102//#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 103 104kern_return_t 105DNBArchImplX86_64::GetGPRState(bool force) 106{ 107 if (force || m_state.GetError(e_regSetGPR, Read)) 108 { 109 kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 110 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (GetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 111 112#if DEBUG_GPR_VALUES 113 m_state.context.gpr.__rax = ('a' << 8) + 'x'; 114 m_state.context.gpr.__rbx = ('b' << 8) + 'x'; 115 m_state.context.gpr.__rcx = ('c' << 8) + 'x'; 116 m_state.context.gpr.__rdx = ('d' << 8) + 'x'; 117 m_state.context.gpr.__rdi = ('d' << 8) + 'i'; 118 m_state.context.gpr.__rsi = ('s' << 8) + 'i'; 119 m_state.context.gpr.__rbp = ('b' << 8) + 'p'; 120 m_state.context.gpr.__rsp = ('s' << 8) + 'p'; 121 m_state.context.gpr.__r8 = ('r' << 8) + '8'; 122 m_state.context.gpr.__r9 = ('r' << 8) + '9'; 123 m_state.context.gpr.__r10 = ('r' << 8) + 'a'; 124 m_state.context.gpr.__r11 = ('r' << 8) + 'b'; 125 m_state.context.gpr.__r12 = ('r' << 8) + 'c'; 126 m_state.context.gpr.__r13 = ('r' << 8) + 'd'; 127 m_state.context.gpr.__r14 = ('r' << 8) + 'e'; 128 m_state.context.gpr.__r15 = ('r' << 8) + 'f'; 129 m_state.context.gpr.__rip = ('i' << 8) + 'p'; 130 m_state.context.gpr.__rflags = ('f' << 8) + 'l'; 131 m_state.context.gpr.__cs = ('c' << 8) + 's'; 132 m_state.context.gpr.__fs = ('f' << 8) + 's'; 133 m_state.context.gpr.__gs = ('g' << 8) + 's'; 134 m_state.SetError(e_regSetGPR, Read, 0); 135#else 136 mach_msg_type_number_t count = e_regSetWordSizeGPR; 137 m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count)); 138 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 139 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 140 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 141 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 142 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 143 "\n\trip = %16.16llx" 144 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 145 m_thread->ThreadID(), x86_THREAD_STATE64, x86_THREAD_STATE64_COUNT, 146 m_state.GetError(e_regSetGPR, Read), 147 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 148 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 149 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 150 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 151 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 152 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 153 m_state.context.gpr.__cs,m_state.context.gpr.__fs, m_state.context.gpr.__gs); 154 155 // DNBLogThreadedIf (LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 156 // "\n\trax = %16.16llx" 157 // "\n\trbx = %16.16llx" 158 // "\n\trcx = %16.16llx" 159 // "\n\trdx = %16.16llx" 160 // "\n\trdi = %16.16llx" 161 // "\n\trsi = %16.16llx" 162 // "\n\trbp = %16.16llx" 163 // "\n\trsp = %16.16llx" 164 // "\n\t r8 = %16.16llx" 165 // "\n\t r9 = %16.16llx" 166 // "\n\tr10 = %16.16llx" 167 // "\n\tr11 = %16.16llx" 168 // "\n\tr12 = %16.16llx" 169 // "\n\tr13 = %16.16llx" 170 // "\n\tr14 = %16.16llx" 171 // "\n\tr15 = %16.16llx" 172 // "\n\trip = %16.16llx" 173 // "\n\tflg = %16.16llx" 174 // "\n\t cs = %16.16llx" 175 // "\n\t fs = %16.16llx" 176 // "\n\t gs = %16.16llx", 177 // m_thread->ThreadID(), 178 // x86_THREAD_STATE64, 179 // x86_THREAD_STATE64_COUNT, 180 // m_state.GetError(e_regSetGPR, Read), 181 // m_state.context.gpr.__rax, 182 // m_state.context.gpr.__rbx, 183 // m_state.context.gpr.__rcx, 184 // m_state.context.gpr.__rdx, 185 // m_state.context.gpr.__rdi, 186 // m_state.context.gpr.__rsi, 187 // m_state.context.gpr.__rbp, 188 // m_state.context.gpr.__rsp, 189 // m_state.context.gpr.__r8, 190 // m_state.context.gpr.__r9, 191 // m_state.context.gpr.__r10, 192 // m_state.context.gpr.__r11, 193 // m_state.context.gpr.__r12, 194 // m_state.context.gpr.__r13, 195 // m_state.context.gpr.__r14, 196 // m_state.context.gpr.__r15, 197 // m_state.context.gpr.__rip, 198 // m_state.context.gpr.__rflags, 199 // m_state.context.gpr.__cs, 200 // m_state.context.gpr.__fs, 201 // m_state.context.gpr.__gs); 202#endif 203 } 204 return m_state.GetError(e_regSetGPR, Read); 205} 206 207// Uncomment the value below to verify the values in the debugger. 208//#define DEBUG_FPU_REGS 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 209 210kern_return_t 211DNBArchImplX86_64::GetFPUState(bool force) 212{ 213 if (force || m_state.GetError(e_regSetFPU, Read)) 214 { 215 if (DEBUG_FPU_REGS) { 216 if (CPUHasAVX() || FORCE_AVX_REGS) 217 { 218 m_state.context.fpu.avx.__fpu_reserved[0] = -1; 219 m_state.context.fpu.avx.__fpu_reserved[1] = -1; 220 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234; 221 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678; 222 m_state.context.fpu.avx.__fpu_ftw = 1; 223 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX; 224 m_state.context.fpu.avx.__fpu_fop = 2; 225 m_state.context.fpu.avx.__fpu_ip = 3; 226 m_state.context.fpu.avx.__fpu_cs = 4; 227 m_state.context.fpu.avx.__fpu_rsrv2 = 5; 228 m_state.context.fpu.avx.__fpu_dp = 6; 229 m_state.context.fpu.avx.__fpu_ds = 7; 230 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX; 231 m_state.context.fpu.avx.__fpu_mxcsr = 8; 232 m_state.context.fpu.avx.__fpu_mxcsrmask = 9; 233 int i; 234 for (i=0; i<16; ++i) 235 { 236 if (i<10) 237 { 238 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 239 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 240 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 241 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 242 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 243 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 244 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 245 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 246 } 247 else 248 { 249 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 250 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 251 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 252 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 253 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 254 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 255 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 256 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 257 } 258 259 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0'; 260 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1'; 261 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2'; 262 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3'; 263 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4'; 264 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5'; 265 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6'; 266 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7'; 267 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8'; 268 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9'; 269 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 270 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 271 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 272 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 273 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 274 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 275 276 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0'; 277 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1'; 278 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2'; 279 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3'; 280 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4'; 281 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5'; 282 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6'; 283 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7'; 284 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8'; 285 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9'; 286 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A'; 287 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B'; 288 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C'; 289 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D'; 290 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E'; 291 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F'; 292 } 293 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i) 294 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN; 295 m_state.context.fpu.avx.__fpu_reserved1 = -1; 296 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i) 297 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; 298 m_state.SetError(e_regSetFPU, Read, 0); 299 } 300 else 301 { 302 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; 303 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; 304 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; 305 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; 306 m_state.context.fpu.no_avx.__fpu_ftw = 1; 307 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; 308 m_state.context.fpu.no_avx.__fpu_fop = 2; 309 m_state.context.fpu.no_avx.__fpu_ip = 3; 310 m_state.context.fpu.no_avx.__fpu_cs = 4; 311 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; 312 m_state.context.fpu.no_avx.__fpu_dp = 6; 313 m_state.context.fpu.no_avx.__fpu_ds = 7; 314 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; 315 m_state.context.fpu.no_avx.__fpu_mxcsr = 8; 316 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; 317 int i; 318 for (i=0; i<16; ++i) 319 { 320 if (i<10) 321 { 322 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 323 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 324 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 325 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 326 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 327 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 328 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 329 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 330 } 331 else 332 { 333 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 334 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 335 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 336 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 337 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 338 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 339 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 340 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 341 } 342 343 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; 344 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; 345 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; 346 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; 347 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; 348 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; 349 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; 350 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; 351 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8'; 352 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9'; 353 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 354 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 355 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 356 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 357 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 358 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 359 } 360 for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) 361 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; 362 m_state.context.fpu.no_avx.__fpu_reserved1 = -1; 363 m_state.SetError(e_regSetFPU, Read, 0); 364 } 365 } 366 else 367 { 368 if (CPUHasAVX() || FORCE_AVX_REGS) 369 { 370 mach_msg_type_number_t count = e_regSetWordSizeAVX; 371 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count)); 372 } 373 else 374 { 375 mach_msg_type_number_t count = e_regSetWordSizeFPR; 376 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count)); 377 } 378 } 379 } 380 return m_state.GetError(e_regSetFPU, Read); 381} 382 383kern_return_t 384DNBArchImplX86_64::GetEXCState(bool force) 385{ 386 if (force || m_state.GetError(e_regSetEXC, Read)) 387 { 388 mach_msg_type_number_t count = e_regSetWordSizeEXC; 389 m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count)); 390 } 391 return m_state.GetError(e_regSetEXC, Read); 392} 393 394kern_return_t 395DNBArchImplX86_64::SetGPRState() 396{ 397 kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 398 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 399 400 m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR)); 401 DNBLogThreadedIf (LOG_THREAD, "::thread_set_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 402 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 403 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 404 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 405 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 406 "\n\trip = %16.16llx" 407 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 408 m_thread->ThreadID(), __x86_64_THREAD_STATE, e_regSetWordSizeGPR, 409 m_state.GetError(e_regSetGPR, Write), 410 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 411 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 412 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 413 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 414 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 415 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 416 m_state.context.gpr.__cs, m_state.context.gpr.__fs, m_state.context.gpr.__gs); 417 return m_state.GetError(e_regSetGPR, Write); 418} 419 420kern_return_t 421DNBArchImplX86_64::SetFPUState() 422{ 423 if (DEBUG_FPU_REGS) 424 { 425 m_state.SetError(e_regSetFPU, Write, 0); 426 return m_state.GetError(e_regSetFPU, Write); 427 } 428 else 429 { 430 if (CPUHasAVX() || FORCE_AVX_REGS) 431 { 432 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX)); 433 return m_state.GetError(e_regSetFPU, Write); 434 } 435 else 436 { 437 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPR)); 438 return m_state.GetError(e_regSetFPU, Write); 439 } 440 } 441} 442 443kern_return_t 444DNBArchImplX86_64::SetEXCState() 445{ 446 m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC)); 447 return m_state.GetError(e_regSetEXC, Write); 448} 449 450kern_return_t 451DNBArchImplX86_64::GetDBGState(bool force) 452{ 453 if (force || m_state.GetError(e_regSetDBG, Read)) 454 { 455 mach_msg_type_number_t count = e_regSetWordSizeDBG; 456 m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count)); 457 } 458 return m_state.GetError(e_regSetDBG, Read); 459} 460 461kern_return_t 462DNBArchImplX86_64::SetDBGState() 463{ 464 m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG)); 465 return m_state.GetError(e_regSetDBG, Write); 466} 467 468void 469DNBArchImplX86_64::ThreadWillResume() 470{ 471 // Do we need to step this thread? If so, let the mach thread tell us so. 472 if (m_thread->IsStepping()) 473 { 474 // This is the primary thread, let the arch do anything it needs 475 EnableHardwareSingleStep(true); 476 } 477 478 // Reset the debug status register, if necessary, before we resume. 479 kern_return_t kret = GetDBGState(false); 480 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret); 481 if (kret != KERN_SUCCESS) 482 return; 483 484 DBG &debug_state = m_state.context.dbg; 485 bool need_reset = false; 486 uint32_t i, num = NumSupportedHardwareWatchpoints(); 487 for (i = 0; i < num; ++i) 488 if (IsWatchpointHit(debug_state, i)) 489 need_reset = true; 490 491 if (need_reset) 492 { 493 ClearWatchpointHits(debug_state); 494 kret = SetDBGState(); 495 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret); 496 } 497} 498 499bool 500DNBArchImplX86_64::ThreadDidStop() 501{ 502 bool success = true; 503 504 m_state.InvalidateAllRegisterStates(); 505 506 // Are we stepping a single instruction? 507 if (GetGPRState(true) == KERN_SUCCESS) 508 { 509 // We are single stepping, was this the primary thread? 510 if (m_thread->IsStepping()) 511 { 512 // This was the primary thread, we need to clear the trace 513 // bit if so. 514 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 515 } 516 else 517 { 518 // The MachThread will automatically restore the suspend count 519 // in ThreadDidStop(), so we don't need to do anything here if 520 // we weren't the primary thread the last time 521 } 522 } 523 return success; 524} 525 526bool 527DNBArchImplX86_64::NotifyException(MachException::Data& exc) 528{ 529 switch (exc.exc_type) 530 { 531 case EXC_BAD_ACCESS: 532 break; 533 case EXC_BAD_INSTRUCTION: 534 break; 535 case EXC_ARITHMETIC: 536 break; 537 case EXC_EMULATION: 538 break; 539 case EXC_SOFTWARE: 540 break; 541 case EXC_BREAKPOINT: 542 if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) 543 { 544 // exc_code = EXC_I386_BPT 545 // 546 nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS); 547 if (pc != INVALID_NUB_ADDRESS && pc > 0) 548 { 549 pc -= 1; 550 // Check for a breakpoint at one byte prior to the current PC value 551 // since the PC will be just past the trap. 552 553 nub_break_t breakID = m_thread->Process()->Breakpoints().FindIDByAddress(pc); 554 if (NUB_BREAK_ID_IS_VALID(breakID)) 555 { 556 // Backup the PC for i386 since the trap was taken and the PC 557 // is at the address following the single byte trap instruction. 558 if (m_state.context.gpr.__rip > 0) 559 { 560 m_state.context.gpr.__rip = pc; 561 // Write the new PC back out 562 SetGPRState (); 563 } 564 } 565 return true; 566 } 567 } 568 else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1) 569 { 570 // exc_code = EXC_I386_SGL 571 // 572 // Check whether this corresponds to a watchpoint hit event. 573 // If yes, set the exc_sub_code to the data break address. 574 nub_addr_t addr = 0; 575 uint32_t hw_index = GetHardwareWatchpointHit(addr); 576 if (hw_index != INVALID_NUB_HW_INDEX) 577 { 578 exc.exc_data[1] = addr; 579 // Piggyback the hw_index in the exc.data. 580 exc.exc_data.push_back(hw_index); 581 } 582 583 return true; 584 } 585 break; 586 case EXC_SYSCALL: 587 break; 588 case EXC_MACH_SYSCALL: 589 break; 590 case EXC_RPC_ALERT: 591 break; 592 } 593 return false; 594} 595 596uint32_t 597DNBArchImplX86_64::NumSupportedHardwareWatchpoints() 598{ 599 // Available debug address registers: dr0, dr1, dr2, dr3. 600 return 4; 601} 602 603static uint32_t 604size_and_rw_bits(nub_size_t size, bool read, bool write) 605{ 606 uint32_t rw; 607 if (read) { 608 rw = 0x3; // READ or READ/WRITE 609 } else if (write) { 610 rw = 0x1; // WRITE 611 } else { 612 assert(0 && "read and write cannot both be false"); 613 } 614 615 switch (size) { 616 case 1: 617 return rw; 618 case 2: 619 return (0x1 << 2) | rw; 620 case 4: 621 return (0x3 << 2) | rw; 622 case 8: 623 return (0x2 << 2) | rw; 624 default: 625 assert(0 && "invalid size, must be one of 1, 2, 4, or 8"); 626 } 627} 628void 629DNBArchImplX86_64::SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write) 630{ 631 // Set both dr7 (debug control register) and dri (debug address register). 632 633 // dr7{7-0} encodes the local/gloabl enable bits: 634 // global enable --. .-- local enable 635 // | | 636 // v v 637 // dr0 -> bits{1-0} 638 // dr1 -> bits{3-2} 639 // dr2 -> bits{5-4} 640 // dr3 -> bits{7-6} 641 // 642 // dr7{31-16} encodes the rw/len bits: 643 // b_x+3, b_x+2, b_x+1, b_x 644 // where bits{x+1, x} => rw 645 // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io read-or-write (unused) 646 // and bits{x+3, x+2} => len 647 // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte 648 // 649 // dr0 -> bits{19-16} 650 // dr1 -> bits{23-20} 651 // dr2 -> bits{27-24} 652 // dr3 -> bits{31-28} 653 debug_state.__dr7 |= (1 << (2*hw_index) | 654 size_and_rw_bits(size, read, write) << (16+4*hw_index)); 655 switch (hw_index) { 656 case 0: 657 debug_state.__dr0 = addr; break; 658 case 1: 659 debug_state.__dr1 = addr; break; 660 case 2: 661 debug_state.__dr2 = addr; break; 662 case 3: 663 debug_state.__dr3 = addr; break; 664 default: 665 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 666 } 667 return; 668} 669 670void 671DNBArchImplX86_64::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) 672{ 673 debug_state.__dr7 &= ~(3 << (2*hw_index)); 674 switch (hw_index) { 675 case 0: 676 debug_state.__dr0 = 0; break; 677 case 1: 678 debug_state.__dr1 = 0; break; 679 case 2: 680 debug_state.__dr2 = 0; break; 681 case 3: 682 debug_state.__dr3 = 0; break; 683 default: 684 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 685 } 686 return; 687} 688 689bool 690DNBArchImplX86_64::IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index) 691{ 692 // Check dr7 (debug control register) for local/global enable bits: 693 // global enable --. .-- local enable 694 // | | 695 // v v 696 // dr0 -> bits{1-0} 697 // dr1 -> bits{3-2} 698 // dr2 -> bits{5-4} 699 // dr3 -> bits{7-6} 700 return (debug_state.__dr7 & (3 << (2*hw_index))) == 0; 701} 702 703// Resets local copy of debug status register to wait for the next debug excpetion. 704void 705DNBArchImplX86_64::ClearWatchpointHits(DBG &debug_state) 706{ 707 // See also IsWatchpointHit(). 708 debug_state.__dr6 = 0; 709 return; 710} 711 712bool 713DNBArchImplX86_64::IsWatchpointHit(const DBG &debug_state, uint32_t hw_index) 714{ 715 // Check dr6 (debug status register) whether a watchpoint hits: 716 // is watchpoint hit? 717 // | 718 // v 719 // dr0 -> bits{0} 720 // dr1 -> bits{1} 721 // dr2 -> bits{2} 722 // dr3 -> bits{3} 723 return (debug_state.__dr6 & (1 << hw_index)); 724} 725 726nub_addr_t 727DNBArchImplX86_64::GetWatchAddress(const DBG &debug_state, uint32_t hw_index) 728{ 729 switch (hw_index) { 730 case 0: 731 return debug_state.__dr0; 732 case 1: 733 return debug_state.__dr1; 734 case 2: 735 return debug_state.__dr2; 736 case 3: 737 return debug_state.__dr3; 738 default: 739 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 740 } 741} 742 743uint32_t 744DNBArchImplX86_64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write) 745{ 746 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write); 747 748 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 749 750 // Can only watch 1, 2, 4, or 8 bytes. 751 if (!(size == 1 || size == 2 || size == 4 || size == 8)) 752 return INVALID_NUB_HW_INDEX; 753 754 // We must watch for either read or write 755 if (read == false && write == false) 756 return INVALID_NUB_HW_INDEX; 757 758 // Read the debug state 759 kern_return_t kret = GetDBGState(false); 760 761 if (kret == KERN_SUCCESS) 762 { 763 // Check to make sure we have the needed hardware support 764 uint32_t i = 0; 765 766 DBG &debug_state = m_state.context.dbg; 767 for (i = 0; i < num_hw_watchpoints; ++i) 768 { 769 if (IsWatchpointVacant(debug_state, i)) 770 break; 771 } 772 773 // See if we found an available hw breakpoint slot above 774 if (i < num_hw_watchpoints) 775 { 776 // Modify our local copy of the debug state, first. 777 SetWatchpoint(debug_state, i, addr, size, read, write); 778 // Now set the watch point in the inferior. 779 kret = SetDBGState(); 780 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret); 781 782 if (kret == KERN_SUCCESS) 783 return i; 784 } 785 else 786 { 787 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints); 788 } 789 } 790 return INVALID_NUB_HW_INDEX; 791} 792 793bool 794DNBArchImplX86_64::DisableHardwareWatchpoint (uint32_t hw_index) 795{ 796 kern_return_t kret = GetDBGState(false); 797 798 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 799 if (kret == KERN_SUCCESS) 800 { 801 DBG &debug_state = m_state.context.dbg; 802 if (hw_index < num_hw_points && !IsWatchpointVacant(debug_state, hw_index)) 803 { 804 // Modify our local copy of the debug state, first. 805 ClearWatchpoint(debug_state, hw_index); 806 // Now disable the watch point in the inferior. 807 kret = SetDBGState(); 808 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::DisableHardwareWatchpoint( %u )", 809 hw_index); 810 811 if (kret == KERN_SUCCESS) 812 return true; 813 } 814 } 815 return false; 816} 817 818// Iterate through the debug status register; return the index of the first hit. 819uint32_t 820DNBArchImplX86_64::GetHardwareWatchpointHit(nub_addr_t &addr) 821{ 822 // Read the debug state 823 kern_return_t kret = GetDBGState(true); 824 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret); 825 if (kret == KERN_SUCCESS) 826 { 827 DBG &debug_state = m_state.context.dbg; 828 uint32_t i, num = NumSupportedHardwareWatchpoints(); 829 for (i = 0; i < num; ++i) 830 { 831 if (IsWatchpointHit(debug_state, i)) 832 { 833 addr = GetWatchAddress(debug_state, i); 834 DNBLogThreadedIf(LOG_WATCHPOINTS, 835 "DNBArchImplX86_64::GetHardwareWatchpointHit() found => %u (addr = %8.8p).", 836 i, addr); 837 return i; 838 } 839 } 840 } 841 return INVALID_NUB_HW_INDEX; 842} 843 844// Set the single step bit in the processor status register. 845kern_return_t 846DNBArchImplX86_64::EnableHardwareSingleStep (bool enable) 847{ 848 if (GetGPRState(false) == KERN_SUCCESS) 849 { 850 const uint32_t trace_bit = 0x100u; 851 if (enable) 852 m_state.context.gpr.__rflags |= trace_bit; 853 else 854 m_state.context.gpr.__rflags &= ~trace_bit; 855 return SetGPRState(); 856 } 857 return m_state.GetError(e_regSetGPR, Read); 858} 859 860 861//---------------------------------------------------------------------- 862// Register information defintions 863//---------------------------------------------------------------------- 864 865enum 866{ 867 gpr_rax = 0, 868 gpr_rbx, 869 gpr_rcx, 870 gpr_rdx, 871 gpr_rdi, 872 gpr_rsi, 873 gpr_rbp, 874 gpr_rsp, 875 gpr_r8, 876 gpr_r9, 877 gpr_r10, 878 gpr_r11, 879 gpr_r12, 880 gpr_r13, 881 gpr_r14, 882 gpr_r15, 883 gpr_rip, 884 gpr_rflags, 885 gpr_cs, 886 gpr_fs, 887 gpr_gs, 888 k_num_gpr_regs 889}; 890 891enum { 892 fpu_fcw, 893 fpu_fsw, 894 fpu_ftw, 895 fpu_fop, 896 fpu_ip, 897 fpu_cs, 898 fpu_dp, 899 fpu_ds, 900 fpu_mxcsr, 901 fpu_mxcsrmask, 902 fpu_stmm0, 903 fpu_stmm1, 904 fpu_stmm2, 905 fpu_stmm3, 906 fpu_stmm4, 907 fpu_stmm5, 908 fpu_stmm6, 909 fpu_stmm7, 910 fpu_xmm0, 911 fpu_xmm1, 912 fpu_xmm2, 913 fpu_xmm3, 914 fpu_xmm4, 915 fpu_xmm5, 916 fpu_xmm6, 917 fpu_xmm7, 918 fpu_xmm8, 919 fpu_xmm9, 920 fpu_xmm10, 921 fpu_xmm11, 922 fpu_xmm12, 923 fpu_xmm13, 924 fpu_xmm14, 925 fpu_xmm15, 926 fpu_ymm0, 927 fpu_ymm1, 928 fpu_ymm2, 929 fpu_ymm3, 930 fpu_ymm4, 931 fpu_ymm5, 932 fpu_ymm6, 933 fpu_ymm7, 934 fpu_ymm8, 935 fpu_ymm9, 936 fpu_ymm10, 937 fpu_ymm11, 938 fpu_ymm12, 939 fpu_ymm13, 940 fpu_ymm14, 941 fpu_ymm15, 942 k_num_fpu_regs, 943 944 // Aliases 945 fpu_fctrl = fpu_fcw, 946 fpu_fstat = fpu_fsw, 947 fpu_ftag = fpu_ftw, 948 fpu_fiseg = fpu_cs, 949 fpu_fioff = fpu_ip, 950 fpu_foseg = fpu_ds, 951 fpu_fooff = fpu_dp 952}; 953 954enum { 955 exc_trapno, 956 exc_err, 957 exc_faultvaddr, 958 k_num_exc_regs, 959}; 960 961 962enum gcc_dwarf_regnums 963{ 964 gcc_dwarf_rax = 0, 965 gcc_dwarf_rdx = 1, 966 gcc_dwarf_rcx = 2, 967 gcc_dwarf_rbx = 3, 968 gcc_dwarf_rsi = 4, 969 gcc_dwarf_rdi = 5, 970 gcc_dwarf_rbp = 6, 971 gcc_dwarf_rsp = 7, 972 gcc_dwarf_r8, 973 gcc_dwarf_r9, 974 gcc_dwarf_r10, 975 gcc_dwarf_r11, 976 gcc_dwarf_r12, 977 gcc_dwarf_r13, 978 gcc_dwarf_r14, 979 gcc_dwarf_r15, 980 gcc_dwarf_rip, 981 gcc_dwarf_xmm0, 982 gcc_dwarf_xmm1, 983 gcc_dwarf_xmm2, 984 gcc_dwarf_xmm3, 985 gcc_dwarf_xmm4, 986 gcc_dwarf_xmm5, 987 gcc_dwarf_xmm6, 988 gcc_dwarf_xmm7, 989 gcc_dwarf_xmm8, 990 gcc_dwarf_xmm9, 991 gcc_dwarf_xmm10, 992 gcc_dwarf_xmm11, 993 gcc_dwarf_xmm12, 994 gcc_dwarf_xmm13, 995 gcc_dwarf_xmm14, 996 gcc_dwarf_xmm15, 997 gcc_dwarf_stmm0, 998 gcc_dwarf_stmm1, 999 gcc_dwarf_stmm2, 1000 gcc_dwarf_stmm3, 1001 gcc_dwarf_stmm4, 1002 gcc_dwarf_stmm5, 1003 gcc_dwarf_stmm6, 1004 gcc_dwarf_stmm7, 1005 gcc_dwarf_ymm0 = gcc_dwarf_xmm0, 1006 gcc_dwarf_ymm1 = gcc_dwarf_xmm1, 1007 gcc_dwarf_ymm2 = gcc_dwarf_xmm2, 1008 gcc_dwarf_ymm3 = gcc_dwarf_xmm3, 1009 gcc_dwarf_ymm4 = gcc_dwarf_xmm4, 1010 gcc_dwarf_ymm5 = gcc_dwarf_xmm5, 1011 gcc_dwarf_ymm6 = gcc_dwarf_xmm6, 1012 gcc_dwarf_ymm7 = gcc_dwarf_xmm7, 1013 gcc_dwarf_ymm8 = gcc_dwarf_xmm8, 1014 gcc_dwarf_ymm9 = gcc_dwarf_xmm9, 1015 gcc_dwarf_ymm10 = gcc_dwarf_xmm10, 1016 gcc_dwarf_ymm11 = gcc_dwarf_xmm11, 1017 gcc_dwarf_ymm12 = gcc_dwarf_xmm12, 1018 gcc_dwarf_ymm13 = gcc_dwarf_xmm13, 1019 gcc_dwarf_ymm14 = gcc_dwarf_xmm14, 1020 gcc_dwarf_ymm15 = gcc_dwarf_xmm15 1021}; 1022 1023enum gdb_regnums 1024{ 1025 gdb_rax = 0, 1026 gdb_rbx = 1, 1027 gdb_rcx = 2, 1028 gdb_rdx = 3, 1029 gdb_rsi = 4, 1030 gdb_rdi = 5, 1031 gdb_rbp = 6, 1032 gdb_rsp = 7, 1033 gdb_r8 = 8, 1034 gdb_r9 = 9, 1035 gdb_r10 = 10, 1036 gdb_r11 = 11, 1037 gdb_r12 = 12, 1038 gdb_r13 = 13, 1039 gdb_r14 = 14, 1040 gdb_r15 = 15, 1041 gdb_rip = 16, 1042 gdb_rflags = 17, 1043 gdb_cs = 18, 1044 gdb_ss = 19, 1045 gdb_ds = 20, 1046 gdb_es = 21, 1047 gdb_fs = 22, 1048 gdb_gs = 23, 1049 gdb_stmm0 = 24, 1050 gdb_stmm1 = 25, 1051 gdb_stmm2 = 26, 1052 gdb_stmm3 = 27, 1053 gdb_stmm4 = 28, 1054 gdb_stmm5 = 29, 1055 gdb_stmm6 = 30, 1056 gdb_stmm7 = 31, 1057 gdb_fctrl = 32, gdb_fcw = gdb_fctrl, 1058 gdb_fstat = 33, gdb_fsw = gdb_fstat, 1059 gdb_ftag = 34, gdb_ftw = gdb_ftag, 1060 gdb_fiseg = 35, gdb_fpu_cs = gdb_fiseg, 1061 gdb_fioff = 36, gdb_ip = gdb_fioff, 1062 gdb_foseg = 37, gdb_fpu_ds = gdb_foseg, 1063 gdb_fooff = 38, gdb_dp = gdb_fooff, 1064 gdb_fop = 39, 1065 gdb_xmm0 = 40, 1066 gdb_xmm1 = 41, 1067 gdb_xmm2 = 42, 1068 gdb_xmm3 = 43, 1069 gdb_xmm4 = 44, 1070 gdb_xmm5 = 45, 1071 gdb_xmm6 = 46, 1072 gdb_xmm7 = 47, 1073 gdb_xmm8 = 48, 1074 gdb_xmm9 = 49, 1075 gdb_xmm10 = 50, 1076 gdb_xmm11 = 51, 1077 gdb_xmm12 = 52, 1078 gdb_xmm13 = 53, 1079 gdb_xmm14 = 54, 1080 gdb_xmm15 = 55, 1081 gdb_mxcsr = 56, 1082 gdb_ymm0 = gdb_xmm0, 1083 gdb_ymm1 = gdb_xmm1, 1084 gdb_ymm2 = gdb_xmm2, 1085 gdb_ymm3 = gdb_xmm3, 1086 gdb_ymm4 = gdb_xmm4, 1087 gdb_ymm5 = gdb_xmm5, 1088 gdb_ymm6 = gdb_xmm6, 1089 gdb_ymm7 = gdb_xmm7, 1090 gdb_ymm8 = gdb_xmm8, 1091 gdb_ymm9 = gdb_xmm9, 1092 gdb_ymm10 = gdb_xmm10, 1093 gdb_ymm11 = gdb_xmm11, 1094 gdb_ymm12 = gdb_xmm12, 1095 gdb_ymm13 = gdb_xmm13, 1096 gdb_ymm14 = gdb_xmm14, 1097 gdb_ymm15 = gdb_xmm15 1098}; 1099 1100#define GPR_OFFSET(reg) (offsetof (DNBArchImplX86_64::GPR, __##reg)) 1101#define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx)) 1102#define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx)) 1103#define EXC_OFFSET(reg) (offsetof (DNBArchImplX86_64::EXC, __##reg) + offsetof (DNBArchImplX86_64::Context, exc)) 1104 1105// This does not accurately identify the location of ymm0...7 in 1106// Context.fpu.avx. That is because there is a bunch of padding 1107// in Context.fpu.avx that we don't need. Offset macros lay out 1108// the register state that Debugserver transmits to the debugger 1109// -- not to interpret the thread_get_state info. 1110#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n)) 1111 1112#define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg)) 1113#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg)) 1114#define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg)) 1115#define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg)) 1116#define FPU_SIZE_YMM(reg) (32) 1117#define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg)) 1118 1119// These macros will auto define the register name, alt name, register size, 1120// register offset, encoding, format and native register. This ensures that 1121// the register state structures are defined correctly and have the correct 1122// sizes and offsets. 1123#define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg } 1124#define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg } 1125#define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg } 1126#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg } 1127 1128// General purpose registers for 64 bit 1129const DNBRegisterInfo 1130DNBArchImplX86_64::g_gpr_registers[] = 1131{ 1132 DEFINE_GPR (rax), 1133 DEFINE_GPR (rbx), 1134 DEFINE_GPR_ALT (rcx , "arg4", GENERIC_REGNUM_ARG4), 1135 DEFINE_GPR_ALT (rdx , "arg3", GENERIC_REGNUM_ARG3), 1136 DEFINE_GPR_ALT (rdi , "arg1", GENERIC_REGNUM_ARG1), 1137 DEFINE_GPR_ALT (rsi , "arg2", GENERIC_REGNUM_ARG2), 1138 DEFINE_GPR_ALT (rbp , "fp" , GENERIC_REGNUM_FP), 1139 DEFINE_GPR_ALT (rsp , "sp" , GENERIC_REGNUM_SP), 1140 DEFINE_GPR_ALT (r8 , "arg5", GENERIC_REGNUM_ARG5), 1141 DEFINE_GPR_ALT (r9 , "arg6", GENERIC_REGNUM_ARG6), 1142 DEFINE_GPR (r10), 1143 DEFINE_GPR (r11), 1144 DEFINE_GPR (r12), 1145 DEFINE_GPR (r13), 1146 DEFINE_GPR (r14), 1147 DEFINE_GPR (r15), 1148 DEFINE_GPR_ALT (rip , "pc", GENERIC_REGNUM_PC), 1149 DEFINE_GPR_ALT3 (rflags, "flags", GENERIC_REGNUM_FLAGS), 1150 DEFINE_GPR_ALT2 (cs, NULL), 1151 DEFINE_GPR_ALT2 (fs, NULL), 1152 DEFINE_GPR_ALT2 (gs, NULL), 1153}; 1154 1155// Floating point registers 64 bit 1156const DNBRegisterInfo 1157DNBArchImplX86_64::g_fpu_registers_no_avx[] = 1158{ 1159 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1, -1, -1, -1 }, 1160 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1, -1, -1, -1 }, 1161 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1, -1, -1, -1 }, 1162 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1, -1, -1, -1 }, 1163 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1, -1, -1, -1 }, 1164 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1, -1, -1, -1 }, 1165 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1, -1, -1, -1 }, 1166 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1, -1, -1, -1 }, 1167 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1, -1, -1, -1 }, 1168 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 1169 1170 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 1171 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1172 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1173 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1174 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1175 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 1176 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1177 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 1178 1179 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 1180 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 1181 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 1182 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 1183 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 1184 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 1185 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 1186 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 1187 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 1188 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 1189 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 1190 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1191 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1192 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 1193 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1194 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 1195}; 1196 1197const DNBRegisterInfo 1198DNBArchImplX86_64::g_fpu_registers_avx[] = 1199{ 1200 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1, -1, -1, -1 }, 1201 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1, -1, -1, -1 }, 1202 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1, -1, -1, -1 }, 1203 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1, -1, -1, -1 }, 1204 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1, -1, -1, -1 }, 1205 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1, -1, -1, -1 }, 1206 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1, -1, -1, -1 }, 1207 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1, -1, -1, -1 }, 1208 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1, -1, -1, -1 }, 1209 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 1210 1211 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 1212 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1213 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1214 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1215 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1216 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 1217 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1218 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 1219 1220 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 1221 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 1222 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 1223 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 1224 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 1225 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 1226 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 1227 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 1228 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 1229 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 1230 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 1231 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1232 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1233 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 1234 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1235 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 1236 1237 { e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1, gdb_ymm0 }, 1238 { e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1, gdb_ymm1 }, 1239 { e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1, gdb_ymm2 }, 1240 { e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1, gdb_ymm3 }, 1241 { e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1, gdb_ymm4 }, 1242 { e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1, gdb_ymm5 }, 1243 { e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1, gdb_ymm6 }, 1244 { e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1, gdb_ymm7 }, 1245 { e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1, gdb_ymm8 }, 1246 { e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1, gdb_ymm9 }, 1247 { e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1, gdb_ymm10 }, 1248 { e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1, gdb_ymm11 }, 1249 { e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1, gdb_ymm12 }, 1250 { e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1, gdb_ymm13 }, 1251 { e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1, gdb_ymm14 }, 1252 { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1, gdb_ymm15 } 1253}; 1254 1255// Exception registers 1256 1257const DNBRegisterInfo 1258DNBArchImplX86_64::g_exc_registers[] = 1259{ 1260 { e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1, -1, -1, -1 }, 1261 { e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1, -1, -1, -1 }, 1262 { e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1, -1, -1, -1 } 1263}; 1264 1265// Number of registers in each register set 1266const size_t DNBArchImplX86_64::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo); 1267const size_t DNBArchImplX86_64::k_num_fpu_registers_no_avx = sizeof(g_fpu_registers_no_avx)/sizeof(DNBRegisterInfo); 1268const size_t DNBArchImplX86_64::k_num_fpu_registers_avx = sizeof(g_fpu_registers_avx)/sizeof(DNBRegisterInfo); 1269const size_t DNBArchImplX86_64::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo); 1270const size_t DNBArchImplX86_64::k_num_all_registers_no_avx = k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers; 1271const size_t DNBArchImplX86_64::k_num_all_registers_avx = k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers; 1272 1273//---------------------------------------------------------------------- 1274// Register set definitions. The first definitions at register set index 1275// of zero is for all registers, followed by other registers sets. The 1276// register information for the all register set need not be filled in. 1277//---------------------------------------------------------------------- 1278const DNBRegisterSetInfo 1279DNBArchImplX86_64::g_reg_sets_no_avx[] = 1280{ 1281 { "x86_64 Registers", NULL, k_num_all_registers_no_avx }, 1282 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1283 { "Floating Point Registers", g_fpu_registers_no_avx, k_num_fpu_registers_no_avx }, 1284 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1285}; 1286 1287const DNBRegisterSetInfo 1288DNBArchImplX86_64::g_reg_sets_avx[] = 1289{ 1290 { "x86_64 Registers", NULL, k_num_all_registers_avx }, 1291 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1292 { "Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx }, 1293 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1294}; 1295 1296// Total number of register sets for this architecture 1297const size_t DNBArchImplX86_64::k_num_register_sets = sizeof(g_reg_sets_avx)/sizeof(DNBRegisterSetInfo); 1298 1299 1300DNBArchProtocol * 1301DNBArchImplX86_64::Create (MachThread *thread) 1302{ 1303 return new DNBArchImplX86_64 (thread); 1304} 1305 1306const uint8_t * const 1307DNBArchImplX86_64::SoftwareBreakpointOpcode (nub_size_t byte_size) 1308{ 1309 static const uint8_t g_breakpoint_opcode[] = { 0xCC }; 1310 if (byte_size == 1) 1311 return g_breakpoint_opcode; 1312 return NULL; 1313} 1314 1315const DNBRegisterSetInfo * 1316DNBArchImplX86_64::GetRegisterSetInfo(nub_size_t *num_reg_sets) 1317{ 1318 *num_reg_sets = k_num_register_sets; 1319 1320 if (CPUHasAVX() || FORCE_AVX_REGS) 1321 return g_reg_sets_avx; 1322 else 1323 return g_reg_sets_no_avx; 1324} 1325 1326void 1327DNBArchImplX86_64::Initialize() 1328{ 1329 DNBArchPluginInfo arch_plugin_info = 1330 { 1331 CPU_TYPE_X86_64, 1332 DNBArchImplX86_64::Create, 1333 DNBArchImplX86_64::GetRegisterSetInfo, 1334 DNBArchImplX86_64::SoftwareBreakpointOpcode 1335 }; 1336 1337 // Register this arch plug-in with the main protocol class 1338 DNBArchProtocol::RegisterArchPlugin (arch_plugin_info); 1339} 1340 1341bool 1342DNBArchImplX86_64::GetRegisterValue(int set, int reg, DNBRegisterValue *value) 1343{ 1344 if (set == REGISTER_SET_GENERIC) 1345 { 1346 switch (reg) 1347 { 1348 case GENERIC_REGNUM_PC: // Program Counter 1349 set = e_regSetGPR; 1350 reg = gpr_rip; 1351 break; 1352 1353 case GENERIC_REGNUM_SP: // Stack Pointer 1354 set = e_regSetGPR; 1355 reg = gpr_rsp; 1356 break; 1357 1358 case GENERIC_REGNUM_FP: // Frame Pointer 1359 set = e_regSetGPR; 1360 reg = gpr_rbp; 1361 break; 1362 1363 case GENERIC_REGNUM_FLAGS: // Processor flags register 1364 set = e_regSetGPR; 1365 reg = gpr_rflags; 1366 break; 1367 1368 case GENERIC_REGNUM_RA: // Return Address 1369 default: 1370 return false; 1371 } 1372 } 1373 1374 if (GetRegisterState(set, false) != KERN_SUCCESS) 1375 return false; 1376 1377 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1378 if (regInfo) 1379 { 1380 value->info = *regInfo; 1381 switch (set) 1382 { 1383 case e_regSetGPR: 1384 if (reg < k_num_gpr_registers) 1385 { 1386 value->value.uint64 = ((uint64_t*)(&m_state.context.gpr))[reg]; 1387 return true; 1388 } 1389 break; 1390 1391 case e_regSetFPU: 1392 if (CPUHasAVX() || FORCE_AVX_REGS) 1393 { 1394 switch (reg) 1395 { 1396 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true; 1397 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true; 1398 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true; 1399 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true; 1400 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true; 1401 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true; 1402 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true; 1403 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true; 1404 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true; 1405 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true; 1406 1407 case fpu_stmm0: 1408 case fpu_stmm1: 1409 case fpu_stmm2: 1410 case fpu_stmm3: 1411 case fpu_stmm4: 1412 case fpu_stmm5: 1413 case fpu_stmm6: 1414 case fpu_stmm7: 1415 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1416 return true; 1417 1418 case fpu_xmm0: 1419 case fpu_xmm1: 1420 case fpu_xmm2: 1421 case fpu_xmm3: 1422 case fpu_xmm4: 1423 case fpu_xmm5: 1424 case fpu_xmm6: 1425 case fpu_xmm7: 1426 case fpu_xmm8: 1427 case fpu_xmm9: 1428 case fpu_xmm10: 1429 case fpu_xmm11: 1430 case fpu_xmm12: 1431 case fpu_xmm13: 1432 case fpu_xmm14: 1433 case fpu_xmm15: 1434 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1435 return true; 1436 1437 case fpu_ymm0: 1438 case fpu_ymm1: 1439 case fpu_ymm2: 1440 case fpu_ymm3: 1441 case fpu_ymm4: 1442 case fpu_ymm5: 1443 case fpu_ymm6: 1444 case fpu_ymm7: 1445 case fpu_ymm8: 1446 case fpu_ymm9: 1447 case fpu_ymm10: 1448 case fpu_ymm11: 1449 case fpu_ymm12: 1450 case fpu_ymm13: 1451 case fpu_ymm14: 1452 case fpu_ymm15: 1453 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16); 1454 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16); 1455 return true; 1456 } 1457 } 1458 else 1459 { 1460 switch (reg) 1461 { 1462 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true; 1463 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true; 1464 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true; 1465 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true; 1466 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true; 1467 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true; 1468 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true; 1469 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true; 1470 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true; 1471 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true; 1472 1473 case fpu_stmm0: 1474 case fpu_stmm1: 1475 case fpu_stmm2: 1476 case fpu_stmm3: 1477 case fpu_stmm4: 1478 case fpu_stmm5: 1479 case fpu_stmm6: 1480 case fpu_stmm7: 1481 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1482 return true; 1483 1484 case fpu_xmm0: 1485 case fpu_xmm1: 1486 case fpu_xmm2: 1487 case fpu_xmm3: 1488 case fpu_xmm4: 1489 case fpu_xmm5: 1490 case fpu_xmm6: 1491 case fpu_xmm7: 1492 case fpu_xmm8: 1493 case fpu_xmm9: 1494 case fpu_xmm10: 1495 case fpu_xmm11: 1496 case fpu_xmm12: 1497 case fpu_xmm13: 1498 case fpu_xmm14: 1499 case fpu_xmm15: 1500 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1501 return true; 1502 } 1503 } 1504 break; 1505 1506 case e_regSetEXC: 1507 switch (reg) 1508 { 1509 case exc_trapno: value->value.uint32 = m_state.context.exc.__trapno; return true; 1510 case exc_err: value->value.uint32 = m_state.context.exc.__err; return true; 1511 case exc_faultvaddr:value->value.uint64 = m_state.context.exc.__faultvaddr; return true; 1512 } 1513 break; 1514 } 1515 } 1516 return false; 1517} 1518 1519 1520bool 1521DNBArchImplX86_64::SetRegisterValue(int set, int reg, const DNBRegisterValue *value) 1522{ 1523 if (set == REGISTER_SET_GENERIC) 1524 { 1525 switch (reg) 1526 { 1527 case GENERIC_REGNUM_PC: // Program Counter 1528 set = e_regSetGPR; 1529 reg = gpr_rip; 1530 break; 1531 1532 case GENERIC_REGNUM_SP: // Stack Pointer 1533 set = e_regSetGPR; 1534 reg = gpr_rsp; 1535 break; 1536 1537 case GENERIC_REGNUM_FP: // Frame Pointer 1538 set = e_regSetGPR; 1539 reg = gpr_rbp; 1540 break; 1541 1542 case GENERIC_REGNUM_FLAGS: // Processor flags register 1543 set = e_regSetGPR; 1544 reg = gpr_rflags; 1545 break; 1546 1547 case GENERIC_REGNUM_RA: // Return Address 1548 default: 1549 return false; 1550 } 1551 } 1552 1553 if (GetRegisterState(set, false) != KERN_SUCCESS) 1554 return false; 1555 1556 bool success = false; 1557 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1558 if (regInfo) 1559 { 1560 switch (set) 1561 { 1562 case e_regSetGPR: 1563 if (reg < k_num_gpr_registers) 1564 { 1565 ((uint64_t*)(&m_state.context.gpr))[reg] = value->value.uint64; 1566 success = true; 1567 } 1568 break; 1569 1570 case e_regSetFPU: 1571 if (CPUHasAVX() || FORCE_AVX_REGS) 1572 { 1573 switch (reg) 1574 { 1575 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1576 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1577 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break; 1578 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break; 1579 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break; 1580 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break; 1581 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break; 1582 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break; 1583 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1584 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1585 1586 case fpu_stmm0: 1587 case fpu_stmm1: 1588 case fpu_stmm2: 1589 case fpu_stmm3: 1590 case fpu_stmm4: 1591 case fpu_stmm5: 1592 case fpu_stmm6: 1593 case fpu_stmm7: 1594 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1595 success = true; 1596 break; 1597 1598 case fpu_xmm0: 1599 case fpu_xmm1: 1600 case fpu_xmm2: 1601 case fpu_xmm3: 1602 case fpu_xmm4: 1603 case fpu_xmm5: 1604 case fpu_xmm6: 1605 case fpu_xmm7: 1606 case fpu_xmm8: 1607 case fpu_xmm9: 1608 case fpu_xmm10: 1609 case fpu_xmm11: 1610 case fpu_xmm12: 1611 case fpu_xmm13: 1612 case fpu_xmm14: 1613 case fpu_xmm15: 1614 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1615 success = true; 1616 break; 1617 1618 case fpu_ymm0: 1619 case fpu_ymm1: 1620 case fpu_ymm2: 1621 case fpu_ymm3: 1622 case fpu_ymm4: 1623 case fpu_ymm5: 1624 case fpu_ymm6: 1625 case fpu_ymm7: 1626 case fpu_ymm8: 1627 case fpu_ymm9: 1628 case fpu_ymm10: 1629 case fpu_ymm11: 1630 case fpu_ymm12: 1631 case fpu_ymm13: 1632 case fpu_ymm14: 1633 case fpu_ymm15: 1634 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16); 1635 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16); 1636 return true; 1637 } 1638 } 1639 else 1640 { 1641 switch (reg) 1642 { 1643 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1644 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1645 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break; 1646 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break; 1647 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break; 1648 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break; 1649 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break; 1650 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break; 1651 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1652 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1653 1654 case fpu_stmm0: 1655 case fpu_stmm1: 1656 case fpu_stmm2: 1657 case fpu_stmm3: 1658 case fpu_stmm4: 1659 case fpu_stmm5: 1660 case fpu_stmm6: 1661 case fpu_stmm7: 1662 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1663 success = true; 1664 break; 1665 1666 case fpu_xmm0: 1667 case fpu_xmm1: 1668 case fpu_xmm2: 1669 case fpu_xmm3: 1670 case fpu_xmm4: 1671 case fpu_xmm5: 1672 case fpu_xmm6: 1673 case fpu_xmm7: 1674 case fpu_xmm8: 1675 case fpu_xmm9: 1676 case fpu_xmm10: 1677 case fpu_xmm11: 1678 case fpu_xmm12: 1679 case fpu_xmm13: 1680 case fpu_xmm14: 1681 case fpu_xmm15: 1682 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1683 success = true; 1684 break; 1685 } 1686 } 1687 break; 1688 1689 case e_regSetEXC: 1690 switch (reg) 1691 { 1692 case exc_trapno: m_state.context.exc.__trapno = value->value.uint32; success = true; break; 1693 case exc_err: m_state.context.exc.__err = value->value.uint32; success = true; break; 1694 case exc_faultvaddr:m_state.context.exc.__faultvaddr = value->value.uint64; success = true; break; 1695 } 1696 break; 1697 } 1698 } 1699 1700 if (success) 1701 return SetRegisterState(set) == KERN_SUCCESS; 1702 return false; 1703} 1704 1705 1706nub_size_t 1707DNBArchImplX86_64::GetRegisterContext (void *buf, nub_size_t buf_len) 1708{ 1709 nub_size_t size = sizeof (m_state.context); 1710 1711 if (buf && buf_len) 1712 { 1713 if (size > buf_len) 1714 size = buf_len; 1715 1716 bool force = false; 1717 if (GetGPRState(force) | GetFPUState(force) | GetEXCState(force)) 1718 return 0; 1719 ::memcpy (buf, &m_state.context, size); 1720 } 1721 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1722 // Return the size of the register context even if NULL was passed in 1723 return size; 1724} 1725 1726nub_size_t 1727DNBArchImplX86_64::SetRegisterContext (const void *buf, nub_size_t buf_len) 1728{ 1729 nub_size_t size = sizeof (m_state.context); 1730 if (buf == NULL || buf_len == 0) 1731 size = 0; 1732 1733 if (size) 1734 { 1735 if (size > buf_len) 1736 size = buf_len; 1737 1738 ::memcpy (&m_state.context, buf, size); 1739 SetGPRState(); 1740 SetFPUState(); 1741 SetEXCState(); 1742 } 1743 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1744 return size; 1745} 1746 1747 1748kern_return_t 1749DNBArchImplX86_64::GetRegisterState(int set, bool force) 1750{ 1751 switch (set) 1752 { 1753 case e_regSetALL: return GetGPRState(force) | GetFPUState(force) | GetEXCState(force); 1754 case e_regSetGPR: return GetGPRState(force); 1755 case e_regSetFPU: return GetFPUState(force); 1756 case e_regSetEXC: return GetEXCState(force); 1757 default: break; 1758 } 1759 return KERN_INVALID_ARGUMENT; 1760} 1761 1762kern_return_t 1763DNBArchImplX86_64::SetRegisterState(int set) 1764{ 1765 // Make sure we have a valid context to set. 1766 if (RegisterSetStateIsValid(set)) 1767 { 1768 switch (set) 1769 { 1770 case e_regSetALL: return SetGPRState() | SetFPUState() | SetEXCState(); 1771 case e_regSetGPR: return SetGPRState(); 1772 case e_regSetFPU: return SetFPUState(); 1773 case e_regSetEXC: return SetEXCState(); 1774 default: break; 1775 } 1776 } 1777 return KERN_INVALID_ARGUMENT; 1778} 1779 1780bool 1781DNBArchImplX86_64::RegisterSetStateIsValid (int set) const 1782{ 1783 return m_state.RegsAreValid(set); 1784} 1785 1786 1787 1788#endif // #if defined (__i386__) || defined (__x86_64__) 1789