DNBArchImplX86_64.cpp revision f4933ed8d0fa218b5db476ecd881ec67495037f3
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- DNBArchImplX86_64.cpp -----------------------------------*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 7868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// 8868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Created by Greg Clayton on 6/25/07. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 14424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#if defined (__i386__) || defined (__x86_64__) 15424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#include <sys/cdefs.h> 172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include <sys/types.h> 182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include <sys/sysctl.h> 19868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 20868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)#include "MacOSX/x86_64/DNBArchImplX86_64.h" 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "DNBLog.h" 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "MachThread.h" 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "MachProcess.h" 247dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch#include <mach/mach.h> 252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include <stdlib.h> 26b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 273551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)#if defined (LLDB_DEBUGSERVER_RELEASE) || defined (LLDB_DEBUGSERVER_DEBUG) 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)enum debugState { 2958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) debugStateUnknown, 3058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) debugStateOff, 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) debugStateOn 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 341320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tuccistatic debugState sFPUDebugState = debugStateUnknown; 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)static debugState sAVXForceState = debugStateUnknown; 36c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 37cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)static bool DebugFPURegs () 388bcbed890bc3ce4d7a057a8f32cab53fa534672eTorne (Richard Coles){ 39effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch if (sFPUDebugState == debugStateUnknown) 40116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { 41116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (getenv("DNB_DEBUG_FPU_REGS")) 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) sFPUDebugState = debugStateOn; 431320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci else 44116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch sFPUDebugState = debugStateOff; 455f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) } 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 47f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return (sFPUDebugState == debugStateOn); 48f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)} 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 505f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)static bool ForceAVXRegs () 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 525f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (sFPUDebugState == debugStateUnknown) 532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 54868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS")) 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) sAVXForceState = debugStateOn; 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) else 570529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch sAVXForceState = debugStateOff; 580529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (sAVXForceState == debugStateOn); 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 621320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 631320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci#define DEBUG_FPU_REGS (DebugFPURegs()) 646d86b77056ed63eb6871182f42a9fd5f07550f90Torne (Richard Coles)#define FORCE_AVX_REGS (ForceAVXRegs()) 65cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)#else 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define DEBUG_FPU_REGS (0) 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define FORCE_AVX_REGS (0) 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)extern "C" bool 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)CPUHasAVX() 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 742a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) enum AVXPresence 751320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci { 761320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci eAVXUnknown = -1, 775d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) eAVXNotPresent = 0, 7858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) eAVXPresent = 1 7923730a6e56a168d1879203e4b3819bb36e3d8f1fTorne (Richard Coles) }; 805d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 815d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) static AVXPresence g_has_avx = eAVXUnknown; 821e9bf3e0803691d0a228da41fc608347b6db4340Torne (Richard Coles) if (g_has_avx == eAVXUnknown) 83f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) { 845d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) g_has_avx = eAVXNotPresent; 855f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 86c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // Only xnu-2020 or later has AVX support, any versions before 871320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // this have a busted thread_get_state RPC where it would truncate 882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // the thread state buffer (<rdar://problem/10122874>). So we need to 89f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // verify the kernel version number manually or disable AVX support. 90c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch int mib[2]; 915d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) char buffer[1024]; 921320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci size_t length = sizeof(buffer); 93cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) uint64_t xnu_version = 0; 94c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch mib[0] = CTL_KERN; 95f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) mib[1] = KERN_VERSION; 96f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) int err = ::sysctl(mib, 2, &buffer, &length, NULL, 0); 971320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (err == 0) 98cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) { 9903b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) const char *xnu = strstr (buffer, "xnu-"); 1001320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (xnu) 1015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 1025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const char *xnu_version_cstr = xnu + 4; 10358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) xnu_version = strtoull (xnu_version_cstr, NULL, 0); 10458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) if (xnu_version >= 2020 && xnu_version != ULLONG_MAX) 1055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 1065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (::HasAVX()) 107a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { 1080529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch g_has_avx = eAVXPresent; 1090529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 1100529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 1110529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 1120529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 113a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "CPUHasAVX(): g_has_avx = %i (err = %i, errno = %i, xnu_version = %llu)\n", g_has_avx, err, errno, xnu_version); 114a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 115a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 116a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return (g_has_avx == eAVXPresent); 117a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)} 1183551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 1193551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)uint64_t 120a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)DNBArchImplX86_64::GetPC(uint64_t failValue) 121a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles){ 122a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // Get program counter 1233551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) if (GetGPRState(false) == KERN_SUCCESS) 1243551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return m_state.context.gpr.__rip; 125a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return failValue; 1265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1274e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 1284e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)kern_return_t 1294e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)DNBArchImplX86_64::SetPC(uint64_t value) 1304e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles){ 1314e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) // Get program counter 1324e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) kern_return_t err = GetGPRState(false); 1334e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) if (err == KERN_SUCCESS) 1344e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) { 1354e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) m_state.context.gpr.__rip = value; 1364e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) err = SetGPRState(); 1374e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) } 1384e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) return err == KERN_SUCCESS; 1394e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)} 1404e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 1414e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)uint64_t 1424e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)DNBArchImplX86_64::GetSP(uint64_t failValue) 1434e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles){ 1444e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) // Get stack pointer 1454e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) if (GetGPRState(false) == KERN_SUCCESS) 1464e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) return m_state.context.gpr.__rsp; 1474e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) return failValue; 1484e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)} 1494e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 1504e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)// Uncomment the value below to verify the values in the debugger. 1514e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)//#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 1524e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) 1534e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)kern_return_t 1544e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)DNBArchImplX86_64::GetGPRState(bool force) 1554e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles){ 1564e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) if (force || m_state.GetError(e_regSetGPR, Read)) 1574e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) { 1584e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 1595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (GetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 1605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#if DEBUG_GPR_VALUES 1625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rax = ('a' << 8) + 'x'; 1635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rbx = ('b' << 8) + 'x'; 1645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rcx = ('c' << 8) + 'x'; 1655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rdx = ('d' << 8) + 'x'; 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rdi = ('d' << 8) + 'i'; 1675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rsi = ('s' << 8) + 'i'; 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rbp = ('b' << 8) + 'p'; 1695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rsp = ('s' << 8) + 'p'; 1700f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) m_state.context.gpr.__r8 = ('r' << 8) + '8'; 1710f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) m_state.context.gpr.__r9 = ('r' << 8) + '9'; 1722a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.gpr.__r10 = ('r' << 8) + 'a'; 17358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) m_state.context.gpr.__r11 = ('r' << 8) + 'b'; 1745d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.gpr.__r12 = ('r' << 8) + 'c'; 175effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch m_state.context.gpr.__r13 = ('r' << 8) + 'd'; 176f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) m_state.context.gpr.__r14 = ('r' << 8) + 'e'; 1771320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci m_state.context.gpr.__r15 = ('r' << 8) + 'f'; 1785d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.gpr.__rip = ('i' << 8) + 'p'; 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rflags = ('f' << 8) + 'l'; 1805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__cs = ('c' << 8) + 's'; 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__fs = ('f' << 8) + 's'; 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__gs = ('g' << 8) + 's'; 1835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.SetError(e_regSetGPR, Read, 0); 1845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#else 1855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) mach_msg_type_number_t count = e_regSetWordSizeGPR; 1865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count)); 1875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 1885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 1895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 1900f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 1910f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 1922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) "\n\trip = %16.16llx" 19358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 1945d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_thread->ThreadID(), x86_THREAD_STATE64, x86_THREAD_STATE64_COUNT, 195effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch m_state.GetError(e_regSetGPR, Read), 196f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 1971320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 1985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 1995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 2005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 2015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 2027dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch m_state.context.gpr.__cs,m_state.context.gpr.__fs, m_state.context.gpr.__gs); 203c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 204c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // DNBLogThreadedIf (LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 205c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // "\n\trax = %16.16llx" 206c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // "\n\trbx = %16.16llx" 207c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // "\n\trcx = %16.16llx" 2085c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // "\n\trdx = %16.16llx" 2095c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // "\n\trdi = %16.16llx" 2105c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // "\n\trsi = %16.16llx" 2115c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu // "\n\trbp = %16.16llx" 2125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // "\n\trsp = %16.16llx" 2135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // "\n\t r8 = %16.16llx" 2143551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) // "\n\t r9 = %16.16llx" 2155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // "\n\tr10 = %16.16llx" 2165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // "\n\tr11 = %16.16llx" 2171320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // "\n\tr12 = %16.16llx" 2181320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // "\n\tr13 = %16.16llx" 2191320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // "\n\tr14 = %16.16llx" 2201320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // "\n\tr15 = %16.16llx" 2213551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) // "\n\trip = %16.16llx" 2225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // "\n\tflg = %16.16llx" 223a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // "\n\t cs = %16.16llx" 2245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // "\n\t fs = %16.16llx" 225a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // "\n\t gs = %16.16llx", 226f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_thread->ThreadID(), 227f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // x86_THREAD_STATE64, 228f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // x86_THREAD_STATE64_COUNT, 229f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.GetError(e_regSetGPR, Read), 230f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__rax, 2315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // m_state.context.gpr.__rbx, 2325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // m_state.context.gpr.__rcx, 233f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__rdx, 234010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // m_state.context.gpr.__rdi, 235010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // m_state.context.gpr.__rsi, 236010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // m_state.context.gpr.__rbp, 237010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // m_state.context.gpr.__rsp, 238f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__r8, 239f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__r9, 240f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__r10, 241f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__r11, 242f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) // m_state.context.gpr.__r12, 243010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // m_state.context.gpr.__r13, 2445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // m_state.context.gpr.__r14, 2455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // m_state.context.gpr.__r15, 2465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // m_state.context.gpr.__rip, 2475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // m_state.context.gpr.__rflags, 2485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // m_state.context.gpr.__cs, 2495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // m_state.context.gpr.__fs, 250116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // m_state.context.gpr.__gs); 2515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 252116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch } 253116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return m_state.GetError(e_regSetGPR, Read); 254116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch} 255116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 2565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Uncomment the value below to verify the values in the debugger. 2575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//#define DEBUG_FPU_REGS 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 2582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2591320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tuccikern_return_t 2601320f92c476a1ad9d19dba2a48c72b75566198e9Primiano TucciDNBArchImplX86_64::GetFPUState(bool force) 2611320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci{ 2625d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (force || m_state.GetError(e_regSetFPU, Read)) 2635d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { 2645d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (DEBUG_FPU_REGS) { 2655d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (CPUHasAVX() || FORCE_AVX_REGS) 2665d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { 2675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.avx.__fpu_reserved[0] = -1; 2685d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_reserved[1] = -1; 269a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234; 270a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678; 2715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ftw = 1; 2725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX; 2735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_fop = 2; 2745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ip = 3; 2752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.avx.__fpu_cs = 4; 2765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.avx.__fpu_rsrv2 = 5; 2772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.avx.__fpu_dp = 6; 2785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ds = 7; 2791320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX; 2801320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci m_state.context.fpu.avx.__fpu_mxcsr = 8; 2811320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci m_state.context.fpu.avx.__fpu_mxcsrmask = 9; 2825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int i; 283116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch for (i=0; i<16; ++i) 284116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { 285116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (i<10) 286116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { 287116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 288116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 289116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 290116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 291116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 2926e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 2936e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 2946e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 2956e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) } 296116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch else 297116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { 298116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 299116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 300cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 30103b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 302cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 303cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 304cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 30503b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 30603b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) } 30703b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) 30803b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0'; 309cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1'; 310cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2'; 311cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3'; 312cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4'; 313cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5'; 314cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6'; 315cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7'; 316a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8'; 3174e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9'; 3187d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 3197d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 3207d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 321a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 32290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 32390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 32490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 32590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0'; 32690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1'; 327116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2'; 328116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3'; 329116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4'; 33090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5'; 33190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6'; 33290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7'; 3335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8'; 334a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9'; 3355d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A'; 3365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B'; 3375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C'; 3385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D'; 3395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E'; 3405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F'; 3415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 3425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i) 3435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN; 3445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__fpu_reserved1 = -1; 3455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i) 3465d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; 3475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.SetError(e_regSetFPU, Read, 0); 3485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 3495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) else 3505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { 3515d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; 3525d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; 3535d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; 3545d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; 3554e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_ftw = 1; 3562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; 3575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_fop = 2; 3585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_ip = 3; 3595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_cs = 4; 3605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; 361a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_dp = 6; 3625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_ds = 7; 3635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; 3645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_mxcsr = 8; 3655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; 3663551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) int i; 3675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) for (i=0; i<16; ++i) 3685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 3693551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) if (i<10) 370a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { 3715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 3725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 3735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 3745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 3755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 3765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 3775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 3785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 3795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3803551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) else 3813551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { 3825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 3835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 3845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 385a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 386a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 3875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 3885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 3895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 3905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; 3932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; 3942a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; 3952a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; 3965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; 3975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; 3983551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; 3992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; 4002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8'; 401116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9'; 4025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 4035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 4045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 4055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 4065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 407c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 408c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch } 409c5cede9ae108bb15f6b7a8aea21c7e1fefa2834cBen Murdoch for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) 41058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; 41158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) m_state.context.fpu.no_avx.__fpu_reserved1 = -1; 4120529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch m_state.SetError(e_regSetFPU, Read, 0); 4130529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 4140529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 4150529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch else 4160529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch { 4170529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch if (CPUHasAVX() || FORCE_AVX_REGS) 4180529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch { 4195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) mach_msg_type_number_t count = e_regSetWordSizeAVX; 42058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count)); 42158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &avx, %u (%u passed in) carp) => 0x%8.8x", 4225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_thread->ThreadID(), __x86_64_AVX_STATE, (uint32_t)count, 4235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) e_regSetWordSizeAVX, m_state.GetError(e_regSetFPU, Read)); 4245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 42558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) else 4260f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) { 42758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) mach_msg_type_number_t count = e_regSetWordSizeFPU; 4280f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count)); 4290f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &fpu, %u (%u passed in) => 0x%8.8x", 4305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) m_thread->ThreadID(), __x86_64_FLOAT_STATE, (uint32_t)count, 4310f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) e_regSetWordSizeFPU, m_state.GetError(e_regSetFPU, Read)); 4320f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) } 4330f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) } 4340f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) } 4350f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) return m_state.GetError(e_regSetFPU, Read); 4360f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles)} 4370f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) 4380f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles)kern_return_t 43958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)DNBArchImplX86_64::GetEXCState(bool force) 44058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles){ 44158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) if (force || m_state.GetError(e_regSetEXC, Read)) 44258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) { 44358537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) mach_msg_type_number_t count = e_regSetWordSizeEXC; 44458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count)); 44558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 446a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return m_state.GetError(e_regSetEXC, Read); 4475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 4485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4493551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)kern_return_t 450a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)DNBArchImplX86_64::SetGPRState() 4515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 4523551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 4535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 4545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR)); 4565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf (LOG_THREAD, "::thread_set_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 4575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 4585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 4595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 4605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 4615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\trip = %16.16llx" 4625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 4635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_thread->ThreadID(), __x86_64_THREAD_STATE, e_regSetWordSizeGPR, 4642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.GetError(e_regSetGPR, Write), 4652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 4665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 4675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 4682a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 4695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 4702a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 4715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__cs, m_state.context.gpr.__fs, m_state.context.gpr.__gs); 472f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return m_state.GetError(e_regSetGPR, Write); 473f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)} 474f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 475f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)kern_return_t 476f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)DNBArchImplX86_64::SetFPUState() 477f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles){ 4781320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (DEBUG_FPU_REGS) 479f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) { 4802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.SetError(e_regSetFPU, Write, 0); 4815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return m_state.GetError(e_regSetFPU, Write); 4821320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci } 4831320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci else 4841320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci { 4851320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (CPUHasAVX() || FORCE_AVX_REGS) 4861320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci { 4871320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX)); 4882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return m_state.GetError(e_regSetFPU, Write); 4895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 4902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) else 4915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 4922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPU)); 4935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return m_state.GetError(e_regSetFPU, Write); 4942a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 4955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 4962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} 4975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4982a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)kern_return_t 4995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::SetEXCState() 5003551c9c881056c480085172ff9840cab31610854Torne (Richard Coles){ 5013551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC)); 5022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return m_state.GetError(e_regSetEXC, Write); 5035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 5042a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 5055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)kern_return_t 5062a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)DNBArchImplX86_64::GetDBGState(bool force) 5075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 5082a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (force || m_state.GetError(e_regSetDBG, Read)) 5095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 5100529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch mach_msg_type_number_t count = e_regSetWordSizeDBG; 5110529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count)); 5122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 5135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return m_state.GetError(e_regSetDBG, Read); 514cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles)} 515cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) 5162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)kern_return_t 5175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::SetDBGState() 5182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles){ 5195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG)); 5201320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return m_state.GetError(e_regSetDBG, Write); 5211320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci} 5222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 5232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)void 5242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)DNBArchImplX86_64::ThreadWillResume() 5255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 5262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Do we need to step this thread? If so, let the mach thread tell us so. 5275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (m_thread->IsStepping()) 5282a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 5292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // This is the primary thread, let the arch do anything it needs 5302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) EnableHardwareSingleStep(true); 5315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 5322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 5335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Reset the debug status register, if necessary, before we resume. 5342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) kern_return_t kret = GetDBGState(false); 535f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret); 536116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (kret != KERN_SUCCESS) 537116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return; 5385f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 539116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DBG &debug_state = m_state.context.dbg; 540010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) bool need_reset = false; 541010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) uint32_t i, num = NumSupportedHardwareWatchpoints(); 542010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) for (i = 0; i < num; ++i) 543f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) if (IsWatchpointHit(debug_state, i)) 544f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) need_reset = true; 545f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) 546f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) if (need_reset) 547010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) { 548a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) ClearWatchpointHits(debug_state); 549a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) kret = SetDBGState(); 550f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret); 551f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) } 552f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)} 553f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 5542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)bool 5555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::ThreadDidStop() 5562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles){ 5575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool success = true; 5582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 5595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.InvalidateAllRegisterStates(); 5602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 5615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Are we stepping a single instruction? 5622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (GetGPRState(true) == KERN_SUCCESS) 5635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 5640529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch // We are single stepping, was this the primary thread? 565010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) if (m_thread->IsStepping()) 566010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) { 567010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // This was the primary thread, we need to clear the trace 568f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // bit if so. 569f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 570f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) } 571f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) else 572f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) { 5730529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch // The MachThread will automatically restore the suspend count 574010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // in ThreadDidStop(), so we don't need to do anything here if 575010d83a9304c5a91596085d917d248abff47903aTorne (Richard Coles) // we weren't the primary thread the last time 5762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 5775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 5782a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return success; 5795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 5802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 5815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)bool 5822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)DNBArchImplX86_64::NotifyException(MachException::Data& exc) 5835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 5842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) switch (exc.exc_type) 5855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 5865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case EXC_BAD_ACCESS: 5875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 5885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case EXC_BAD_INSTRUCTION: 5892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) break; 5905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case EXC_ARITHMETIC: 5915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 5925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case EXC_EMULATION: 5932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) break; 5940f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) case EXC_SOFTWARE: 5952a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) break; 5962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) case EXC_BREAKPOINT: 5972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) 5982a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 5992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // exc_code = EXC_I386_BPT 6002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // 6012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS); 6022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (pc != INVALID_NUB_ADDRESS && pc > 0) 603f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) { 604f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) pc -= 1; 6055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Check for a breakpoint at one byte prior to the current PC value 6065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // since the PC will be just past the trap. 6075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 6085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) nub_break_t breakID = m_thread->Process()->Breakpoints().FindIDByAddress(pc); 6095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (NUB_BREAK_ID_IS_VALID(breakID)) 6105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 6115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Backup the PC for i386 since the trap was taken and the PC 6125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // is at the address following the single byte trap instruction. 6135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (m_state.context.gpr.__rip > 0) 614116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { 615116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch m_state.context.gpr.__rip = pc; 616116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch // Write the new PC back out 6175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SetGPRState (); 6185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 619a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 6205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 6215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 6225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 6235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1) 6245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 625a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // exc_code = EXC_I386_SGL 6265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // 6275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Check whether this corresponds to a watchpoint hit event. 628a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // If yes, set the exc_sub_code to the data break address. 6295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) nub_addr_t addr = 0; 6305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) uint32_t hw_index = GetHardwareWatchpointHit(addr); 631a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) if (hw_index != INVALID_NUB_HW_INDEX) 6322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 6332a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) exc.exc_data[1] = addr; 634a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) // Piggyback the hw_index in the exc.data. 6355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) exc.exc_data.push_back(hw_index); 6365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 637a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 6381320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return true; 6391320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci } 6401320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci break; 6415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case EXC_SYSCALL: 6425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 643a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) case EXC_MACH_SYSCALL: 6445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 6455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case EXC_RPC_ALERT: 646a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) break; 6470529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch } 6480529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch return false; 6490529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch} 6505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 6515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)uint32_t 652a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)DNBArchImplX86_64::NumSupportedHardwareWatchpoints() 653cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles){ 654cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) // Available debug address registers: dr0, dr1, dr2, dr3. 655cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) return 4; 6565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 6575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 658a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)static uint32_t 6595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)size_and_rw_bits(nub_size_t size, bool read, bool write) 6605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 661a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) uint32_t rw; 6622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (read) { 6632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) rw = 0x3; // READ or READ/WRITE 664a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) } else if (write) { 6655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) rw = 0x1; // WRITE 6665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } else { 667a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) assert(0 && "read and write cannot both be false"); 6685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 6695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 670a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) switch (size) { 6715c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu case 1: 6725c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu return rw; 673a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) case 2: 674116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return (0x1 << 2) | rw; 675116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case 4: 676116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch return (0x3 << 2) | rw; 6775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case 8: 6785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (0x2 << 2) | rw; 67958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) default: 68058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) assert(0 && "invalid size, must be one of 1, 2, 4, or 8"); 68158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 68258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles)} 6835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void 6845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write) 6855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 6865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Set both dr7 (debug control register) and dri (debug address register). 6875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 6885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr7{7-0} encodes the local/gloabl enable bits: 6895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // global enable --. .-- local enable 6905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // | | 6915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // v v 6925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr0 -> bits{1-0} 6935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr1 -> bits{3-2} 6945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr2 -> bits{5-4} 6955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr3 -> bits{7-6} 6965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // 6975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr7{31-16} encodes the rw/len bits: 6985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // b_x+3, b_x+2, b_x+1, b_x 6995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // where bits{x+1, x} => rw 7005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io read-or-write (unused) 7015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // and bits{x+3, x+2} => len 7025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte 7035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // 7045f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // dr0 -> bits{19-16} 7055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr1 -> bits{23-20} 7065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr2 -> bits{27-24} 707effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch // dr3 -> bits{31-28} 7085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) debug_state.__dr7 |= (1 << (2*hw_index) | 7095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) size_and_rw_bits(size, read, write) << (16+4*hw_index)); 7100f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) switch (hw_index) { 7110f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) case 0: 7120f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) debug_state.__dr0 = addr; break; 7130f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) case 1: 7140f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) debug_state.__dr1 = addr; break; 7150f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) case 2: 7160f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) debug_state.__dr2 = addr; break; 7170f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) case 3: 7185f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) debug_state.__dr3 = addr; break; 7195f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) default: 7205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 7215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 7225f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return; 723424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)} 724424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 725424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)void 726424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DNBArchImplX86_64::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) 727424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles){ 728424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) debug_state.__dr7 &= ~(3 << (2*hw_index)); 729a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) switch (hw_index) { 730424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) case 0: 7315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) debug_state.__dr0 = 0; break; 7325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case 1: 7335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) debug_state.__dr1 = 0; break; 7345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case 2: 7355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) debug_state.__dr2 = 0; break; 736f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) case 3: 737f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) debug_state.__dr3 = 0; break; 738f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) default: 739f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 740f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) } 741f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return; 742f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)} 743f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) 744f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)bool 745f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)DNBArchImplX86_64::IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index) 746f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles){ 747f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // Check dr7 (debug control register) for local/global enable bits: 748f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // global enable --. .-- local enable 749f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // | | 750f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // v v 7515f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // dr0 -> bits{1-0} 7525f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // dr1 -> bits{3-2} 753f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // dr2 -> bits{5-4} 754f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) // dr3 -> bits{7-6} 755f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return (debug_state.__dr7 & (3 << (2*hw_index))) == 0; 756effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch} 7575c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu 758effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch// Resets local copy of debug status register to wait for the next debug excpetion. 759effb81e5f8246d0db0270817048dc992db66e9fbBen Murdochvoid 760effb81e5f8246d0db0270817048dc992db66e9fbBen MurdochDNBArchImplX86_64::ClearWatchpointHits(DBG &debug_state) 7611320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci{ 7621320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci // See also IsWatchpointHit(). 7631320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci debug_state.__dr6 = 0; 7641320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return; 7655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 7665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 7675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)bool 7685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::IsWatchpointHit(const DBG &debug_state, uint32_t hw_index) 7695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 7705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Check dr6 (debug status register) whether a watchpoint hits: 7715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // is watchpoint hit? 7725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // | 7735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // v 7745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // dr0 -> bits{0} 775effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch // dr1 -> bits{1} 776effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch // dr2 -> bits{2} 777effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch // dr3 -> bits{3} 7785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (debug_state.__dr6 & (1 << hw_index)); 7795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 7805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 7815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)nub_addr_t 7825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::GetWatchAddress(const DBG &debug_state, uint32_t hw_index) 783116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch{ 784116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch switch (hw_index) { 7855f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) case 0: 7865f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) return debug_state.__dr0; 787116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch case 1: 7885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return debug_state.__dr1; 7895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case 2: 7905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return debug_state.__dr2; 7915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case 3: 7925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return debug_state.__dr3; 7935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) default: 7945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 7955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 7965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 7975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 7985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)uint32_t 7995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write) 8002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles){ 8012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(addr = 0x%llx, size = %zu, read = %u, write = %u)", (uint64_t)addr, size, read, write); 8022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 8032a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 804868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 8052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Can only watch 1, 2, 4, or 8 bytes. 806868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) if (!(size == 1 || size == 2 || size == 4 || size == 8)) 807868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) return INVALID_NUB_HW_INDEX; 808868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 8095f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // We must watch for either read or write 8105f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) if (read == false && write == false) 811868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) return INVALID_NUB_HW_INDEX; 8122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 8132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Read the debug state 8142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) kern_return_t kret = GetDBGState(false); 815868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 8162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (kret == KERN_SUCCESS) 8172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 8185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Check to make sure we have the needed hardware support 8195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) uint32_t i = 0; 8205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 8215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DBG &debug_state = m_state.context.dbg; 8225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) for (i = 0; i < num_hw_watchpoints; ++i) 8232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 8247d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) if (IsWatchpointVacant(debug_state, i)) 8255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 8265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 8275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 8285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // See if we found an available hw breakpoint slot above 829116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch if (i < num_hw_watchpoints) 8305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 8315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Modify our local copy of the debug state, first. 8325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) SetWatchpoint(debug_state, i, addr, size, read, write); 8335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Now set the watch point in the inferior. 8343551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) kret = SetDBGState(); 8351320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret); 8361320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 8371320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (kret == KERN_SUCCESS) 8381320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return i; 8393551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) } 8405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) else 8412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { 8422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints); 8435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 8443551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) } 8455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return INVALID_NUB_HW_INDEX; 8461320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci} 8475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 8485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)bool 8495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)DNBArchImplX86_64::DisableHardwareWatchpoint (uint32_t hw_index) 8505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles){ 8515d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) kern_return_t kret = GetDBGState(false); 8521320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 8535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 8547d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) if (kret == KERN_SUCCESS) 8557d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) { 8565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DBG &debug_state = m_state.context.dbg; 8575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (hw_index < num_hw_points && !IsWatchpointVacant(debug_state, hw_index)) 8585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 8595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Modify our local copy of the debug state, first. 8605d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) ClearWatchpoint(debug_state, hw_index); 8615d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Now disable the watch point in the inferior. 8621320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci kret = SetDBGState(); 8635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::DisableHardwareWatchpoint( %u )", 8647d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) hw_index); 8657d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 8665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (kret == KERN_SUCCESS) 8675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 8685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 8695d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 8705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 8715d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)} 8725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 8731320f92c476a1ad9d19dba2a48c72b75566198e9Primiano TucciDNBArchImplX86_64::DBG DNBArchImplX86_64::Global_Debug_State = {0,0,0,0,0,0,0,0}; 8745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)bool DNBArchImplX86_64::Valid_Global_Debug_State = false; 8757d4cd473f85ac64c3747c96c277f9e506a0d2246Torne (Richard Coles) 8765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Use this callback from MachThread, which in turn was called from MachThreadList, to update 8775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// the global view of the hardware watchpoint state, so that when new thread comes along, they 8785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// get to inherit the existing hardware watchpoint state. 8795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)void 8805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::HardwareWatchpointStateChanged () 8815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 882f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) Global_Debug_State = m_state.context.dbg; 8835f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) Valid_Global_Debug_State = true; 8845f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)} 8855f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 8862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// Iterate through the debug status register; return the index of the first hit. 887f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles)uint32_t 8882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)DNBArchImplX86_64::GetHardwareWatchpointHit(nub_addr_t &addr) 8895f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles){ 8905f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) // Read the debug state 8912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) kern_return_t kret = GetDBGState(true); 8925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret); 8935c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu if (kret == KERN_SUCCESS) 8945c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu { 8955c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu DBG &debug_state = m_state.context.dbg; 896cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) uint32_t i, num = NumSupportedHardwareWatchpoints(); 8970529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch for (i = 0; i < num; ++i) 8985c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu { 8995c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu if (IsWatchpointHit(debug_state, i)) 9005c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu { 9015c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu addr = GetWatchAddress(debug_state, i); 9020529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch DNBLogThreadedIf(LOG_WATCHPOINTS, 9030529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch "DNBArchImplX86_64::GetHardwareWatchpointHit() found => %u (addr = 0x%llx).", 9041320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci i, 9051320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci (uint64_t)addr); 9061320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci return i; 9075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 9085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 9093551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) } 9103551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return INVALID_NUB_HW_INDEX; 9115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 9125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 9135d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// Set the single step bit in the processor status register. 9145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)kern_return_t 9155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)DNBArchImplX86_64::EnableHardwareSingleStep (bool enable) 9165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles){ 917effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch if (GetGPRState(false) == KERN_SUCCESS) 918effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch { 919effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch const uint32_t trace_bit = 0x100u; 9205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) if (enable) 9215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rflags |= trace_bit; 9225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) else 9235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) m_state.context.gpr.__rflags &= ~trace_bit; 9243551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return SetGPRState(); 9252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 926f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) return m_state.GetError(e_regSetGPR, Read); 9275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 9285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 9295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 9303551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)//---------------------------------------------------------------------- 9313551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// Register information defintions 9323551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)//---------------------------------------------------------------------- 9335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 9345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)enum 9353551c9c881056c480085172ff9840cab31610854Torne (Richard Coles){ 9363551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gpr_rax = 0, 9375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rbx, 9385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rcx, 9395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rdx, 9405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rdi, 9415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rsi, 9425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rbp, 9435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rsp, 9445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r8, 9455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r9, 9465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r10, 9475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r11, 9485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r12, 9495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r13, 9505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r14, 9515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_r15, 9525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rip, 9535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_rflags, 9545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_cs, 9555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gpr_fs, 9565d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gpr_gs, 9575d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) k_num_gpr_regs 9585d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)}; 9595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 9605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)enum { 9615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_fcw, 9625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_fsw, 9635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ftw, 9645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_fop, 9656e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) fpu_ip, 9665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_cs, 9675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_dp, 9685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ds, 9695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_mxcsr, 9706e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) fpu_mxcsrmask, 9715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_stmm0, 9725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_stmm1, 9733551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) fpu_stmm2, 9743551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) fpu_stmm3, 9752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) fpu_stmm4, 9762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) fpu_stmm5, 9772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) fpu_stmm6, 978a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) fpu_stmm7, 9792a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) fpu_xmm0, 980f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) fpu_xmm1, 981a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) fpu_xmm2, 982a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) fpu_xmm3, 9832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) fpu_xmm4, 9842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) fpu_xmm5, 9853551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) fpu_xmm6, 9863551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) fpu_xmm7, 9875d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) fpu_xmm8, 9885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_xmm9, 989116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch fpu_xmm10, 9905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_xmm11, 9915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_xmm12, 9921320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_xmm13, 9931320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_xmm14, 9941320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_xmm15, 9951320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm0, 9961320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm1, 9971320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm2, 9981320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm3, 9991320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm4, 10001320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm5, 10011320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm6, 10021320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm7, 10031320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci fpu_ymm8, 10043551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) fpu_ymm9, 10053551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) fpu_ymm10, 10065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ymm11, 10075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ymm12, 10085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ymm13, 10095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ymm14, 10105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_ymm15, 10115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) k_num_fpu_regs, 10125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1013a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) // Aliases 1014a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) fpu_fctrl = fpu_fcw, 1015a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) fpu_fstat = fpu_fsw, 1016a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) fpu_ftag = fpu_ftw, 1017a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) fpu_fiseg = fpu_cs, 1018a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) fpu_fioff = fpu_ip, 10195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_foseg = fpu_ds, 10205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) fpu_fooff = fpu_dp 10215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 10225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1023a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)enum { 10245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) exc_trapno, 1025a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) exc_err, 10265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) exc_faultvaddr, 10275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) k_num_exc_regs, 10285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 10295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 10305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 10315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)enum gcc_dwarf_regnums 10325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 10335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rax = 0, 1034a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) gcc_dwarf_rdx = 1, 10355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rcx = 2, 10365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rbx = 3, 10375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rsi = 4, 10385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rdi = 5, 10395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rbp = 6, 10405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_rsp = 7, 10415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r8, 10425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r9, 10435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r10, 10445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r11, 10455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r12, 10465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r13, 10475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r14, 10485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_r15, 10493551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gcc_dwarf_rip, 10505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm0, 10515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm1, 10525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm2, 10535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm3, 10545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm4, 10555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm5, 10565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm6, 10575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm7, 10585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm8, 10595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm9, 10605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm10, 10615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm11, 10625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm12, 10635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm13, 10645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm14, 10655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_xmm15, 10665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_stmm0, 10675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_stmm1, 10685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_stmm2, 10695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_stmm3, 10702a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gcc_dwarf_stmm4, 10712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gcc_dwarf_stmm5, 10725d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gcc_dwarf_stmm6, 10735d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gcc_dwarf_stmm7, 10745d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gcc_dwarf_ymm0 = gcc_dwarf_xmm0, 10755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_ymm1 = gcc_dwarf_xmm1, 10765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_ymm2 = gcc_dwarf_xmm2, 10770529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm3 = gcc_dwarf_xmm3, 10780529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm4 = gcc_dwarf_xmm4, 10790529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm5 = gcc_dwarf_xmm5, 10800529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm6 = gcc_dwarf_xmm6, 10810529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm7 = gcc_dwarf_xmm7, 10820529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm8 = gcc_dwarf_xmm8, 10830529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm9 = gcc_dwarf_xmm9, 10840529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm10 = gcc_dwarf_xmm10, 10850529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm11 = gcc_dwarf_xmm11, 10860529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm12 = gcc_dwarf_xmm12, 10870529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm13 = gcc_dwarf_xmm13, 10880529e5d033099cbfc42635f6f6183833b09dff6eBen Murdoch gcc_dwarf_ymm14 = gcc_dwarf_xmm14, 10895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gcc_dwarf_ymm15 = gcc_dwarf_xmm15 10903551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)}; 10915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 10925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)enum gdb_regnums 10935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 10945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rax = 0, 10955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rbx = 1, 10965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rcx = 2, 10975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rdx = 3, 10985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rsi = 4, 10995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rdi = 5, 110090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) gdb_rbp = 6, 1101a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) gdb_rsp = 7, 1102a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) gdb_r8 = 8, 11035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_r9 = 9, 11045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_r10 = 10, 11055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_r11 = 11, 11065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_r12 = 12, 11075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gdb_r13 = 13, 11085d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gdb_r14 = 14, 11095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_r15 = 15, 11105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_rip = 16, 1111cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_rflags = 17, 1112cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_cs = 18, 1113cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_ss = 19, 1114cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_ds = 20, 1115cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_es = 21, 1116cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_fs = 22, 1117cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_gs = 23, 1118cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_stmm0 = 24, 1119cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_stmm1 = 25, 1120cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_stmm2 = 26, 1121cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_stmm3 = 27, 1122cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_stmm4 = 28, 1123cedac228d2dd51db4b79ea1e72c7f249408ee061Torne (Richard Coles) gdb_stmm5 = 29, 11243551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gdb_stmm6 = 30, 11253551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gdb_stmm7 = 31, 11265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_fctrl = 32, gdb_fcw = gdb_fctrl, 11275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_fstat = 33, gdb_fsw = gdb_fstat, 11285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_ftag = 34, gdb_ftw = gdb_ftag, 11295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_fiseg = 35, gdb_fpu_cs = gdb_fiseg, 11305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_fioff = 36, gdb_ip = gdb_fioff, 11315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_foseg = 37, gdb_fpu_ds = gdb_foseg, 11325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_fooff = 38, gdb_dp = gdb_fooff, 11335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_fop = 39, 113490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) gdb_xmm0 = 40, 1135a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) gdb_xmm1 = 41, 1136a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) gdb_xmm2 = 42, 11375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm3 = 43, 11385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm4 = 44, 11395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm5 = 45, 11405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm6 = 46, 11415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm7 = 47, 11425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm8 = 48, 11435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm9 = 49, 11445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm10 = 50, 11455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm11 = 51, 11465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm12 = 52, 11475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_xmm13 = 53, 11483551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gdb_xmm14 = 54, 11493551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gdb_xmm15 = 55, 11505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_mxcsr = 56, 11511320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci gdb_ymm0 = gdb_xmm0, 11525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) gdb_ymm1 = gdb_xmm1, 1153c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) gdb_ymm2 = gdb_xmm2, 1154c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) gdb_ymm3 = gdb_xmm3, 11552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gdb_ymm4 = gdb_xmm4, 11562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gdb_ymm5 = gdb_xmm5, 11573551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gdb_ymm6 = gdb_xmm6, 11583551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) gdb_ymm7 = gdb_xmm7, 11595d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) gdb_ymm8 = gdb_xmm8, 11602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gdb_ymm9 = gdb_xmm9, 11612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gdb_ymm10 = gdb_xmm10, 1162effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch gdb_ymm11 = gdb_xmm11, 1163effb81e5f8246d0db0270817048dc992db66e9fbBen Murdoch gdb_ymm12 = gdb_xmm12, 1164a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) gdb_ymm13 = gdb_xmm13, 11652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gdb_ymm14 = gdb_xmm14, 11662a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) gdb_ymm15 = gdb_xmm15 1167868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)}; 1168868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 1169868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)#define GPR_OFFSET(reg) (offsetof (DNBArchImplX86_64::GPR, __##reg)) 1170868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)#define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx)) 11712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx)) 1172868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)#define EXC_OFFSET(reg) (offsetof (DNBArchImplX86_64::EXC, __##reg) + offsetof (DNBArchImplX86_64::Context, exc)) 117346d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles) 117446d4c2bc3267f3f028f39e7e311b0f89aba2e4fdTorne (Richard Coles)// This does not accurately identify the location of ymm0...7 in 1175868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// Context.fpu.avx. That is because there is a bunch of padding 1176868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// in Context.fpu.avx that we don't need. Offset macros lay out 1177868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// the register state that Debugserver transmits to the debugger 1178868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// -- not to interpret the thread_get_state info. 1179868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n)) 1180868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles) 1181868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)#define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg)) 11824e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg)) 11834e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)#define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg)) 11844e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles)#define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg)) 11855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define FPU_SIZE_YMM(reg) (32) 11865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg)) 11873551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 11883551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// These macros will auto define the register name, alt name, register size, 11895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// register offset, encoding, format and native register. This ensures that 11905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// the register state structures are defined correctly and have the correct 11915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// sizes and offsets. 1192a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg } 1193a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)#define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg } 1194a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)#define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg } 1195a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles)#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg } 11965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 11975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// General purpose registers for 64 bit 11983551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)const DNBRegisterInfo 11993551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)DNBArchImplX86_64::g_gpr_registers[] = 12005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 12012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DEFINE_GPR (rax), 12022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DEFINE_GPR (rbx), 12032a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DEFINE_GPR_ALT (rcx , "arg4", GENERIC_REGNUM_ARG4), 12042a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DEFINE_GPR_ALT (rdx , "arg3", GENERIC_REGNUM_ARG3), 12052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) DEFINE_GPR_ALT (rdi , "arg1", GENERIC_REGNUM_ARG1), 12065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DEFINE_GPR_ALT (rsi , "arg2", GENERIC_REGNUM_ARG2), 12075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DEFINE_GPR_ALT (rbp , "fp" , GENERIC_REGNUM_FP), 12085c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu DEFINE_GPR_ALT (rsp , "sp" , GENERIC_REGNUM_SP), 12093551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) DEFINE_GPR_ALT (r8 , "arg5", GENERIC_REGNUM_ARG5), 12105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DEFINE_GPR_ALT (r9 , "arg6", GENERIC_REGNUM_ARG6), 12115c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu DEFINE_GPR (r10), 12125c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu DEFINE_GPR (r11), 12135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DEFINE_GPR (r12), 12145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DEFINE_GPR (r13), 1215116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR (r14), 1216116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR (r15), 1217116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR_ALT (rip , "pc", GENERIC_REGNUM_PC), 1218116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR_ALT3 (rflags, "flags", GENERIC_REGNUM_FLAGS), 1219116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR_ALT2 (cs, NULL), 1220116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR_ALT2 (fs, NULL), 1221116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch DEFINE_GPR_ALT2 (gs, NULL), 1222116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch}; 1223116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch 1224116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch// Floating point registers 64 bit 12256e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)const DNBRegisterInfo 12266e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles)DNBArchImplX86_64::g_fpu_registers_no_avx[] = 12276e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles){ 12286e8cce623b6e4fe0c9e4af605d675dd9d0338c38Torne (Richard Coles) { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1, -1, -1, -1 }, 1229116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1, -1, -1, -1 }, 1230116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1, -1, -1, -1 }, 12315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1, -1, -1, -1 }, 12323551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1, -1, -1, -1 }, 1233116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1, -1, -1, -1 }, 12345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1, -1, -1, -1 }, 12355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1, -1, -1, -1 }, 12365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1, -1, -1, -1 }, 12375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 12383551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 12395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 12405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 12415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 12425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 12435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 12445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 12455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 12465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 12475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 12485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 12495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 12505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 12515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 12525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 12535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 12545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 12555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 12565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 12575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 12585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 12595f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 12605f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 12615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 12625f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 12635f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 12645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 12655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 12665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const DNBRegisterInfo 12675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::g_fpu_registers_avx[] = 12685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 12695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1, -1, -1, -1 }, 12705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1, -1, -1, -1 }, 12715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1, -1, -1, -1 }, 12725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1, -1, -1, -1 }, 12735f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1, -1, -1, -1 }, 1274a1401311d1ab56c4ed0a474bd38c108f75cb0cd9Torne (Richard Coles) { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1, -1, -1, -1 }, 1275424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1, -1, -1, -1 }, 12765f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1, -1, -1, -1 }, 1277424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1, -1, -1, -1 }, 12780f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 12790f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) 12800f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 12810f1bc08d4cfcc34181b0b5cbf065c40f687bf740Torne (Richard Coles) { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1282f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1283f8ee788a64d60abd8f2d742a5fdedde054ecd910Torne (Richard Coles) { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1284c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1285c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 12862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1287a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 12882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 128958537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 129058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 12911320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 12921320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 12935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 12945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 12955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 12965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 12975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 12985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 12995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 13005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1301f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1302a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 13035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1304424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 13055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1, gdb_ymm0 }, 13075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1, gdb_ymm1 }, 13085d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1, gdb_ymm2 }, 13095d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1, gdb_ymm3 }, 13105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1, gdb_ymm4 }, 13115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1, gdb_ymm5 }, 13125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1, gdb_ymm6 }, 1313a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1, gdb_ymm7 }, 13142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) { e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1, gdb_ymm8 }, 13155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1, gdb_ymm9 }, 1316a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1, gdb_ymm10 }, 13173551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1, gdb_ymm11 }, 13183551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1, gdb_ymm12 }, 13193551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1, gdb_ymm13 }, 13203551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1, gdb_ymm14 }, 13213551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1, gdb_ymm15 } 13225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 13235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Exception registers 13255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 13265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const DNBRegisterInfo 13275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)DNBArchImplX86_64::g_exc_registers[] = 13285d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles){ 13295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) { e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1, -1, -1, -1 }, 1330f2477e01787aa58f445919b809d89e252beef54fTorne (Richard Coles) { e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1, -1, -1, -1 }, 1331a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) { e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1, -1, -1, -1 } 13325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 13335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1334424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)// Number of registers in each register set 13355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo); 13365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_fpu_registers_no_avx = sizeof(g_fpu_registers_no_avx)/sizeof(DNBRegisterInfo); 13375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_fpu_registers_avx = sizeof(g_fpu_registers_avx)/sizeof(DNBRegisterInfo); 1338a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo); 1339a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_all_registers_no_avx = k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers; 13405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_all_registers_avx = k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers; 1341a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 13423551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)//---------------------------------------------------------------------- 13433551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// Register set definitions. The first definitions at register set index 13443551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// of zero is for all registers, followed by other registers sets. The 13453551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)// register information for the all register set need not be filled in. 13463551c9c881056c480085172ff9840cab31610854Torne (Richard Coles)//---------------------------------------------------------------------- 13475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const DNBRegisterSetInfo 13485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::g_reg_sets_no_avx[] = 13495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 13505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "x86_64 Registers", NULL, k_num_all_registers_no_avx }, 13515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 13525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "Floating Point Registers", g_fpu_registers_no_avx, k_num_fpu_registers_no_avx }, 13535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1354424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)}; 13555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const DNBRegisterSetInfo 1357424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DNBArchImplX86_64::g_reg_sets_avx[] = 1358424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles){ 13595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "x86_64 Registers", NULL, k_num_all_registers_avx }, 13605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 13615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx }, 13625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1363a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)}; 13645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1365a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// Total number of register sets for this architecture 1366a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)const size_t DNBArchImplX86_64::k_num_register_sets = sizeof(g_reg_sets_avx)/sizeof(DNBRegisterSetInfo); 13675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchProtocol * 13705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::Create (MachThread *thread) 1371424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles){ 1372424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DNBArchImplX86_64 *obj = new DNBArchImplX86_64 (thread); 13735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1374424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) // When new thread comes along, it tries to inherit from the global debug state, if it is valid. 1375424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) if (Valid_Global_Debug_State) 1376424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) { 1377424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) obj->m_state.context.dbg = Global_Debug_State; 1378424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) kern_return_t kret = obj->SetDBGState(); 13795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBLogThreadedIf(LOG_WATCHPOINTS, 13805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) "DNBArchImplX86_64::Create() Inherit and SetDBGState() => 0x%8.8x.", kret); 13815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 13825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return obj; 13835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 13845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)const uint8_t * const 13861320f92c476a1ad9d19dba2a48c72b75566198e9Primiano TucciDNBArchImplX86_64::SoftwareBreakpointOpcode (nub_size_t byte_size) 13875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 13885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static const uint8_t g_breakpoint_opcode[] = { 0xCC }; 13891320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci if (byte_size == 1) 13905d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return g_breakpoint_opcode; 13915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return NULL; 1392424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)} 1393424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 13941320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucciconst DNBRegisterSetInfo * 13955d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)DNBArchImplX86_64::GetRegisterSetInfo(nub_size_t *num_reg_sets) 13965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles){ 13975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) *num_reg_sets = k_num_register_sets; 13985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 13995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (CPUHasAVX() || FORCE_AVX_REGS) 14005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return g_reg_sets_avx; 1401424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) else 1402424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) return g_reg_sets_no_avx; 14035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1404424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 1405424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)void 14065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)DNBArchImplX86_64::Initialize() 1407424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles){ 1408424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DNBArchPluginInfo arch_plugin_info = 14095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 14105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CPU_TYPE_X86_64, 14115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBArchImplX86_64::Create, 14125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBArchImplX86_64::GetRegisterSetInfo, 14135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBArchImplX86_64::SoftwareBreakpointOpcode 14145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 14155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 14162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Register this arch plug-in with the main protocol class 14175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DNBArchProtocol::RegisterArchPlugin (arch_plugin_info); 14185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 14192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 14205f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)bool 14215f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DNBArchImplX86_64::GetRegisterValue(int set, int reg, DNBRegisterValue *value) 14225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles){ 14235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (set == REGISTER_SET_GENERIC) 14245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 14255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) switch (reg) 14265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) { 14275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case GENERIC_REGNUM_PC: // Program Counter 14285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) set = e_regSetGPR; 14291320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci reg = gpr_rip; 14301320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci break; 14311320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci 14321320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci case GENERIC_REGNUM_SP: // Stack Pointer 14331320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci set = e_regSetGPR; 14341320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci reg = gpr_rsp; 14351320f92c476a1ad9d19dba2a48c72b75566198e9Primiano Tucci break; 14365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 14375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case GENERIC_REGNUM_FP: // Frame Pointer 14385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) set = e_regSetGPR; 14395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) reg = gpr_rbp; 14405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 14415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 14425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case GENERIC_REGNUM_FLAGS: // Processor flags register 14435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) set = e_regSetGPR; 14445c02ac1a9c1b504631c0a3d2b6e737b5d738bae1Bo Liu reg = gpr_rflags; 14455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) break; 14465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 14475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) case GENERIC_REGNUM_RA: // Return Address 1448a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) default: 1449a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return false; 1450 } 1451 } 1452 1453 if (GetRegisterState(set, false) != KERN_SUCCESS) 1454 return false; 1455 1456 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1457 if (regInfo) 1458 { 1459 value->info = *regInfo; 1460 switch (set) 1461 { 1462 case e_regSetGPR: 1463 if (reg < k_num_gpr_registers) 1464 { 1465 value->value.uint64 = ((uint64_t*)(&m_state.context.gpr))[reg]; 1466 return true; 1467 } 1468 break; 1469 1470 case e_regSetFPU: 1471 if (CPUHasAVX() || FORCE_AVX_REGS) 1472 { 1473 switch (reg) 1474 { 1475 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true; 1476 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true; 1477 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true; 1478 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true; 1479 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true; 1480 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true; 1481 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true; 1482 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true; 1483 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true; 1484 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true; 1485 1486 case fpu_stmm0: 1487 case fpu_stmm1: 1488 case fpu_stmm2: 1489 case fpu_stmm3: 1490 case fpu_stmm4: 1491 case fpu_stmm5: 1492 case fpu_stmm6: 1493 case fpu_stmm7: 1494 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1495 return true; 1496 1497 case fpu_xmm0: 1498 case fpu_xmm1: 1499 case fpu_xmm2: 1500 case fpu_xmm3: 1501 case fpu_xmm4: 1502 case fpu_xmm5: 1503 case fpu_xmm6: 1504 case fpu_xmm7: 1505 case fpu_xmm8: 1506 case fpu_xmm9: 1507 case fpu_xmm10: 1508 case fpu_xmm11: 1509 case fpu_xmm12: 1510 case fpu_xmm13: 1511 case fpu_xmm14: 1512 case fpu_xmm15: 1513 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1514 return true; 1515 1516 case fpu_ymm0: 1517 case fpu_ymm1: 1518 case fpu_ymm2: 1519 case fpu_ymm3: 1520 case fpu_ymm4: 1521 case fpu_ymm5: 1522 case fpu_ymm6: 1523 case fpu_ymm7: 1524 case fpu_ymm8: 1525 case fpu_ymm9: 1526 case fpu_ymm10: 1527 case fpu_ymm11: 1528 case fpu_ymm12: 1529 case fpu_ymm13: 1530 case fpu_ymm14: 1531 case fpu_ymm15: 1532 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16); 1533 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16); 1534 return true; 1535 } 1536 } 1537 else 1538 { 1539 switch (reg) 1540 { 1541 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true; 1542 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true; 1543 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true; 1544 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true; 1545 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true; 1546 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true; 1547 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true; 1548 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true; 1549 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true; 1550 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true; 1551 1552 case fpu_stmm0: 1553 case fpu_stmm1: 1554 case fpu_stmm2: 1555 case fpu_stmm3: 1556 case fpu_stmm4: 1557 case fpu_stmm5: 1558 case fpu_stmm6: 1559 case fpu_stmm7: 1560 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1561 return true; 1562 1563 case fpu_xmm0: 1564 case fpu_xmm1: 1565 case fpu_xmm2: 1566 case fpu_xmm3: 1567 case fpu_xmm4: 1568 case fpu_xmm5: 1569 case fpu_xmm6: 1570 case fpu_xmm7: 1571 case fpu_xmm8: 1572 case fpu_xmm9: 1573 case fpu_xmm10: 1574 case fpu_xmm11: 1575 case fpu_xmm12: 1576 case fpu_xmm13: 1577 case fpu_xmm14: 1578 case fpu_xmm15: 1579 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1580 return true; 1581 } 1582 } 1583 break; 1584 1585 case e_regSetEXC: 1586 switch (reg) 1587 { 1588 case exc_trapno: value->value.uint32 = m_state.context.exc.__trapno; return true; 1589 case exc_err: value->value.uint32 = m_state.context.exc.__err; return true; 1590 case exc_faultvaddr:value->value.uint64 = m_state.context.exc.__faultvaddr; return true; 1591 } 1592 break; 1593 } 1594 } 1595 return false; 1596} 1597 1598 1599bool 1600DNBArchImplX86_64::SetRegisterValue(int set, int reg, const DNBRegisterValue *value) 1601{ 1602 if (set == REGISTER_SET_GENERIC) 1603 { 1604 switch (reg) 1605 { 1606 case GENERIC_REGNUM_PC: // Program Counter 1607 set = e_regSetGPR; 1608 reg = gpr_rip; 1609 break; 1610 1611 case GENERIC_REGNUM_SP: // Stack Pointer 1612 set = e_regSetGPR; 1613 reg = gpr_rsp; 1614 break; 1615 1616 case GENERIC_REGNUM_FP: // Frame Pointer 1617 set = e_regSetGPR; 1618 reg = gpr_rbp; 1619 break; 1620 1621 case GENERIC_REGNUM_FLAGS: // Processor flags register 1622 set = e_regSetGPR; 1623 reg = gpr_rflags; 1624 break; 1625 1626 case GENERIC_REGNUM_RA: // Return Address 1627 default: 1628 return false; 1629 } 1630 } 1631 1632 if (GetRegisterState(set, false) != KERN_SUCCESS) 1633 return false; 1634 1635 bool success = false; 1636 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1637 if (regInfo) 1638 { 1639 switch (set) 1640 { 1641 case e_regSetGPR: 1642 if (reg < k_num_gpr_registers) 1643 { 1644 ((uint64_t*)(&m_state.context.gpr))[reg] = value->value.uint64; 1645 success = true; 1646 } 1647 break; 1648 1649 case e_regSetFPU: 1650 if (CPUHasAVX() || FORCE_AVX_REGS) 1651 { 1652 switch (reg) 1653 { 1654 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1655 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1656 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break; 1657 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break; 1658 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break; 1659 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break; 1660 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break; 1661 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break; 1662 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1663 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1664 1665 case fpu_stmm0: 1666 case fpu_stmm1: 1667 case fpu_stmm2: 1668 case fpu_stmm3: 1669 case fpu_stmm4: 1670 case fpu_stmm5: 1671 case fpu_stmm6: 1672 case fpu_stmm7: 1673 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1674 success = true; 1675 break; 1676 1677 case fpu_xmm0: 1678 case fpu_xmm1: 1679 case fpu_xmm2: 1680 case fpu_xmm3: 1681 case fpu_xmm4: 1682 case fpu_xmm5: 1683 case fpu_xmm6: 1684 case fpu_xmm7: 1685 case fpu_xmm8: 1686 case fpu_xmm9: 1687 case fpu_xmm10: 1688 case fpu_xmm11: 1689 case fpu_xmm12: 1690 case fpu_xmm13: 1691 case fpu_xmm14: 1692 case fpu_xmm15: 1693 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1694 success = true; 1695 break; 1696 1697 case fpu_ymm0: 1698 case fpu_ymm1: 1699 case fpu_ymm2: 1700 case fpu_ymm3: 1701 case fpu_ymm4: 1702 case fpu_ymm5: 1703 case fpu_ymm6: 1704 case fpu_ymm7: 1705 case fpu_ymm8: 1706 case fpu_ymm9: 1707 case fpu_ymm10: 1708 case fpu_ymm11: 1709 case fpu_ymm12: 1710 case fpu_ymm13: 1711 case fpu_ymm14: 1712 case fpu_ymm15: 1713 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16); 1714 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16); 1715 return true; 1716 } 1717 } 1718 else 1719 { 1720 switch (reg) 1721 { 1722 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1723 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1724 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break; 1725 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break; 1726 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break; 1727 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break; 1728 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break; 1729 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break; 1730 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1731 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1732 1733 case fpu_stmm0: 1734 case fpu_stmm1: 1735 case fpu_stmm2: 1736 case fpu_stmm3: 1737 case fpu_stmm4: 1738 case fpu_stmm5: 1739 case fpu_stmm6: 1740 case fpu_stmm7: 1741 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1742 success = true; 1743 break; 1744 1745 case fpu_xmm0: 1746 case fpu_xmm1: 1747 case fpu_xmm2: 1748 case fpu_xmm3: 1749 case fpu_xmm4: 1750 case fpu_xmm5: 1751 case fpu_xmm6: 1752 case fpu_xmm7: 1753 case fpu_xmm8: 1754 case fpu_xmm9: 1755 case fpu_xmm10: 1756 case fpu_xmm11: 1757 case fpu_xmm12: 1758 case fpu_xmm13: 1759 case fpu_xmm14: 1760 case fpu_xmm15: 1761 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1762 success = true; 1763 break; 1764 } 1765 } 1766 break; 1767 1768 case e_regSetEXC: 1769 switch (reg) 1770 { 1771 case exc_trapno: m_state.context.exc.__trapno = value->value.uint32; success = true; break; 1772 case exc_err: m_state.context.exc.__err = value->value.uint32; success = true; break; 1773 case exc_faultvaddr:m_state.context.exc.__faultvaddr = value->value.uint64; success = true; break; 1774 } 1775 break; 1776 } 1777 } 1778 1779 if (success) 1780 return SetRegisterState(set) == KERN_SUCCESS; 1781 return false; 1782} 1783 1784 1785nub_size_t 1786DNBArchImplX86_64::GetRegisterContext (void *buf, nub_size_t buf_len) 1787{ 1788 nub_size_t size = sizeof (m_state.context); 1789 1790 if (buf && buf_len) 1791 { 1792 if (size > buf_len) 1793 size = buf_len; 1794 1795 bool force = false; 1796 kern_return_t kret; 1797 if ((kret = GetGPRState(force)) != KERN_SUCCESS) 1798 { 1799 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) error: GPR regs failed to read: %u ", buf, buf_len, kret); 1800 size = 0; 1801 } 1802 else 1803 if ((kret = GetFPUState(force)) != KERN_SUCCESS) 1804 { 1805 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) error: %s regs failed to read: %u", buf, buf_len, CPUHasAVX() ? "AVX" : "FPU", kret); 1806 size = 0; 1807 } 1808 else 1809 if ((kret = GetEXCState(force)) != KERN_SUCCESS) 1810 { 1811 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) error: EXC regs failed to read: %u", buf, buf_len, kret); 1812 size = 0; 1813 } 1814 else 1815 { 1816 // Success 1817 ::memcpy (buf, &m_state.context, size); 1818 } 1819 } 1820 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1821 // Return the size of the register context even if NULL was passed in 1822 return size; 1823} 1824 1825nub_size_t 1826DNBArchImplX86_64::SetRegisterContext (const void *buf, nub_size_t buf_len) 1827{ 1828 nub_size_t size = sizeof (m_state.context); 1829 if (buf == NULL || buf_len == 0) 1830 size = 0; 1831 1832 if (size) 1833 { 1834 if (size > buf_len) 1835 size = buf_len; 1836 1837 ::memcpy (&m_state.context, buf, size); 1838 kern_return_t kret; 1839 if ((kret = SetGPRState()) != KERN_SUCCESS) 1840 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) error: GPR regs failed to write: %u", buf, buf_len, kret); 1841 if ((kret = SetFPUState()) != KERN_SUCCESS) 1842 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) error: %s regs failed to write: %u", buf, buf_len, CPUHasAVX() ? "AVX" : "FPU", kret); 1843 if ((kret = SetEXCState()) != KERN_SUCCESS) 1844 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) error: EXP regs failed to write: %u", buf, buf_len, kret); 1845 } 1846 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1847 return size; 1848} 1849 1850 1851kern_return_t 1852DNBArchImplX86_64::GetRegisterState(int set, bool force) 1853{ 1854 switch (set) 1855 { 1856 case e_regSetALL: return GetGPRState(force) | GetFPUState(force) | GetEXCState(force); 1857 case e_regSetGPR: return GetGPRState(force); 1858 case e_regSetFPU: return GetFPUState(force); 1859 case e_regSetEXC: return GetEXCState(force); 1860 default: break; 1861 } 1862 return KERN_INVALID_ARGUMENT; 1863} 1864 1865kern_return_t 1866DNBArchImplX86_64::SetRegisterState(int set) 1867{ 1868 // Make sure we have a valid context to set. 1869 if (RegisterSetStateIsValid(set)) 1870 { 1871 switch (set) 1872 { 1873 case e_regSetALL: return SetGPRState() | SetFPUState() | SetEXCState(); 1874 case e_regSetGPR: return SetGPRState(); 1875 case e_regSetFPU: return SetFPUState(); 1876 case e_regSetEXC: return SetEXCState(); 1877 default: break; 1878 } 1879 } 1880 return KERN_INVALID_ARGUMENT; 1881} 1882 1883bool 1884DNBArchImplX86_64::RegisterSetStateIsValid (int set) const 1885{ 1886 return m_state.RegsAreValid(set); 1887} 1888 1889 1890 1891#endif // #if defined (__i386__) || defined (__x86_64__) 1892