DNBArchImplX86_64.cpp revision fc8909388e6f1cea591c0d56434236f8d16543e6
1c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl//===-- DNBArchImplX86_64.cpp -----------------------------------*- C++ -*-===// 2c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// 3c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// The LLVM Compiler Infrastructure 4c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// 5c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// This file is distributed under the University of Illinois Open Source 6c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// License. See LICENSE.TXT for details. 7c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// 8c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl//===----------------------------------------------------------------------===// 9c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// 10c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// Created by Greg Clayton on 6/25/07. 11c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl// 12c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl//===----------------------------------------------------------------------===// 13c42e1183846228a7fa5143ad76507d6d60f5c6f3Sebastian Redl 14#if defined (__i386__) || defined (__x86_64__) 15 16#include <sys/cdefs.h> 17 18#include "MacOSX/x86_64/DNBArchImplX86_64.h" 19#include "DNBLog.h" 20#include "MachThread.h" 21#include "MachProcess.h" 22#include <mach/mach.h> 23#include <stdlib.h> 24 25#if defined (LLDB_DEBUGSERVER_RELEASE) || defined (LLDB_DEBUGSERVER_DEBUG) 26enum debugState { 27 debugStateUnknown, 28 debugStateOff, 29 debugStateOn 30}; 31 32static debugState sFPUDebugState = debugStateUnknown; 33static debugState sAVXForceState = debugStateUnknown; 34 35static bool DebugFPURegs () 36{ 37 if (sFPUDebugState == debugStateUnknown) 38 { 39 if (getenv("DNB_DEBUG_FPU_REGS")) 40 sFPUDebugState = debugStateOn; 41 else 42 sFPUDebugState = debugStateOff; 43 } 44 45 return (sFPUDebugState == debugStateOn); 46} 47 48static bool ForceAVXRegs () 49{ 50 if (sFPUDebugState == debugStateUnknown) 51 { 52 if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS")) 53 sAVXForceState = debugStateOn; 54 else 55 sAVXForceState = debugStateOff; 56 } 57 58 return (sAVXForceState == debugStateOn); 59} 60 61#define DEBUG_FPU_REGS (DebugFPURegs()) 62#define FORCE_AVX_REGS (ForceAVXRegs()) 63#else 64#define DEBUG_FPU_REGS (0) 65#define FORCE_AVX_REGS (0) 66#endif 67 68enum DNBArchImplX86_64::AVXPresence DNBArchImplX86_64::s_has_avx = DNBArchImplX86_64::kAVXUnknown; 69 70uint64_t 71DNBArchImplX86_64::GetPC(uint64_t failValue) 72{ 73 // Get program counter 74 if (GetGPRState(false) == KERN_SUCCESS) 75 return m_state.context.gpr.__rip; 76 return failValue; 77} 78 79kern_return_t 80DNBArchImplX86_64::SetPC(uint64_t value) 81{ 82 // Get program counter 83 kern_return_t err = GetGPRState(false); 84 if (err == KERN_SUCCESS) 85 { 86 m_state.context.gpr.__rip = value; 87 err = SetGPRState(); 88 } 89 return err == KERN_SUCCESS; 90} 91 92uint64_t 93DNBArchImplX86_64::GetSP(uint64_t failValue) 94{ 95 // Get stack pointer 96 if (GetGPRState(false) == KERN_SUCCESS) 97 return m_state.context.gpr.__rsp; 98 return failValue; 99} 100 101// Uncomment the value below to verify the values in the debugger. 102//#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 103 104kern_return_t 105DNBArchImplX86_64::GetGPRState(bool force) 106{ 107 if (force || m_state.GetError(e_regSetGPR, Read)) 108 { 109 kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 110 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (GetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 111 112#if DEBUG_GPR_VALUES 113 m_state.context.gpr.__rax = ('a' << 8) + 'x'; 114 m_state.context.gpr.__rbx = ('b' << 8) + 'x'; 115 m_state.context.gpr.__rcx = ('c' << 8) + 'x'; 116 m_state.context.gpr.__rdx = ('d' << 8) + 'x'; 117 m_state.context.gpr.__rdi = ('d' << 8) + 'i'; 118 m_state.context.gpr.__rsi = ('s' << 8) + 'i'; 119 m_state.context.gpr.__rbp = ('b' << 8) + 'p'; 120 m_state.context.gpr.__rsp = ('s' << 8) + 'p'; 121 m_state.context.gpr.__r8 = ('r' << 8) + '8'; 122 m_state.context.gpr.__r9 = ('r' << 8) + '9'; 123 m_state.context.gpr.__r10 = ('r' << 8) + 'a'; 124 m_state.context.gpr.__r11 = ('r' << 8) + 'b'; 125 m_state.context.gpr.__r12 = ('r' << 8) + 'c'; 126 m_state.context.gpr.__r13 = ('r' << 8) + 'd'; 127 m_state.context.gpr.__r14 = ('r' << 8) + 'e'; 128 m_state.context.gpr.__r15 = ('r' << 8) + 'f'; 129 m_state.context.gpr.__rip = ('i' << 8) + 'p'; 130 m_state.context.gpr.__rflags = ('f' << 8) + 'l'; 131 m_state.context.gpr.__cs = ('c' << 8) + 's'; 132 m_state.context.gpr.__fs = ('f' << 8) + 's'; 133 m_state.context.gpr.__gs = ('g' << 8) + 's'; 134 m_state.SetError(e_regSetGPR, Read, 0); 135#else 136 mach_msg_type_number_t count = e_regSetWordSizeGPR; 137 m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count)); 138 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 139 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 140 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 141 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 142 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 143 "\n\trip = %16.16llx" 144 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 145 m_thread->ThreadID(), x86_THREAD_STATE64, x86_THREAD_STATE64_COUNT, 146 m_state.GetError(e_regSetGPR, Read), 147 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 148 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 149 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 150 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 151 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 152 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 153 m_state.context.gpr.__cs,m_state.context.gpr.__fs, m_state.context.gpr.__gs); 154 155 // DNBLogThreadedIf (LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 156 // "\n\trax = %16.16llx" 157 // "\n\trbx = %16.16llx" 158 // "\n\trcx = %16.16llx" 159 // "\n\trdx = %16.16llx" 160 // "\n\trdi = %16.16llx" 161 // "\n\trsi = %16.16llx" 162 // "\n\trbp = %16.16llx" 163 // "\n\trsp = %16.16llx" 164 // "\n\t r8 = %16.16llx" 165 // "\n\t r9 = %16.16llx" 166 // "\n\tr10 = %16.16llx" 167 // "\n\tr11 = %16.16llx" 168 // "\n\tr12 = %16.16llx" 169 // "\n\tr13 = %16.16llx" 170 // "\n\tr14 = %16.16llx" 171 // "\n\tr15 = %16.16llx" 172 // "\n\trip = %16.16llx" 173 // "\n\tflg = %16.16llx" 174 // "\n\t cs = %16.16llx" 175 // "\n\t fs = %16.16llx" 176 // "\n\t gs = %16.16llx", 177 // m_thread->ThreadID(), 178 // x86_THREAD_STATE64, 179 // x86_THREAD_STATE64_COUNT, 180 // m_state.GetError(e_regSetGPR, Read), 181 // m_state.context.gpr.__rax, 182 // m_state.context.gpr.__rbx, 183 // m_state.context.gpr.__rcx, 184 // m_state.context.gpr.__rdx, 185 // m_state.context.gpr.__rdi, 186 // m_state.context.gpr.__rsi, 187 // m_state.context.gpr.__rbp, 188 // m_state.context.gpr.__rsp, 189 // m_state.context.gpr.__r8, 190 // m_state.context.gpr.__r9, 191 // m_state.context.gpr.__r10, 192 // m_state.context.gpr.__r11, 193 // m_state.context.gpr.__r12, 194 // m_state.context.gpr.__r13, 195 // m_state.context.gpr.__r14, 196 // m_state.context.gpr.__r15, 197 // m_state.context.gpr.__rip, 198 // m_state.context.gpr.__rflags, 199 // m_state.context.gpr.__cs, 200 // m_state.context.gpr.__fs, 201 // m_state.context.gpr.__gs); 202#endif 203 } 204 return m_state.GetError(e_regSetGPR, Read); 205} 206 207// Uncomment the value below to verify the values in the debugger. 208//#define DEBUG_FPU_REGS 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 209 210kern_return_t 211DNBArchImplX86_64::GetFPUState(bool force) 212{ 213 if (force || m_state.GetError(e_regSetFPU, Read)) 214 { 215 if (DEBUG_FPU_REGS) { 216 if (CPUHasAVX() || FORCE_AVX_REGS) 217 { 218 m_state.context.fpu.avx.__fpu_reserved[0] = -1; 219 m_state.context.fpu.avx.__fpu_reserved[1] = -1; 220 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234; 221 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678; 222 m_state.context.fpu.avx.__fpu_ftw = 1; 223 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX; 224 m_state.context.fpu.avx.__fpu_fop = 2; 225 m_state.context.fpu.avx.__fpu_ip = 3; 226 m_state.context.fpu.avx.__fpu_cs = 4; 227 m_state.context.fpu.avx.__fpu_rsrv2 = 5; 228 m_state.context.fpu.avx.__fpu_dp = 6; 229 m_state.context.fpu.avx.__fpu_ds = 7; 230 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX; 231 m_state.context.fpu.avx.__fpu_mxcsr = 8; 232 m_state.context.fpu.avx.__fpu_mxcsrmask = 9; 233 int i; 234 for (i=0; i<16; ++i) 235 { 236 if (i<10) 237 { 238 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 239 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 240 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 241 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 242 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 243 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 244 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 245 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 246 } 247 else 248 { 249 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 250 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 251 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 252 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 253 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 254 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 255 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 256 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 257 } 258 259 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0'; 260 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1'; 261 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2'; 262 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3'; 263 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4'; 264 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5'; 265 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6'; 266 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7'; 267 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8'; 268 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9'; 269 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 270 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 271 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 272 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 273 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 274 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 275 276 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0'; 277 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1'; 278 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2'; 279 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3'; 280 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4'; 281 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5'; 282 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6'; 283 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7'; 284 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8'; 285 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9'; 286 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A'; 287 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B'; 288 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C'; 289 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D'; 290 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E'; 291 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F'; 292 } 293 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i) 294 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN; 295 m_state.context.fpu.avx.__fpu_reserved1 = -1; 296 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i) 297 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; 298 m_state.SetError(e_regSetFPU, Read, 0); 299 } 300 else 301 { 302 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; 303 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; 304 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; 305 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; 306 m_state.context.fpu.no_avx.__fpu_ftw = 1; 307 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; 308 m_state.context.fpu.no_avx.__fpu_fop = 2; 309 m_state.context.fpu.no_avx.__fpu_ip = 3; 310 m_state.context.fpu.no_avx.__fpu_cs = 4; 311 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; 312 m_state.context.fpu.no_avx.__fpu_dp = 6; 313 m_state.context.fpu.no_avx.__fpu_ds = 7; 314 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; 315 m_state.context.fpu.no_avx.__fpu_mxcsr = 8; 316 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; 317 int i; 318 for (i=0; i<16; ++i) 319 { 320 if (i<10) 321 { 322 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 323 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 324 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 325 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 326 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 327 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 328 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 329 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 330 } 331 else 332 { 333 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 334 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 335 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 336 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 337 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 338 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 339 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 340 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 341 } 342 343 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; 344 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; 345 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; 346 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; 347 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; 348 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; 349 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; 350 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; 351 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8'; 352 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9'; 353 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 354 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 355 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 356 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 357 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 358 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 359 } 360 for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) 361 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; 362 m_state.context.fpu.no_avx.__fpu_reserved1 = -1; 363 m_state.SetError(e_regSetFPU, Read, 0); 364 } 365 } 366 else 367 { 368 if (CPUHasAVX() || FORCE_AVX_REGS) 369 { 370 mach_msg_type_number_t count = e_regSetWordSizeAVX; 371 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count)); 372 } 373 else 374 { 375 mach_msg_type_number_t count = e_regSetWordSizeFPR; 376 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count)); 377 } 378 } 379 } 380 return m_state.GetError(e_regSetFPU, Read); 381} 382 383kern_return_t 384DNBArchImplX86_64::GetEXCState(bool force) 385{ 386 if (force || m_state.GetError(e_regSetEXC, Read)) 387 { 388 mach_msg_type_number_t count = e_regSetWordSizeEXC; 389 m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count)); 390 } 391 return m_state.GetError(e_regSetEXC, Read); 392} 393 394kern_return_t 395DNBArchImplX86_64::SetGPRState() 396{ 397 kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 398 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 399 400 m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR)); 401 DNBLogThreadedIf (LOG_THREAD, "::thread_set_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 402 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 403 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 404 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 405 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 406 "\n\trip = %16.16llx" 407 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 408 m_thread->ThreadID(), __x86_64_THREAD_STATE, e_regSetWordSizeGPR, 409 m_state.GetError(e_regSetGPR, Write), 410 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 411 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 412 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 413 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 414 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 415 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 416 m_state.context.gpr.__cs, m_state.context.gpr.__fs, m_state.context.gpr.__gs); 417 return m_state.GetError(e_regSetGPR, Write); 418} 419 420kern_return_t 421DNBArchImplX86_64::SetFPUState() 422{ 423 if (DEBUG_FPU_REGS) 424 { 425 m_state.SetError(e_regSetFPU, Write, 0); 426 return m_state.GetError(e_regSetFPU, Write); 427 } 428 else 429 { 430 if (CPUHasAVX() || FORCE_AVX_REGS) 431 { 432 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX)); 433 return m_state.GetError(e_regSetFPU, Write); 434 } 435 else 436 { 437 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPR)); 438 return m_state.GetError(e_regSetFPU, Write); 439 } 440 } 441} 442 443kern_return_t 444DNBArchImplX86_64::SetEXCState() 445{ 446 m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC)); 447 return m_state.GetError(e_regSetEXC, Write); 448} 449 450kern_return_t 451DNBArchImplX86_64::GetDBGState(bool force) 452{ 453 if (force || m_state.GetError(e_regSetDBG, Read)) 454 { 455 mach_msg_type_number_t count = e_regSetWordSizeDBG; 456 m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count)); 457 } 458 return m_state.GetError(e_regSetDBG, Read); 459} 460 461kern_return_t 462DNBArchImplX86_64::SetDBGState() 463{ 464 m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG)); 465 return m_state.GetError(e_regSetDBG, Write); 466} 467 468void 469DNBArchImplX86_64::ThreadWillResume() 470{ 471 // Do we need to step this thread? If so, let the mach thread tell us so. 472 if (m_thread->IsStepping()) 473 { 474 // This is the primary thread, let the arch do anything it needs 475 EnableHardwareSingleStep(true); 476 } 477 478 // Reset the debug status register before we resume. 479 kern_return_t kret = GetDBGState(false); 480 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() GetDBGState() => 0x%8.8x.", kret); 481 if (kret == KERN_SUCCESS) 482 { 483 DBG debug_state = m_state.context.dbg; 484 ClearWatchpointHits(debug_state); 485 kret = SetDBGState(); 486 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::ThreadWillResume() SetDBGState() => 0x%8.8x.", kret); 487 } 488} 489 490bool 491DNBArchImplX86_64::ThreadDidStop() 492{ 493 bool success = true; 494 495 m_state.InvalidateAllRegisterStates(); 496 497 // Are we stepping a single instruction? 498 if (GetGPRState(true) == KERN_SUCCESS) 499 { 500 // We are single stepping, was this the primary thread? 501 if (m_thread->IsStepping()) 502 { 503 // This was the primary thread, we need to clear the trace 504 // bit if so. 505 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 506 } 507 else 508 { 509 // The MachThread will automatically restore the suspend count 510 // in ThreadDidStop(), so we don't need to do anything here if 511 // we weren't the primary thread the last time 512 } 513 } 514 return success; 515} 516 517bool 518DNBArchImplX86_64::NotifyException(MachException::Data& exc) 519{ 520 switch (exc.exc_type) 521 { 522 case EXC_BAD_ACCESS: 523 break; 524 case EXC_BAD_INSTRUCTION: 525 break; 526 case EXC_ARITHMETIC: 527 break; 528 case EXC_EMULATION: 529 break; 530 case EXC_SOFTWARE: 531 break; 532 case EXC_BREAKPOINT: 533 if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) 534 { 535 nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS); 536 if (pc != INVALID_NUB_ADDRESS && pc > 0) 537 { 538 pc -= 1; 539 // Check for a breakpoint at one byte prior to the current PC value 540 // since the PC will be just past the trap. 541 542 nub_break_t breakID = m_thread->Process()->Breakpoints().FindIDByAddress(pc); 543 if (NUB_BREAK_ID_IS_VALID(breakID)) 544 { 545 // Backup the PC for i386 since the trap was taken and the PC 546 // is at the address following the single byte trap instruction. 547 if (m_state.context.gpr.__rip > 0) 548 { 549 m_state.context.gpr.__rip = pc; 550 // Write the new PC back out 551 SetGPRState (); 552 } 553 } 554 return true; 555 } 556 } 557 else if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 1) 558 { 559 // exc_code = EXC_I386_SGL 560 // 561 // Check whether this corresponds to a watchpoint hit event. 562 // If yes, set the exc_sub_code to the data break address. 563 nub_addr_t addr = 0; 564 uint32_t hw_index = GetHardwareWatchpointHit(addr); 565 if (hw_index != INVALID_NUB_HW_INDEX) 566 exc.exc_data[1] = addr; 567 568 return true; 569 } 570 break; 571 case EXC_SYSCALL: 572 break; 573 case EXC_MACH_SYSCALL: 574 break; 575 case EXC_RPC_ALERT: 576 break; 577 } 578 return false; 579} 580 581uint32_t 582DNBArchImplX86_64::NumSupportedHardwareWatchpoints() 583{ 584 // Available debug address registers: dr0, dr1, dr2, dr3. 585 return 4; 586} 587 588static uint32_t 589size_and_rw_bits(nub_size_t size, bool read, bool write) 590{ 591 uint32_t rw; 592 if (read) { 593 rw = 0x3; // READ or READ/WRITE 594 } else if (write) { 595 rw = 0x1; // WRITE 596 } else { 597 assert(0 && "read and write cannot both be false"); 598 } 599 600 switch (size) { 601 case 1: 602 return rw; 603 case 2: 604 return (0x1 << 2) | rw; 605 case 4: 606 return (0x3 << 2) | rw; 607 case 8: 608 return (0x2 << 2) | rw; 609 default: 610 assert(0 && "invalid size, must be one of 1, 2, 4, or 8"); 611 } 612} 613void 614DNBArchImplX86_64::SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write) 615{ 616 // Set both dr7 (debug control register) and dri (debug address register). 617 618 // dr7{7-0} encodes the local/gloabl enable bits: 619 // global enable --. .-- local enable 620 // | | 621 // v v 622 // dr0 -> bits{1-0} 623 // dr1 -> bits{3-2} 624 // dr2 -> bits{5-4} 625 // dr3 -> bits{7-6} 626 // 627 // dr7{31-16} encodes the rw/len bits: 628 // b_x+3, b_x+2, b_x+1, b_x 629 // where bits{x+1, x} => rw 630 // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io read-or-write (unused) 631 // and bits{x+3, x+2} => len 632 // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte 633 // 634 // dr0 -> bits{19-16} 635 // dr1 -> bits{23-20} 636 // dr2 -> bits{27-24} 637 // dr3 -> bits{31-28} 638 debug_state.__dr7 |= (1 << (2*hw_index) | 639 size_and_rw_bits(size, read, write) << (16+4*hw_index)); 640 switch (hw_index) { 641 case 0: 642 debug_state.__dr0 == addr; break; 643 case 1: 644 debug_state.__dr1 == addr; break; 645 case 2: 646 debug_state.__dr2 == addr; break; 647 case 3: 648 debug_state.__dr3 == addr; break; 649 default: 650 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 651 } 652 return; 653} 654 655void 656DNBArchImplX86_64::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) 657{ 658 debug_state.__dr7 &= ~(3 << (2*hw_index)); 659 switch (hw_index) { 660 case 0: 661 debug_state.__dr0 == 0; break; 662 case 1: 663 debug_state.__dr1 == 0; break; 664 case 2: 665 debug_state.__dr2 == 0; break; 666 case 3: 667 debug_state.__dr3 == 0; break; 668 default: 669 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 670 } 671 return; 672} 673 674bool 675DNBArchImplX86_64::IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index) 676{ 677 // Check dr7 (debug control register) for local/global enable bits: 678 // global enable --. .-- local enable 679 // | | 680 // v v 681 // dr0 -> bits{1-0} 682 // dr1 -> bits{3-2} 683 // dr2 -> bits{5-4} 684 // dr3 -> bits{7-6} 685 return (debug_state.__dr7 & (3 << (2*hw_index))) == 0; 686} 687 688// Resets local copy of debug status register to wait for the next debug excpetion. 689void 690DNBArchImplX86_64::ClearWatchpointHits(DBG &debug_state) 691{ 692 // See also IsWatchpointHit(). 693 debug_state.__dr6 = 0; 694 return; 695} 696 697bool 698DNBArchImplX86_64::IsWatchpointHit(const DBG &debug_state, uint32_t hw_index) 699{ 700 // Check dr6 (debug status register) whether a watchpoint hits: 701 // is watchpoint hit? 702 // | 703 // v 704 // dr0 -> bits{0} 705 // dr1 -> bits{1} 706 // dr2 -> bits{2} 707 // dr3 -> bits{3} 708 return (debug_state.__dr6 & (1 << hw_index)); 709} 710 711nub_addr_t 712DNBArchImplX86_64::GetWatchAddress(const DBG &debug_state, uint32_t hw_index) 713{ 714 switch (hw_index) { 715 case 0: 716 return debug_state.__dr0; 717 case 1: 718 return debug_state.__dr1; 719 case 2: 720 return debug_state.__dr2; 721 case 3: 722 return debug_state.__dr3; 723 default: 724 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 725 } 726} 727 728uint32_t 729DNBArchImplX86_64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write) 730{ 731 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write); 732 733 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 734 735 // Can only watch 1, 2, 4, or 8 bytes. 736 if (!(size == 1 || size == 2 || size == 4 || size == 8)) 737 return INVALID_NUB_HW_INDEX; 738 739 // We must watch for either read or write 740 if (read == false && write == false) 741 return INVALID_NUB_HW_INDEX; 742 743 // Read the debug state 744 kern_return_t kret = GetDBGState(false); 745 746 if (kret == KERN_SUCCESS) 747 { 748 // Check to make sure we have the needed hardware support 749 uint32_t i = 0; 750 751 DBG debug_state = m_state.context.dbg; 752 for (i = 0; i < num_hw_watchpoints; ++i) 753 { 754 if (IsWatchpointVacant(debug_state, i)) 755 break; 756 } 757 758 // See if we found an available hw breakpoint slot above 759 if (i < num_hw_watchpoints) 760 { 761 // Modify our local copy of the debug state, first. 762 SetWatchpoint(debug_state, i, addr, size, read, write); 763 // Now set the watch point in the inferior. 764 kret = SetDBGState(); 765 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret); 766 767 if (kret == KERN_SUCCESS) 768 return i; 769 } 770 else 771 { 772 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints); 773 } 774 } 775 return INVALID_NUB_HW_INDEX; 776} 777 778bool 779DNBArchImplX86_64::DisableHardwareWatchpoint (uint32_t hw_index) 780{ 781 kern_return_t kret = GetDBGState(false); 782 783 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 784 if (kret == KERN_SUCCESS) 785 { 786 DBG debug_state = m_state.context.dbg; 787 if (hw_index < num_hw_points && !IsWatchpointVacant(debug_state, hw_index)) 788 { 789 // Modify our local copy of the debug state, first. 790 ClearWatchpoint(debug_state, hw_index); 791 // Now disable the watch point in the inferior. 792 kret = SetDBGState(); 793 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::DisableHardwareWatchpoint( %u )", 794 hw_index); 795 796 if (kret == KERN_SUCCESS) 797 return true; 798 } 799 } 800 return false; 801} 802 803// Iterate through the debug status register; return the index of the first hit. 804uint32_t 805DNBArchImplX86_64::GetHardwareWatchpointHit(nub_addr_t &addr) 806{ 807 // Read the debug state 808 kern_return_t kret = GetDBGState(false); 809 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::GetHardwareWatchpointHit() GetDBGState() => 0x%8.8x.", kret); 810 if (kret == KERN_SUCCESS) 811 { 812 DBG debug_state = m_state.context.dbg; 813 uint32_t i, num = NumSupportedHardwareWatchpoints(); 814 for (i = 0; i < num; ++i) 815 { 816 if (IsWatchpointHit(debug_state, i)) 817 { 818 addr = GetWatchAddress(debug_state, i); 819 DNBLogThreadedIf(LOG_WATCHPOINTS, 820 "DNBArchImplX86_64::GetHardwareWatchpointHit() found => %u (addr = %8.8p).", 821 i, addr); 822 return i; 823 } 824 } 825 } 826 return INVALID_NUB_HW_INDEX; 827} 828 829// Set the single step bit in the processor status register. 830kern_return_t 831DNBArchImplX86_64::EnableHardwareSingleStep (bool enable) 832{ 833 if (GetGPRState(false) == KERN_SUCCESS) 834 { 835 const uint32_t trace_bit = 0x100u; 836 if (enable) 837 m_state.context.gpr.__rflags |= trace_bit; 838 else 839 m_state.context.gpr.__rflags &= ~trace_bit; 840 return SetGPRState(); 841 } 842 return m_state.GetError(e_regSetGPR, Read); 843} 844 845 846//---------------------------------------------------------------------- 847// Register information defintions 848//---------------------------------------------------------------------- 849 850enum 851{ 852 gpr_rax = 0, 853 gpr_rbx, 854 gpr_rcx, 855 gpr_rdx, 856 gpr_rdi, 857 gpr_rsi, 858 gpr_rbp, 859 gpr_rsp, 860 gpr_r8, 861 gpr_r9, 862 gpr_r10, 863 gpr_r11, 864 gpr_r12, 865 gpr_r13, 866 gpr_r14, 867 gpr_r15, 868 gpr_rip, 869 gpr_rflags, 870 gpr_cs, 871 gpr_fs, 872 gpr_gs, 873 k_num_gpr_regs 874}; 875 876enum { 877 fpu_fcw, 878 fpu_fsw, 879 fpu_ftw, 880 fpu_fop, 881 fpu_ip, 882 fpu_cs, 883 fpu_dp, 884 fpu_ds, 885 fpu_mxcsr, 886 fpu_mxcsrmask, 887 fpu_stmm0, 888 fpu_stmm1, 889 fpu_stmm2, 890 fpu_stmm3, 891 fpu_stmm4, 892 fpu_stmm5, 893 fpu_stmm6, 894 fpu_stmm7, 895 fpu_xmm0, 896 fpu_xmm1, 897 fpu_xmm2, 898 fpu_xmm3, 899 fpu_xmm4, 900 fpu_xmm5, 901 fpu_xmm6, 902 fpu_xmm7, 903 fpu_xmm8, 904 fpu_xmm9, 905 fpu_xmm10, 906 fpu_xmm11, 907 fpu_xmm12, 908 fpu_xmm13, 909 fpu_xmm14, 910 fpu_xmm15, 911 fpu_ymm0, 912 fpu_ymm1, 913 fpu_ymm2, 914 fpu_ymm3, 915 fpu_ymm4, 916 fpu_ymm5, 917 fpu_ymm6, 918 fpu_ymm7, 919 fpu_ymm8, 920 fpu_ymm9, 921 fpu_ymm10, 922 fpu_ymm11, 923 fpu_ymm12, 924 fpu_ymm13, 925 fpu_ymm14, 926 fpu_ymm15, 927 k_num_fpu_regs, 928 929 // Aliases 930 fpu_fctrl = fpu_fcw, 931 fpu_fstat = fpu_fsw, 932 fpu_ftag = fpu_ftw, 933 fpu_fiseg = fpu_cs, 934 fpu_fioff = fpu_ip, 935 fpu_foseg = fpu_ds, 936 fpu_fooff = fpu_dp 937}; 938 939enum { 940 exc_trapno, 941 exc_err, 942 exc_faultvaddr, 943 k_num_exc_regs, 944}; 945 946 947enum gcc_dwarf_regnums 948{ 949 gcc_dwarf_rax = 0, 950 gcc_dwarf_rdx = 1, 951 gcc_dwarf_rcx = 2, 952 gcc_dwarf_rbx = 3, 953 gcc_dwarf_rsi = 4, 954 gcc_dwarf_rdi = 5, 955 gcc_dwarf_rbp = 6, 956 gcc_dwarf_rsp = 7, 957 gcc_dwarf_r8, 958 gcc_dwarf_r9, 959 gcc_dwarf_r10, 960 gcc_dwarf_r11, 961 gcc_dwarf_r12, 962 gcc_dwarf_r13, 963 gcc_dwarf_r14, 964 gcc_dwarf_r15, 965 gcc_dwarf_rip, 966 gcc_dwarf_xmm0, 967 gcc_dwarf_xmm1, 968 gcc_dwarf_xmm2, 969 gcc_dwarf_xmm3, 970 gcc_dwarf_xmm4, 971 gcc_dwarf_xmm5, 972 gcc_dwarf_xmm6, 973 gcc_dwarf_xmm7, 974 gcc_dwarf_xmm8, 975 gcc_dwarf_xmm9, 976 gcc_dwarf_xmm10, 977 gcc_dwarf_xmm11, 978 gcc_dwarf_xmm12, 979 gcc_dwarf_xmm13, 980 gcc_dwarf_xmm14, 981 gcc_dwarf_xmm15, 982 gcc_dwarf_stmm0, 983 gcc_dwarf_stmm1, 984 gcc_dwarf_stmm2, 985 gcc_dwarf_stmm3, 986 gcc_dwarf_stmm4, 987 gcc_dwarf_stmm5, 988 gcc_dwarf_stmm6, 989 gcc_dwarf_stmm7, 990 gcc_dwarf_ymm0 = gcc_dwarf_xmm0, 991 gcc_dwarf_ymm1 = gcc_dwarf_xmm1, 992 gcc_dwarf_ymm2 = gcc_dwarf_xmm2, 993 gcc_dwarf_ymm3 = gcc_dwarf_xmm3, 994 gcc_dwarf_ymm4 = gcc_dwarf_xmm4, 995 gcc_dwarf_ymm5 = gcc_dwarf_xmm5, 996 gcc_dwarf_ymm6 = gcc_dwarf_xmm6, 997 gcc_dwarf_ymm7 = gcc_dwarf_xmm7, 998 gcc_dwarf_ymm8 = gcc_dwarf_xmm8, 999 gcc_dwarf_ymm9 = gcc_dwarf_xmm9, 1000 gcc_dwarf_ymm10 = gcc_dwarf_xmm10, 1001 gcc_dwarf_ymm11 = gcc_dwarf_xmm11, 1002 gcc_dwarf_ymm12 = gcc_dwarf_xmm12, 1003 gcc_dwarf_ymm13 = gcc_dwarf_xmm13, 1004 gcc_dwarf_ymm14 = gcc_dwarf_xmm14, 1005 gcc_dwarf_ymm15 = gcc_dwarf_xmm15 1006}; 1007 1008enum gdb_regnums 1009{ 1010 gdb_rax = 0, 1011 gdb_rbx = 1, 1012 gdb_rcx = 2, 1013 gdb_rdx = 3, 1014 gdb_rsi = 4, 1015 gdb_rdi = 5, 1016 gdb_rbp = 6, 1017 gdb_rsp = 7, 1018 gdb_r8 = 8, 1019 gdb_r9 = 9, 1020 gdb_r10 = 10, 1021 gdb_r11 = 11, 1022 gdb_r12 = 12, 1023 gdb_r13 = 13, 1024 gdb_r14 = 14, 1025 gdb_r15 = 15, 1026 gdb_rip = 16, 1027 gdb_rflags = 17, 1028 gdb_cs = 18, 1029 gdb_ss = 19, 1030 gdb_ds = 20, 1031 gdb_es = 21, 1032 gdb_fs = 22, 1033 gdb_gs = 23, 1034 gdb_stmm0 = 24, 1035 gdb_stmm1 = 25, 1036 gdb_stmm2 = 26, 1037 gdb_stmm3 = 27, 1038 gdb_stmm4 = 28, 1039 gdb_stmm5 = 29, 1040 gdb_stmm6 = 30, 1041 gdb_stmm7 = 31, 1042 gdb_fctrl = 32, gdb_fcw = gdb_fctrl, 1043 gdb_fstat = 33, gdb_fsw = gdb_fstat, 1044 gdb_ftag = 34, gdb_ftw = gdb_ftag, 1045 gdb_fiseg = 35, gdb_fpu_cs = gdb_fiseg, 1046 gdb_fioff = 36, gdb_ip = gdb_fioff, 1047 gdb_foseg = 37, gdb_fpu_ds = gdb_foseg, 1048 gdb_fooff = 38, gdb_dp = gdb_fooff, 1049 gdb_fop = 39, 1050 gdb_xmm0 = 40, 1051 gdb_xmm1 = 41, 1052 gdb_xmm2 = 42, 1053 gdb_xmm3 = 43, 1054 gdb_xmm4 = 44, 1055 gdb_xmm5 = 45, 1056 gdb_xmm6 = 46, 1057 gdb_xmm7 = 47, 1058 gdb_xmm8 = 48, 1059 gdb_xmm9 = 49, 1060 gdb_xmm10 = 50, 1061 gdb_xmm11 = 51, 1062 gdb_xmm12 = 52, 1063 gdb_xmm13 = 53, 1064 gdb_xmm14 = 54, 1065 gdb_xmm15 = 55, 1066 gdb_mxcsr = 56, 1067 gdb_ymm0 = gdb_xmm0, 1068 gdb_ymm1 = gdb_xmm1, 1069 gdb_ymm2 = gdb_xmm2, 1070 gdb_ymm3 = gdb_xmm3, 1071 gdb_ymm4 = gdb_xmm4, 1072 gdb_ymm5 = gdb_xmm5, 1073 gdb_ymm6 = gdb_xmm6, 1074 gdb_ymm7 = gdb_xmm7, 1075 gdb_ymm8 = gdb_xmm8, 1076 gdb_ymm9 = gdb_xmm9, 1077 gdb_ymm10 = gdb_xmm10, 1078 gdb_ymm11 = gdb_xmm11, 1079 gdb_ymm12 = gdb_xmm12, 1080 gdb_ymm13 = gdb_xmm13, 1081 gdb_ymm14 = gdb_xmm14, 1082 gdb_ymm15 = gdb_xmm15 1083}; 1084 1085#define GPR_OFFSET(reg) (offsetof (DNBArchImplX86_64::GPR, __##reg)) 1086#define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx)) 1087#define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx)) 1088#define EXC_OFFSET(reg) (offsetof (DNBArchImplX86_64::EXC, __##reg) + offsetof (DNBArchImplX86_64::Context, exc)) 1089 1090// This does not accurately identify the location of ymm0...7 in 1091// Context.fpu.avx. That is because there is a bunch of padding 1092// in Context.fpu.avx that we don't need. Offset macros lay out 1093// the register state that Debugserver transmits to the debugger 1094// -- not to interpret the thread_get_state info. 1095#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n)) 1096 1097#define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg)) 1098#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg)) 1099#define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg)) 1100#define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg)) 1101#define FPU_SIZE_YMM(reg) (32) 1102#define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg)) 1103 1104// These macros will auto define the register name, alt name, register size, 1105// register offset, encoding, format and native register. This ensures that 1106// the register state structures are defined correctly and have the correct 1107// sizes and offsets. 1108#define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg } 1109#define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg } 1110#define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg } 1111#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg } 1112 1113// General purpose registers for 64 bit 1114const DNBRegisterInfo 1115DNBArchImplX86_64::g_gpr_registers[] = 1116{ 1117 DEFINE_GPR (rax), 1118 DEFINE_GPR (rbx), 1119 DEFINE_GPR_ALT (rcx , "arg4", GENERIC_REGNUM_ARG4), 1120 DEFINE_GPR_ALT (rdx , "arg3", GENERIC_REGNUM_ARG3), 1121 DEFINE_GPR_ALT (rdi , "arg1", GENERIC_REGNUM_ARG1), 1122 DEFINE_GPR_ALT (rsi , "arg2", GENERIC_REGNUM_ARG2), 1123 DEFINE_GPR_ALT (rbp , "fp" , GENERIC_REGNUM_FP), 1124 DEFINE_GPR_ALT (rsp , "sp" , GENERIC_REGNUM_SP), 1125 DEFINE_GPR_ALT (r8 , "arg5", GENERIC_REGNUM_ARG5), 1126 DEFINE_GPR_ALT (r9 , "arg6", GENERIC_REGNUM_ARG6), 1127 DEFINE_GPR (r10), 1128 DEFINE_GPR (r11), 1129 DEFINE_GPR (r12), 1130 DEFINE_GPR (r13), 1131 DEFINE_GPR (r14), 1132 DEFINE_GPR (r15), 1133 DEFINE_GPR_ALT (rip , "pc", GENERIC_REGNUM_PC), 1134 DEFINE_GPR_ALT3 (rflags, "flags", GENERIC_REGNUM_FLAGS), 1135 DEFINE_GPR_ALT2 (cs, NULL), 1136 DEFINE_GPR_ALT2 (fs, NULL), 1137 DEFINE_GPR_ALT2 (gs, NULL), 1138}; 1139 1140// Floating point registers 64 bit 1141const DNBRegisterInfo 1142DNBArchImplX86_64::g_fpu_registers_no_avx[] = 1143{ 1144 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1, -1, -1, -1 }, 1145 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1, -1, -1, -1 }, 1146 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1, -1, -1, -1 }, 1147 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1, -1, -1, -1 }, 1148 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1, -1, -1, -1 }, 1149 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1, -1, -1, -1 }, 1150 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1, -1, -1, -1 }, 1151 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1, -1, -1, -1 }, 1152 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1, -1, -1, -1 }, 1153 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 1154 1155 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 1156 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1157 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1158 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1159 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1160 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 1161 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1162 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 1163 1164 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 1165 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 1166 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 1167 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 1168 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 1169 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 1170 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 1171 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 1172 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 1173 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 1174 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 1175 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1176 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1177 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 1178 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1179 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 1180}; 1181 1182const DNBRegisterInfo 1183DNBArchImplX86_64::g_fpu_registers_avx[] = 1184{ 1185 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1, -1, -1, -1 }, 1186 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1, -1, -1, -1 }, 1187 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1, -1, -1, -1 }, 1188 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1, -1, -1, -1 }, 1189 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1, -1, -1, -1 }, 1190 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1, -1, -1, -1 }, 1191 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1, -1, -1, -1 }, 1192 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1, -1, -1, -1 }, 1193 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1, -1, -1, -1 }, 1194 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 1195 1196 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 1197 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1198 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1199 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1200 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1201 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 1202 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1203 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 1204 1205 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 1206 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 1207 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 1208 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 1209 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 1210 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 1211 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 1212 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 1213 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 1214 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 1215 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 1216 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1217 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1218 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 1219 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1220 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 1221 1222 { e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1, gdb_ymm0 }, 1223 { e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1, gdb_ymm1 }, 1224 { e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1, gdb_ymm2 }, 1225 { e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1, gdb_ymm3 }, 1226 { e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1, gdb_ymm4 }, 1227 { e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1, gdb_ymm5 }, 1228 { e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1, gdb_ymm6 }, 1229 { e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1, gdb_ymm7 }, 1230 { e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1, gdb_ymm8 }, 1231 { e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1, gdb_ymm9 }, 1232 { e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1, gdb_ymm10 }, 1233 { e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1, gdb_ymm11 }, 1234 { e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1, gdb_ymm12 }, 1235 { e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1, gdb_ymm13 }, 1236 { e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1, gdb_ymm14 }, 1237 { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1, gdb_ymm15 } 1238}; 1239 1240// Exception registers 1241 1242const DNBRegisterInfo 1243DNBArchImplX86_64::g_exc_registers[] = 1244{ 1245 { e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1, -1, -1, -1 }, 1246 { e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1, -1, -1, -1 }, 1247 { e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1, -1, -1, -1 } 1248}; 1249 1250// Number of registers in each register set 1251const size_t DNBArchImplX86_64::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo); 1252const size_t DNBArchImplX86_64::k_num_fpu_registers_no_avx = sizeof(g_fpu_registers_no_avx)/sizeof(DNBRegisterInfo); 1253const size_t DNBArchImplX86_64::k_num_fpu_registers_avx = sizeof(g_fpu_registers_avx)/sizeof(DNBRegisterInfo); 1254const size_t DNBArchImplX86_64::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo); 1255const size_t DNBArchImplX86_64::k_num_all_registers_no_avx = k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers; 1256const size_t DNBArchImplX86_64::k_num_all_registers_avx = k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers; 1257 1258//---------------------------------------------------------------------- 1259// Register set definitions. The first definitions at register set index 1260// of zero is for all registers, followed by other registers sets. The 1261// register information for the all register set need not be filled in. 1262//---------------------------------------------------------------------- 1263const DNBRegisterSetInfo 1264DNBArchImplX86_64::g_reg_sets_no_avx[] = 1265{ 1266 { "x86_64 Registers", NULL, k_num_all_registers_no_avx }, 1267 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1268 { "Floating Point Registers", g_fpu_registers_no_avx, k_num_fpu_registers_no_avx }, 1269 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1270}; 1271 1272const DNBRegisterSetInfo 1273DNBArchImplX86_64::g_reg_sets_avx[] = 1274{ 1275 { "x86_64 Registers", NULL, k_num_all_registers_avx }, 1276 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1277 { "Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx }, 1278 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1279}; 1280 1281// Total number of register sets for this architecture 1282const size_t DNBArchImplX86_64::k_num_register_sets = sizeof(g_reg_sets_avx)/sizeof(DNBRegisterSetInfo); 1283 1284 1285DNBArchProtocol * 1286DNBArchImplX86_64::Create (MachThread *thread) 1287{ 1288 return new DNBArchImplX86_64 (thread); 1289} 1290 1291const uint8_t * const 1292DNBArchImplX86_64::SoftwareBreakpointOpcode (nub_size_t byte_size) 1293{ 1294 static const uint8_t g_breakpoint_opcode[] = { 0xCC }; 1295 if (byte_size == 1) 1296 return g_breakpoint_opcode; 1297 return NULL; 1298} 1299 1300const DNBRegisterSetInfo * 1301DNBArchImplX86_64::GetRegisterSetInfo(nub_size_t *num_reg_sets) 1302{ 1303 *num_reg_sets = k_num_register_sets; 1304 1305 if (CPUHasAVX() || FORCE_AVX_REGS) 1306 return g_reg_sets_avx; 1307 else 1308 return g_reg_sets_no_avx; 1309} 1310 1311void 1312DNBArchImplX86_64::Initialize() 1313{ 1314 DNBArchPluginInfo arch_plugin_info = 1315 { 1316 CPU_TYPE_X86_64, 1317 DNBArchImplX86_64::Create, 1318 DNBArchImplX86_64::GetRegisterSetInfo, 1319 DNBArchImplX86_64::SoftwareBreakpointOpcode 1320 }; 1321 1322 // Register this arch plug-in with the main protocol class 1323 DNBArchProtocol::RegisterArchPlugin (arch_plugin_info); 1324} 1325 1326bool 1327DNBArchImplX86_64::GetRegisterValue(int set, int reg, DNBRegisterValue *value) 1328{ 1329 if (set == REGISTER_SET_GENERIC) 1330 { 1331 switch (reg) 1332 { 1333 case GENERIC_REGNUM_PC: // Program Counter 1334 set = e_regSetGPR; 1335 reg = gpr_rip; 1336 break; 1337 1338 case GENERIC_REGNUM_SP: // Stack Pointer 1339 set = e_regSetGPR; 1340 reg = gpr_rsp; 1341 break; 1342 1343 case GENERIC_REGNUM_FP: // Frame Pointer 1344 set = e_regSetGPR; 1345 reg = gpr_rbp; 1346 break; 1347 1348 case GENERIC_REGNUM_FLAGS: // Processor flags register 1349 set = e_regSetGPR; 1350 reg = gpr_rflags; 1351 break; 1352 1353 case GENERIC_REGNUM_RA: // Return Address 1354 default: 1355 return false; 1356 } 1357 } 1358 1359 if (GetRegisterState(set, false) != KERN_SUCCESS) 1360 return false; 1361 1362 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1363 if (regInfo) 1364 { 1365 value->info = *regInfo; 1366 switch (set) 1367 { 1368 case e_regSetGPR: 1369 if (reg < k_num_gpr_registers) 1370 { 1371 value->value.uint64 = ((uint64_t*)(&m_state.context.gpr))[reg]; 1372 return true; 1373 } 1374 break; 1375 1376 case e_regSetFPU: 1377 if (CPUHasAVX() || FORCE_AVX_REGS) 1378 { 1379 switch (reg) 1380 { 1381 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true; 1382 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true; 1383 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true; 1384 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true; 1385 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true; 1386 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true; 1387 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true; 1388 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true; 1389 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true; 1390 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true; 1391 1392 case fpu_stmm0: 1393 case fpu_stmm1: 1394 case fpu_stmm2: 1395 case fpu_stmm3: 1396 case fpu_stmm4: 1397 case fpu_stmm5: 1398 case fpu_stmm6: 1399 case fpu_stmm7: 1400 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1401 return true; 1402 1403 case fpu_xmm0: 1404 case fpu_xmm1: 1405 case fpu_xmm2: 1406 case fpu_xmm3: 1407 case fpu_xmm4: 1408 case fpu_xmm5: 1409 case fpu_xmm6: 1410 case fpu_xmm7: 1411 case fpu_xmm8: 1412 case fpu_xmm9: 1413 case fpu_xmm10: 1414 case fpu_xmm11: 1415 case fpu_xmm12: 1416 case fpu_xmm13: 1417 case fpu_xmm14: 1418 case fpu_xmm15: 1419 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1420 return true; 1421 1422 case fpu_ymm0: 1423 case fpu_ymm1: 1424 case fpu_ymm2: 1425 case fpu_ymm3: 1426 case fpu_ymm4: 1427 case fpu_ymm5: 1428 case fpu_ymm6: 1429 case fpu_ymm7: 1430 case fpu_ymm8: 1431 case fpu_ymm9: 1432 case fpu_ymm10: 1433 case fpu_ymm11: 1434 case fpu_ymm12: 1435 case fpu_ymm13: 1436 case fpu_ymm14: 1437 case fpu_ymm15: 1438 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16); 1439 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16); 1440 return true; 1441 } 1442 } 1443 else 1444 { 1445 switch (reg) 1446 { 1447 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true; 1448 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true; 1449 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true; 1450 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true; 1451 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true; 1452 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true; 1453 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true; 1454 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true; 1455 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true; 1456 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true; 1457 1458 case fpu_stmm0: 1459 case fpu_stmm1: 1460 case fpu_stmm2: 1461 case fpu_stmm3: 1462 case fpu_stmm4: 1463 case fpu_stmm5: 1464 case fpu_stmm6: 1465 case fpu_stmm7: 1466 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1467 return true; 1468 1469 case fpu_xmm0: 1470 case fpu_xmm1: 1471 case fpu_xmm2: 1472 case fpu_xmm3: 1473 case fpu_xmm4: 1474 case fpu_xmm5: 1475 case fpu_xmm6: 1476 case fpu_xmm7: 1477 case fpu_xmm8: 1478 case fpu_xmm9: 1479 case fpu_xmm10: 1480 case fpu_xmm11: 1481 case fpu_xmm12: 1482 case fpu_xmm13: 1483 case fpu_xmm14: 1484 case fpu_xmm15: 1485 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1486 return true; 1487 } 1488 } 1489 break; 1490 1491 case e_regSetEXC: 1492 switch (reg) 1493 { 1494 case exc_trapno: value->value.uint32 = m_state.context.exc.__trapno; return true; 1495 case exc_err: value->value.uint32 = m_state.context.exc.__err; return true; 1496 case exc_faultvaddr:value->value.uint64 = m_state.context.exc.__faultvaddr; return true; 1497 } 1498 break; 1499 } 1500 } 1501 return false; 1502} 1503 1504 1505bool 1506DNBArchImplX86_64::SetRegisterValue(int set, int reg, const DNBRegisterValue *value) 1507{ 1508 if (set == REGISTER_SET_GENERIC) 1509 { 1510 switch (reg) 1511 { 1512 case GENERIC_REGNUM_PC: // Program Counter 1513 set = e_regSetGPR; 1514 reg = gpr_rip; 1515 break; 1516 1517 case GENERIC_REGNUM_SP: // Stack Pointer 1518 set = e_regSetGPR; 1519 reg = gpr_rsp; 1520 break; 1521 1522 case GENERIC_REGNUM_FP: // Frame Pointer 1523 set = e_regSetGPR; 1524 reg = gpr_rbp; 1525 break; 1526 1527 case GENERIC_REGNUM_FLAGS: // Processor flags register 1528 set = e_regSetGPR; 1529 reg = gpr_rflags; 1530 break; 1531 1532 case GENERIC_REGNUM_RA: // Return Address 1533 default: 1534 return false; 1535 } 1536 } 1537 1538 if (GetRegisterState(set, false) != KERN_SUCCESS) 1539 return false; 1540 1541 bool success = false; 1542 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1543 if (regInfo) 1544 { 1545 switch (set) 1546 { 1547 case e_regSetGPR: 1548 if (reg < k_num_gpr_registers) 1549 { 1550 ((uint64_t*)(&m_state.context.gpr))[reg] = value->value.uint64; 1551 success = true; 1552 } 1553 break; 1554 1555 case e_regSetFPU: 1556 if (CPUHasAVX() || FORCE_AVX_REGS) 1557 { 1558 switch (reg) 1559 { 1560 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1561 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1562 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break; 1563 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break; 1564 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break; 1565 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break; 1566 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break; 1567 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break; 1568 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1569 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1570 1571 case fpu_stmm0: 1572 case fpu_stmm1: 1573 case fpu_stmm2: 1574 case fpu_stmm3: 1575 case fpu_stmm4: 1576 case fpu_stmm5: 1577 case fpu_stmm6: 1578 case fpu_stmm7: 1579 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1580 success = true; 1581 break; 1582 1583 case fpu_xmm0: 1584 case fpu_xmm1: 1585 case fpu_xmm2: 1586 case fpu_xmm3: 1587 case fpu_xmm4: 1588 case fpu_xmm5: 1589 case fpu_xmm6: 1590 case fpu_xmm7: 1591 case fpu_xmm8: 1592 case fpu_xmm9: 1593 case fpu_xmm10: 1594 case fpu_xmm11: 1595 case fpu_xmm12: 1596 case fpu_xmm13: 1597 case fpu_xmm14: 1598 case fpu_xmm15: 1599 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1600 success = true; 1601 break; 1602 1603 case fpu_ymm0: 1604 case fpu_ymm1: 1605 case fpu_ymm2: 1606 case fpu_ymm3: 1607 case fpu_ymm4: 1608 case fpu_ymm5: 1609 case fpu_ymm6: 1610 case fpu_ymm7: 1611 case fpu_ymm8: 1612 case fpu_ymm9: 1613 case fpu_ymm10: 1614 case fpu_ymm11: 1615 case fpu_ymm12: 1616 case fpu_ymm13: 1617 case fpu_ymm14: 1618 case fpu_ymm15: 1619 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16); 1620 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16); 1621 return true; 1622 } 1623 } 1624 else 1625 { 1626 switch (reg) 1627 { 1628 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1629 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1630 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break; 1631 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break; 1632 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break; 1633 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break; 1634 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break; 1635 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break; 1636 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1637 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1638 1639 case fpu_stmm0: 1640 case fpu_stmm1: 1641 case fpu_stmm2: 1642 case fpu_stmm3: 1643 case fpu_stmm4: 1644 case fpu_stmm5: 1645 case fpu_stmm6: 1646 case fpu_stmm7: 1647 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1648 success = true; 1649 break; 1650 1651 case fpu_xmm0: 1652 case fpu_xmm1: 1653 case fpu_xmm2: 1654 case fpu_xmm3: 1655 case fpu_xmm4: 1656 case fpu_xmm5: 1657 case fpu_xmm6: 1658 case fpu_xmm7: 1659 case fpu_xmm8: 1660 case fpu_xmm9: 1661 case fpu_xmm10: 1662 case fpu_xmm11: 1663 case fpu_xmm12: 1664 case fpu_xmm13: 1665 case fpu_xmm14: 1666 case fpu_xmm15: 1667 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1668 success = true; 1669 break; 1670 } 1671 } 1672 break; 1673 1674 case e_regSetEXC: 1675 switch (reg) 1676 { 1677 case exc_trapno: m_state.context.exc.__trapno = value->value.uint32; success = true; break; 1678 case exc_err: m_state.context.exc.__err = value->value.uint32; success = true; break; 1679 case exc_faultvaddr:m_state.context.exc.__faultvaddr = value->value.uint64; success = true; break; 1680 } 1681 break; 1682 } 1683 } 1684 1685 if (success) 1686 return SetRegisterState(set) == KERN_SUCCESS; 1687 return false; 1688} 1689 1690 1691nub_size_t 1692DNBArchImplX86_64::GetRegisterContext (void *buf, nub_size_t buf_len) 1693{ 1694 nub_size_t size = sizeof (m_state.context); 1695 1696 if (buf && buf_len) 1697 { 1698 if (size > buf_len) 1699 size = buf_len; 1700 1701 bool force = false; 1702 if (GetGPRState(force) | GetFPUState(force) | GetEXCState(force)) 1703 return 0; 1704 ::memcpy (buf, &m_state.context, size); 1705 } 1706 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1707 // Return the size of the register context even if NULL was passed in 1708 return size; 1709} 1710 1711nub_size_t 1712DNBArchImplX86_64::SetRegisterContext (const void *buf, nub_size_t buf_len) 1713{ 1714 nub_size_t size = sizeof (m_state.context); 1715 if (buf == NULL || buf_len == 0) 1716 size = 0; 1717 1718 if (size) 1719 { 1720 if (size > buf_len) 1721 size = buf_len; 1722 1723 ::memcpy (&m_state.context, buf, size); 1724 SetGPRState(); 1725 SetFPUState(); 1726 SetEXCState(); 1727 } 1728 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1729 return size; 1730} 1731 1732 1733kern_return_t 1734DNBArchImplX86_64::GetRegisterState(int set, bool force) 1735{ 1736 switch (set) 1737 { 1738 case e_regSetALL: return GetGPRState(force) | GetFPUState(force) | GetEXCState(force); 1739 case e_regSetGPR: return GetGPRState(force); 1740 case e_regSetFPU: return GetFPUState(force); 1741 case e_regSetEXC: return GetEXCState(force); 1742 default: break; 1743 } 1744 return KERN_INVALID_ARGUMENT; 1745} 1746 1747kern_return_t 1748DNBArchImplX86_64::SetRegisterState(int set) 1749{ 1750 // Make sure we have a valid context to set. 1751 if (RegisterSetStateIsValid(set)) 1752 { 1753 switch (set) 1754 { 1755 case e_regSetALL: return SetGPRState() | SetFPUState() | SetEXCState(); 1756 case e_regSetGPR: return SetGPRState(); 1757 case e_regSetFPU: return SetFPUState(); 1758 case e_regSetEXC: return SetEXCState(); 1759 default: break; 1760 } 1761 } 1762 return KERN_INVALID_ARGUMENT; 1763} 1764 1765bool 1766DNBArchImplX86_64::RegisterSetStateIsValid (int set) const 1767{ 1768 return m_state.RegsAreValid(set); 1769} 1770 1771 1772 1773#endif // #if defined (__i386__) || defined (__x86_64__) 1774