DNBArchImplX86_64.cpp revision fe98a2e6d17f0cb3ffa4a071bb43eb76c339adef
1//===-- DNBArchImplX86_64.cpp -----------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Created by Greg Clayton on 6/25/07. 11// 12//===----------------------------------------------------------------------===// 13 14#if defined (__i386__) || defined (__x86_64__) 15 16#include <sys/cdefs.h> 17 18#include "MacOSX/x86_64/DNBArchImplX86_64.h" 19#include "DNBLog.h" 20#include "MachThread.h" 21#include "MachProcess.h" 22#include <mach/mach.h> 23#include <stdlib.h> 24 25#if defined (LLDB_DEBUGSERVER_RELEASE) || defined (LLDB_DEBUGSERVER_DEBUG) 26enum debugState { 27 debugStateUnknown, 28 debugStateOff, 29 debugStateOn 30}; 31 32static debugState sFPUDebugState = debugStateUnknown; 33static debugState sAVXForceState = debugStateUnknown; 34 35static bool DebugFPURegs () 36{ 37 if (sFPUDebugState == debugStateUnknown) 38 { 39 if (getenv("DNB_DEBUG_FPU_REGS")) 40 sFPUDebugState = debugStateOn; 41 else 42 sFPUDebugState = debugStateOff; 43 } 44 45 return (sFPUDebugState == debugStateOn); 46} 47 48static bool ForceAVXRegs () 49{ 50 if (sFPUDebugState == debugStateUnknown) 51 { 52 if (getenv("DNB_DEBUG_X86_FORCE_AVX_REGS")) 53 sAVXForceState = debugStateOn; 54 else 55 sAVXForceState = debugStateOff; 56 } 57 58 return (sAVXForceState == debugStateOn); 59} 60 61#define DEBUG_FPU_REGS (DebugFPURegs()) 62#define FORCE_AVX_REGS (ForceAVXRegs()) 63#else 64#define DEBUG_FPU_REGS (0) 65#define FORCE_AVX_REGS (0) 66#endif 67 68enum DNBArchImplX86_64::AVXPresence DNBArchImplX86_64::s_has_avx = DNBArchImplX86_64::kAVXUnknown; 69 70uint64_t 71DNBArchImplX86_64::GetPC(uint64_t failValue) 72{ 73 // Get program counter 74 if (GetGPRState(false) == KERN_SUCCESS) 75 return m_state.context.gpr.__rip; 76 return failValue; 77} 78 79kern_return_t 80DNBArchImplX86_64::SetPC(uint64_t value) 81{ 82 // Get program counter 83 kern_return_t err = GetGPRState(false); 84 if (err == KERN_SUCCESS) 85 { 86 m_state.context.gpr.__rip = value; 87 err = SetGPRState(); 88 } 89 return err == KERN_SUCCESS; 90} 91 92uint64_t 93DNBArchImplX86_64::GetSP(uint64_t failValue) 94{ 95 // Get stack pointer 96 if (GetGPRState(false) == KERN_SUCCESS) 97 return m_state.context.gpr.__rsp; 98 return failValue; 99} 100 101// Uncomment the value below to verify the values in the debugger. 102//#define DEBUG_GPR_VALUES 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 103 104kern_return_t 105DNBArchImplX86_64::GetGPRState(bool force) 106{ 107 if (force || m_state.GetError(e_regSetGPR, Read)) 108 { 109 kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 110 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (GetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 111 112#if DEBUG_GPR_VALUES 113 m_state.context.gpr.__rax = ('a' << 8) + 'x'; 114 m_state.context.gpr.__rbx = ('b' << 8) + 'x'; 115 m_state.context.gpr.__rcx = ('c' << 8) + 'x'; 116 m_state.context.gpr.__rdx = ('d' << 8) + 'x'; 117 m_state.context.gpr.__rdi = ('d' << 8) + 'i'; 118 m_state.context.gpr.__rsi = ('s' << 8) + 'i'; 119 m_state.context.gpr.__rbp = ('b' << 8) + 'p'; 120 m_state.context.gpr.__rsp = ('s' << 8) + 'p'; 121 m_state.context.gpr.__r8 = ('r' << 8) + '8'; 122 m_state.context.gpr.__r9 = ('r' << 8) + '9'; 123 m_state.context.gpr.__r10 = ('r' << 8) + 'a'; 124 m_state.context.gpr.__r11 = ('r' << 8) + 'b'; 125 m_state.context.gpr.__r12 = ('r' << 8) + 'c'; 126 m_state.context.gpr.__r13 = ('r' << 8) + 'd'; 127 m_state.context.gpr.__r14 = ('r' << 8) + 'e'; 128 m_state.context.gpr.__r15 = ('r' << 8) + 'f'; 129 m_state.context.gpr.__rip = ('i' << 8) + 'p'; 130 m_state.context.gpr.__rflags = ('f' << 8) + 'l'; 131 m_state.context.gpr.__cs = ('c' << 8) + 's'; 132 m_state.context.gpr.__fs = ('f' << 8) + 's'; 133 m_state.context.gpr.__gs = ('g' << 8) + 's'; 134 m_state.SetError(e_regSetGPR, Read, 0); 135#else 136 mach_msg_type_number_t count = e_regSetWordSizeGPR; 137 m_state.SetError(e_regSetGPR, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, &count)); 138 DNBLogThreadedIf (LOG_THREAD, "::thread_get_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 139 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 140 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 141 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 142 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 143 "\n\trip = %16.16llx" 144 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 145 m_thread->ThreadID(), x86_THREAD_STATE64, x86_THREAD_STATE64_COUNT, 146 m_state.GetError(e_regSetGPR, Read), 147 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 148 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 149 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 150 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 151 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 152 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 153 m_state.context.gpr.__cs,m_state.context.gpr.__fs, m_state.context.gpr.__gs); 154 155 // DNBLogThreadedIf (LOG_THREAD, "thread_get_state(0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 156 // "\n\trax = %16.16llx" 157 // "\n\trbx = %16.16llx" 158 // "\n\trcx = %16.16llx" 159 // "\n\trdx = %16.16llx" 160 // "\n\trdi = %16.16llx" 161 // "\n\trsi = %16.16llx" 162 // "\n\trbp = %16.16llx" 163 // "\n\trsp = %16.16llx" 164 // "\n\t r8 = %16.16llx" 165 // "\n\t r9 = %16.16llx" 166 // "\n\tr10 = %16.16llx" 167 // "\n\tr11 = %16.16llx" 168 // "\n\tr12 = %16.16llx" 169 // "\n\tr13 = %16.16llx" 170 // "\n\tr14 = %16.16llx" 171 // "\n\tr15 = %16.16llx" 172 // "\n\trip = %16.16llx" 173 // "\n\tflg = %16.16llx" 174 // "\n\t cs = %16.16llx" 175 // "\n\t fs = %16.16llx" 176 // "\n\t gs = %16.16llx", 177 // m_thread->ThreadID(), 178 // x86_THREAD_STATE64, 179 // x86_THREAD_STATE64_COUNT, 180 // m_state.GetError(e_regSetGPR, Read), 181 // m_state.context.gpr.__rax, 182 // m_state.context.gpr.__rbx, 183 // m_state.context.gpr.__rcx, 184 // m_state.context.gpr.__rdx, 185 // m_state.context.gpr.__rdi, 186 // m_state.context.gpr.__rsi, 187 // m_state.context.gpr.__rbp, 188 // m_state.context.gpr.__rsp, 189 // m_state.context.gpr.__r8, 190 // m_state.context.gpr.__r9, 191 // m_state.context.gpr.__r10, 192 // m_state.context.gpr.__r11, 193 // m_state.context.gpr.__r12, 194 // m_state.context.gpr.__r13, 195 // m_state.context.gpr.__r14, 196 // m_state.context.gpr.__r15, 197 // m_state.context.gpr.__rip, 198 // m_state.context.gpr.__rflags, 199 // m_state.context.gpr.__cs, 200 // m_state.context.gpr.__fs, 201 // m_state.context.gpr.__gs); 202#endif 203 } 204 return m_state.GetError(e_regSetGPR, Read); 205} 206 207// Uncomment the value below to verify the values in the debugger. 208//#define DEBUG_FPU_REGS 1 // DO NOT CHECK IN WITH THIS DEFINE ENABLED 209 210kern_return_t 211DNBArchImplX86_64::GetFPUState(bool force) 212{ 213 if (force || m_state.GetError(e_regSetFPU, Read)) 214 { 215 if (DEBUG_FPU_REGS) { 216 if (CPUHasAVX() || FORCE_AVX_REGS) 217 { 218 m_state.context.fpu.avx.__fpu_reserved[0] = -1; 219 m_state.context.fpu.avx.__fpu_reserved[1] = -1; 220 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234; 221 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678; 222 m_state.context.fpu.avx.__fpu_ftw = 1; 223 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX; 224 m_state.context.fpu.avx.__fpu_fop = 2; 225 m_state.context.fpu.avx.__fpu_ip = 3; 226 m_state.context.fpu.avx.__fpu_cs = 4; 227 m_state.context.fpu.avx.__fpu_rsrv2 = 5; 228 m_state.context.fpu.avx.__fpu_dp = 6; 229 m_state.context.fpu.avx.__fpu_ds = 7; 230 m_state.context.fpu.avx.__fpu_rsrv3 = UINT16_MAX; 231 m_state.context.fpu.avx.__fpu_mxcsr = 8; 232 m_state.context.fpu.avx.__fpu_mxcsrmask = 9; 233 int i; 234 for (i=0; i<16; ++i) 235 { 236 if (i<10) 237 { 238 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 239 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 240 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 241 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 242 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 243 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 244 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 245 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 246 } 247 else 248 { 249 m_state.context.fpu.avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 250 m_state.context.fpu.avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 251 m_state.context.fpu.avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 252 m_state.context.fpu.avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 253 m_state.context.fpu.avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 254 m_state.context.fpu.avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 255 m_state.context.fpu.avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 256 m_state.context.fpu.avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 257 } 258 259 m_state.context.fpu.avx.__fpu_xmm0.__xmm_reg[i] = '0'; 260 m_state.context.fpu.avx.__fpu_xmm1.__xmm_reg[i] = '1'; 261 m_state.context.fpu.avx.__fpu_xmm2.__xmm_reg[i] = '2'; 262 m_state.context.fpu.avx.__fpu_xmm3.__xmm_reg[i] = '3'; 263 m_state.context.fpu.avx.__fpu_xmm4.__xmm_reg[i] = '4'; 264 m_state.context.fpu.avx.__fpu_xmm5.__xmm_reg[i] = '5'; 265 m_state.context.fpu.avx.__fpu_xmm6.__xmm_reg[i] = '6'; 266 m_state.context.fpu.avx.__fpu_xmm7.__xmm_reg[i] = '7'; 267 m_state.context.fpu.avx.__fpu_xmm8.__xmm_reg[i] = '8'; 268 m_state.context.fpu.avx.__fpu_xmm9.__xmm_reg[i] = '9'; 269 m_state.context.fpu.avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 270 m_state.context.fpu.avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 271 m_state.context.fpu.avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 272 m_state.context.fpu.avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 273 m_state.context.fpu.avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 274 m_state.context.fpu.avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 275 276 m_state.context.fpu.avx.__fpu_ymmh0.__xmm_reg[i] = '0'; 277 m_state.context.fpu.avx.__fpu_ymmh1.__xmm_reg[i] = '1'; 278 m_state.context.fpu.avx.__fpu_ymmh2.__xmm_reg[i] = '2'; 279 m_state.context.fpu.avx.__fpu_ymmh3.__xmm_reg[i] = '3'; 280 m_state.context.fpu.avx.__fpu_ymmh4.__xmm_reg[i] = '4'; 281 m_state.context.fpu.avx.__fpu_ymmh5.__xmm_reg[i] = '5'; 282 m_state.context.fpu.avx.__fpu_ymmh6.__xmm_reg[i] = '6'; 283 m_state.context.fpu.avx.__fpu_ymmh7.__xmm_reg[i] = '7'; 284 m_state.context.fpu.avx.__fpu_ymmh8.__xmm_reg[i] = '8'; 285 m_state.context.fpu.avx.__fpu_ymmh9.__xmm_reg[i] = '9'; 286 m_state.context.fpu.avx.__fpu_ymmh10.__xmm_reg[i] = 'A'; 287 m_state.context.fpu.avx.__fpu_ymmh11.__xmm_reg[i] = 'B'; 288 m_state.context.fpu.avx.__fpu_ymmh12.__xmm_reg[i] = 'C'; 289 m_state.context.fpu.avx.__fpu_ymmh13.__xmm_reg[i] = 'D'; 290 m_state.context.fpu.avx.__fpu_ymmh14.__xmm_reg[i] = 'E'; 291 m_state.context.fpu.avx.__fpu_ymmh15.__xmm_reg[i] = 'F'; 292 } 293 for (i=0; i<sizeof(m_state.context.fpu.avx.__fpu_rsrv4); ++i) 294 m_state.context.fpu.avx.__fpu_rsrv4[i] = INT8_MIN; 295 m_state.context.fpu.avx.__fpu_reserved1 = -1; 296 for (i=0; i<sizeof(m_state.context.fpu.avx.__avx_reserved1); ++i) 297 m_state.context.fpu.avx.__avx_reserved1[i] = INT8_MIN; 298 m_state.SetError(e_regSetFPU, Read, 0); 299 } 300 else 301 { 302 m_state.context.fpu.no_avx.__fpu_reserved[0] = -1; 303 m_state.context.fpu.no_avx.__fpu_reserved[1] = -1; 304 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fcw) = 0x1234; 305 *(uint16_t *)&(m_state.context.fpu.no_avx.__fpu_fsw) = 0x5678; 306 m_state.context.fpu.no_avx.__fpu_ftw = 1; 307 m_state.context.fpu.no_avx.__fpu_rsrv1 = UINT8_MAX; 308 m_state.context.fpu.no_avx.__fpu_fop = 2; 309 m_state.context.fpu.no_avx.__fpu_ip = 3; 310 m_state.context.fpu.no_avx.__fpu_cs = 4; 311 m_state.context.fpu.no_avx.__fpu_rsrv2 = 5; 312 m_state.context.fpu.no_avx.__fpu_dp = 6; 313 m_state.context.fpu.no_avx.__fpu_ds = 7; 314 m_state.context.fpu.no_avx.__fpu_rsrv3 = UINT16_MAX; 315 m_state.context.fpu.no_avx.__fpu_mxcsr = 8; 316 m_state.context.fpu.no_avx.__fpu_mxcsrmask = 9; 317 int i; 318 for (i=0; i<16; ++i) 319 { 320 if (i<10) 321 { 322 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = 'a'; 323 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = 'b'; 324 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = 'c'; 325 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = 'd'; 326 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = 'e'; 327 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = 'f'; 328 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = 'g'; 329 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = 'h'; 330 } 331 else 332 { 333 m_state.context.fpu.no_avx.__fpu_stmm0.__mmst_reg[i] = INT8_MIN; 334 m_state.context.fpu.no_avx.__fpu_stmm1.__mmst_reg[i] = INT8_MIN; 335 m_state.context.fpu.no_avx.__fpu_stmm2.__mmst_reg[i] = INT8_MIN; 336 m_state.context.fpu.no_avx.__fpu_stmm3.__mmst_reg[i] = INT8_MIN; 337 m_state.context.fpu.no_avx.__fpu_stmm4.__mmst_reg[i] = INT8_MIN; 338 m_state.context.fpu.no_avx.__fpu_stmm5.__mmst_reg[i] = INT8_MIN; 339 m_state.context.fpu.no_avx.__fpu_stmm6.__mmst_reg[i] = INT8_MIN; 340 m_state.context.fpu.no_avx.__fpu_stmm7.__mmst_reg[i] = INT8_MIN; 341 } 342 343 m_state.context.fpu.no_avx.__fpu_xmm0.__xmm_reg[i] = '0'; 344 m_state.context.fpu.no_avx.__fpu_xmm1.__xmm_reg[i] = '1'; 345 m_state.context.fpu.no_avx.__fpu_xmm2.__xmm_reg[i] = '2'; 346 m_state.context.fpu.no_avx.__fpu_xmm3.__xmm_reg[i] = '3'; 347 m_state.context.fpu.no_avx.__fpu_xmm4.__xmm_reg[i] = '4'; 348 m_state.context.fpu.no_avx.__fpu_xmm5.__xmm_reg[i] = '5'; 349 m_state.context.fpu.no_avx.__fpu_xmm6.__xmm_reg[i] = '6'; 350 m_state.context.fpu.no_avx.__fpu_xmm7.__xmm_reg[i] = '7'; 351 m_state.context.fpu.no_avx.__fpu_xmm8.__xmm_reg[i] = '8'; 352 m_state.context.fpu.no_avx.__fpu_xmm9.__xmm_reg[i] = '9'; 353 m_state.context.fpu.no_avx.__fpu_xmm10.__xmm_reg[i] = 'A'; 354 m_state.context.fpu.no_avx.__fpu_xmm11.__xmm_reg[i] = 'B'; 355 m_state.context.fpu.no_avx.__fpu_xmm12.__xmm_reg[i] = 'C'; 356 m_state.context.fpu.no_avx.__fpu_xmm13.__xmm_reg[i] = 'D'; 357 m_state.context.fpu.no_avx.__fpu_xmm14.__xmm_reg[i] = 'E'; 358 m_state.context.fpu.no_avx.__fpu_xmm15.__xmm_reg[i] = 'F'; 359 } 360 for (i=0; i<sizeof(m_state.context.fpu.no_avx.__fpu_rsrv4); ++i) 361 m_state.context.fpu.no_avx.__fpu_rsrv4[i] = INT8_MIN; 362 m_state.context.fpu.no_avx.__fpu_reserved1 = -1; 363 m_state.SetError(e_regSetFPU, Read, 0); 364 } 365 } 366 else 367 { 368 if (CPUHasAVX() || FORCE_AVX_REGS) 369 { 370 mach_msg_type_number_t count = e_regSetWordSizeAVX; 371 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, &count)); 372 } 373 else 374 { 375 mach_msg_type_number_t count = e_regSetWordSizeFPR; 376 m_state.SetError(e_regSetFPU, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, &count)); 377 } 378 } 379 } 380 return m_state.GetError(e_regSetFPU, Read); 381} 382 383kern_return_t 384DNBArchImplX86_64::GetEXCState(bool force) 385{ 386 if (force || m_state.GetError(e_regSetEXC, Read)) 387 { 388 mach_msg_type_number_t count = e_regSetWordSizeEXC; 389 m_state.SetError(e_regSetEXC, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, &count)); 390 } 391 return m_state.GetError(e_regSetEXC, Read); 392} 393 394kern_return_t 395DNBArchImplX86_64::SetGPRState() 396{ 397 kern_return_t kret = ::thread_abort_safely(m_thread->ThreadID()); 398 DNBLogThreadedIf (LOG_THREAD, "thread = 0x%4.4x calling thread_abort_safely (tid) => %u (SetGPRState() for stop_count = %u)", m_thread->ThreadID(), kret, m_thread->Process()->StopCount()); 399 400 m_state.SetError(e_regSetGPR, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_THREAD_STATE, (thread_state_t)&m_state.context.gpr, e_regSetWordSizeGPR)); 401 DNBLogThreadedIf (LOG_THREAD, "::thread_set_state (0x%4.4x, %u, &gpr, %u) => 0x%8.8x" 402 "\n\trax = %16.16llx rbx = %16.16llx rcx = %16.16llx rdx = %16.16llx" 403 "\n\trdi = %16.16llx rsi = %16.16llx rbp = %16.16llx rsp = %16.16llx" 404 "\n\t r8 = %16.16llx r9 = %16.16llx r10 = %16.16llx r11 = %16.16llx" 405 "\n\tr12 = %16.16llx r13 = %16.16llx r14 = %16.16llx r15 = %16.16llx" 406 "\n\trip = %16.16llx" 407 "\n\tflg = %16.16llx cs = %16.16llx fs = %16.16llx gs = %16.16llx", 408 m_thread->ThreadID(), __x86_64_THREAD_STATE, e_regSetWordSizeGPR, 409 m_state.GetError(e_regSetGPR, Write), 410 m_state.context.gpr.__rax,m_state.context.gpr.__rbx,m_state.context.gpr.__rcx, 411 m_state.context.gpr.__rdx,m_state.context.gpr.__rdi,m_state.context.gpr.__rsi, 412 m_state.context.gpr.__rbp,m_state.context.gpr.__rsp,m_state.context.gpr.__r8, 413 m_state.context.gpr.__r9, m_state.context.gpr.__r10,m_state.context.gpr.__r11, 414 m_state.context.gpr.__r12,m_state.context.gpr.__r13,m_state.context.gpr.__r14, 415 m_state.context.gpr.__r15,m_state.context.gpr.__rip,m_state.context.gpr.__rflags, 416 m_state.context.gpr.__cs, m_state.context.gpr.__fs, m_state.context.gpr.__gs); 417 return m_state.GetError(e_regSetGPR, Write); 418} 419 420kern_return_t 421DNBArchImplX86_64::SetFPUState() 422{ 423 if (DEBUG_FPU_REGS) 424 { 425 m_state.SetError(e_regSetFPU, Write, 0); 426 return m_state.GetError(e_regSetFPU, Write); 427 } 428 else 429 { 430 if (CPUHasAVX() || FORCE_AVX_REGS) 431 { 432 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_AVX_STATE, (thread_state_t)&m_state.context.fpu.avx, e_regSetWordSizeAVX)); 433 return m_state.GetError(e_regSetFPU, Write); 434 } 435 else 436 { 437 m_state.SetError(e_regSetFPU, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_FLOAT_STATE, (thread_state_t)&m_state.context.fpu.no_avx, e_regSetWordSizeFPR)); 438 return m_state.GetError(e_regSetFPU, Write); 439 } 440 } 441} 442 443kern_return_t 444DNBArchImplX86_64::SetEXCState() 445{ 446 m_state.SetError(e_regSetEXC, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_EXCEPTION_STATE, (thread_state_t)&m_state.context.exc, e_regSetWordSizeEXC)); 447 return m_state.GetError(e_regSetEXC, Write); 448} 449 450kern_return_t 451DNBArchImplX86_64::GetDBGState(bool force) 452{ 453 if (force || m_state.GetError(e_regSetDBG, Read)) 454 { 455 mach_msg_type_number_t count = e_regSetWordSizeDBG; 456 m_state.SetError(e_regSetDBG, Read, ::thread_get_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, &count)); 457 } 458 return m_state.GetError(e_regSetDBG, Read); 459} 460 461kern_return_t 462DNBArchImplX86_64::SetDBGState() 463{ 464 m_state.SetError(e_regSetDBG, Write, ::thread_set_state(m_thread->ThreadID(), __x86_64_DEBUG_STATE, (thread_state_t)&m_state.context.dbg, e_regSetWordSizeDBG)); 465 return m_state.GetError(e_regSetDBG, Write); 466} 467 468void 469DNBArchImplX86_64::ThreadWillResume() 470{ 471 // Do we need to step this thread? If so, let the mach thread tell us so. 472 if (m_thread->IsStepping()) 473 { 474 // This is the primary thread, let the arch do anything it needs 475 EnableHardwareSingleStep(true); 476 } 477} 478 479bool 480DNBArchImplX86_64::ThreadDidStop() 481{ 482 bool success = true; 483 484 m_state.InvalidateAllRegisterStates(); 485 486 // Are we stepping a single instruction? 487 if (GetGPRState(true) == KERN_SUCCESS) 488 { 489 // We are single stepping, was this the primary thread? 490 if (m_thread->IsStepping()) 491 { 492 // This was the primary thread, we need to clear the trace 493 // bit if so. 494 success = EnableHardwareSingleStep(false) == KERN_SUCCESS; 495 } 496 else 497 { 498 // The MachThread will automatically restore the suspend count 499 // in ThreadDidStop(), so we don't need to do anything here if 500 // we weren't the primary thread the last time 501 } 502 } 503 return success; 504} 505 506bool 507DNBArchImplX86_64::NotifyException(MachException::Data& exc) 508{ 509 switch (exc.exc_type) 510 { 511 case EXC_BAD_ACCESS: 512 break; 513 case EXC_BAD_INSTRUCTION: 514 break; 515 case EXC_ARITHMETIC: 516 break; 517 case EXC_EMULATION: 518 break; 519 case EXC_SOFTWARE: 520 break; 521 case EXC_BREAKPOINT: 522 if (exc.exc_data.size() >= 2 && exc.exc_data[0] == 2) 523 { 524 nub_addr_t pc = GetPC(INVALID_NUB_ADDRESS); 525 if (pc != INVALID_NUB_ADDRESS && pc > 0) 526 { 527 pc -= 1; 528 // Check for a breakpoint at one byte prior to the current PC value 529 // since the PC will be just past the trap. 530 531 nub_break_t breakID = m_thread->Process()->Breakpoints().FindIDByAddress(pc); 532 if (NUB_BREAK_ID_IS_VALID(breakID)) 533 { 534 // Backup the PC for i386 since the trap was taken and the PC 535 // is at the address following the single byte trap instruction. 536 if (m_state.context.gpr.__rip > 0) 537 { 538 m_state.context.gpr.__rip = pc; 539 // Write the new PC back out 540 SetGPRState (); 541 } 542 } 543 return true; 544 } 545 } 546 break; 547 case EXC_SYSCALL: 548 break; 549 case EXC_MACH_SYSCALL: 550 break; 551 case EXC_RPC_ALERT: 552 break; 553 } 554 return false; 555} 556 557uint32_t 558DNBArchImplX86_64::NumSupportedHardwareWatchpoints() 559{ 560 // Available debug address registers: dr0, dr1, dr2, dr3. 561 return 4; 562} 563 564static uint32_t 565size_and_rw_bits(nub_size_t size, bool read, bool write) 566{ 567 uint32_t rw; 568 if (read) { 569 rw = 0x3; // READ or READ/WRITE 570 } else if (write) { 571 rw = 0x1; // WRITE 572 } else { 573 assert(0 && "read and write cannot both be false"); 574 } 575 576 switch (size) { 577 case 1: 578 return rw; 579 case 2: 580 return (0x1 << 2) | rw; 581 case 4: 582 return (0x3 << 2) | rw; 583 case 8: 584 return (0x2 << 2) | rw; 585 default: 586 assert(0 && "invalid size, must be one of 1, 2, 4, or 8"); 587 } 588} 589void 590DNBArchImplX86_64::SetWatchpoint(DBG &debug_state, uint32_t hw_index, nub_addr_t addr, nub_size_t size, bool read, bool write) 591{ 592 // Set both dr7 (debug control register) and dri (debug address register). 593 594 // dr7{7-0} encodes the local/gloabl enable bits: 595 // global enable --. .-- local enable 596 // | | 597 // v v 598 // dr0 -> bits{1-0} 599 // dr1 -> bits{3-2} 600 // dr2 -> bits{5-4} 601 // dr3 -> bits{7-6} 602 // 603 // dr7{31-16} encodes the rw/len bits: 604 // b_x+3, b_x+2, b_x+1, b_x 605 // where bits{x+1, x} => rw 606 // 0b00: execute, 0b01: write, 0b11: read-or-write, 0b10: io read-or-write (unused) 607 // and bits{x+3, x+2} => len 608 // 0b00: 1-byte, 0b01: 2-byte, 0b11: 4-byte, 0b10: 8-byte 609 // 610 // dr0 -> bits{19-16} 611 // dr1 -> bits{23-20} 612 // dr2 -> bits{27-24} 613 // dr3 -> bits{31-28} 614 debug_state.__dr7 |= (1 << (2*hw_index) | 615 size_and_rw_bits(size, read, write) << (16+4*hw_index)); 616 switch (hw_index) { 617 case 0: 618 debug_state.__dr0 == addr; break; 619 case 1: 620 debug_state.__dr1 == addr; break; 621 case 2: 622 debug_state.__dr2 == addr; break; 623 case 3: 624 debug_state.__dr3 == addr; break; 625 default: 626 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 627 } 628 return; 629} 630 631void 632DNBArchImplX86_64::ClearWatchpoint(DBG &debug_state, uint32_t hw_index) 633{ 634 debug_state.__dr7 &= ~(3 << (2*hw_index)); 635 switch (hw_index) { 636 case 0: 637 debug_state.__dr0 == 0; break; 638 case 1: 639 debug_state.__dr1 == 0; break; 640 case 2: 641 debug_state.__dr2 == 0; break; 642 case 3: 643 debug_state.__dr3 == 0; break; 644 default: 645 assert(0 && "invalid hardware register index, must be one of 0, 1, 2, or 3"); 646 } 647 return; 648} 649 650bool 651DNBArchImplX86_64::IsWatchpointVacant(const DBG &debug_state, uint32_t hw_index) 652{ 653 // Check dr7 (debug control register) for local/global enable bits: 654 // global enable --. .-- local enable 655 // | | 656 // v v 657 // dr0 -> bits{1-0} 658 // dr1 -> bits{3-2} 659 // dr2 -> bits{5-4} 660 // dr3 -> bits{7-6} 661 return (debug_state.__dr7 & (3 << (2*hw_index))) == 0; 662} 663 664// Resets local copy of debug status register to wait for the next debug excpetion. 665void 666DNBArchImplX86_64::ClearWatchpointHits(DBG &debug_state) 667{ 668 // See also IsWatchpointHit(). 669 debug_state.__dr6 = 0; 670 return; 671} 672 673bool 674DNBArchImplX86_64::IsWatchpointHit(const DBG &debug_state, uint32_t hw_index) 675{ 676 // Check dr6 (debug status register) whether a watchpoint hits: 677 // is watchpoint hit? 678 // | 679 // v 680 // dr0 -> bits{0} 681 // dr1 -> bits{1} 682 // dr2 -> bits{2} 683 // dr3 -> bits{3} 684 return (debug_state.__dr6 & (1 << hw_index)); 685} 686 687uint32_t 688DNBArchImplX86_64::EnableHardwareWatchpoint (nub_addr_t addr, nub_size_t size, bool read, bool write) 689{ 690 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write); 691 692 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints(); 693 694 // Can only watch 1, 2, 4, or 8 bytes. 695 if (!(size == 1 || size == 2 || size == 4 || size == 8)) 696 return INVALID_NUB_HW_INDEX; 697 698 // We must watch for either read or write 699 if (read == false && write == false) 700 return INVALID_NUB_HW_INDEX; 701 702 // Read the debug state 703 kern_return_t kret = GetDBGState(false); 704 705 if (kret == KERN_SUCCESS) 706 { 707 // Check to make sure we have the needed hardware support 708 uint32_t i = 0; 709 710 DBG debug_state = m_state.context.dbg; 711 for (i = 0; i < num_hw_watchpoints; ++i) 712 { 713 if (IsWatchpointVacant(debug_state, i)) 714 break; 715 } 716 717 // See if we found an available hw breakpoint slot above 718 if (i < num_hw_watchpoints) 719 { 720 // Modify our local copy of the debug state, first. 721 SetWatchpoint(debug_state, i, addr, size, read, write); 722 // Now set the watch point in the inferior. 723 kret = SetDBGState(); 724 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint() SetDBGState() => 0x%8.8x.", kret); 725 726 if (kret == KERN_SUCCESS) 727 return i; 728 } 729 else 730 { 731 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints); 732 } 733 } 734 return INVALID_NUB_HW_INDEX; 735} 736 737bool 738DNBArchImplX86_64::DisableHardwareWatchpoint (uint32_t hw_index) 739{ 740 kern_return_t kret = GetDBGState(false); 741 742 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints(); 743 if (kret == KERN_SUCCESS) 744 { 745 DBG debug_state = m_state.context.dbg; 746 if (hw_index < num_hw_points && !IsWatchpointVacant(debug_state, hw_index)) 747 { 748 // Modify our local copy of the debug state, first. 749 ClearWatchpoint(debug_state, hw_index); 750 // Now disable the watch point in the inferior. 751 kret = SetDBGState(); 752 DNBLogThreadedIf(LOG_WATCHPOINTS, "DNBArchImplX86_64::DisableHardwareWatchpoint( %u )", 753 hw_index); 754 755 if (kret == KERN_SUCCESS) 756 return true; 757 } 758 } 759 return false; 760} 761 762// Set the single step bit in the processor status register. 763kern_return_t 764DNBArchImplX86_64::EnableHardwareSingleStep (bool enable) 765{ 766 if (GetGPRState(false) == KERN_SUCCESS) 767 { 768 const uint32_t trace_bit = 0x100u; 769 if (enable) 770 m_state.context.gpr.__rflags |= trace_bit; 771 else 772 m_state.context.gpr.__rflags &= ~trace_bit; 773 return SetGPRState(); 774 } 775 return m_state.GetError(e_regSetGPR, Read); 776} 777 778 779//---------------------------------------------------------------------- 780// Register information defintions 781//---------------------------------------------------------------------- 782 783enum 784{ 785 gpr_rax = 0, 786 gpr_rbx, 787 gpr_rcx, 788 gpr_rdx, 789 gpr_rdi, 790 gpr_rsi, 791 gpr_rbp, 792 gpr_rsp, 793 gpr_r8, 794 gpr_r9, 795 gpr_r10, 796 gpr_r11, 797 gpr_r12, 798 gpr_r13, 799 gpr_r14, 800 gpr_r15, 801 gpr_rip, 802 gpr_rflags, 803 gpr_cs, 804 gpr_fs, 805 gpr_gs, 806 k_num_gpr_regs 807}; 808 809enum { 810 fpu_fcw, 811 fpu_fsw, 812 fpu_ftw, 813 fpu_fop, 814 fpu_ip, 815 fpu_cs, 816 fpu_dp, 817 fpu_ds, 818 fpu_mxcsr, 819 fpu_mxcsrmask, 820 fpu_stmm0, 821 fpu_stmm1, 822 fpu_stmm2, 823 fpu_stmm3, 824 fpu_stmm4, 825 fpu_stmm5, 826 fpu_stmm6, 827 fpu_stmm7, 828 fpu_xmm0, 829 fpu_xmm1, 830 fpu_xmm2, 831 fpu_xmm3, 832 fpu_xmm4, 833 fpu_xmm5, 834 fpu_xmm6, 835 fpu_xmm7, 836 fpu_xmm8, 837 fpu_xmm9, 838 fpu_xmm10, 839 fpu_xmm11, 840 fpu_xmm12, 841 fpu_xmm13, 842 fpu_xmm14, 843 fpu_xmm15, 844 fpu_ymm0, 845 fpu_ymm1, 846 fpu_ymm2, 847 fpu_ymm3, 848 fpu_ymm4, 849 fpu_ymm5, 850 fpu_ymm6, 851 fpu_ymm7, 852 fpu_ymm8, 853 fpu_ymm9, 854 fpu_ymm10, 855 fpu_ymm11, 856 fpu_ymm12, 857 fpu_ymm13, 858 fpu_ymm14, 859 fpu_ymm15, 860 k_num_fpu_regs, 861 862 // Aliases 863 fpu_fctrl = fpu_fcw, 864 fpu_fstat = fpu_fsw, 865 fpu_ftag = fpu_ftw, 866 fpu_fiseg = fpu_cs, 867 fpu_fioff = fpu_ip, 868 fpu_foseg = fpu_ds, 869 fpu_fooff = fpu_dp 870}; 871 872enum { 873 exc_trapno, 874 exc_err, 875 exc_faultvaddr, 876 k_num_exc_regs, 877}; 878 879 880enum gcc_dwarf_regnums 881{ 882 gcc_dwarf_rax = 0, 883 gcc_dwarf_rdx = 1, 884 gcc_dwarf_rcx = 2, 885 gcc_dwarf_rbx = 3, 886 gcc_dwarf_rsi = 4, 887 gcc_dwarf_rdi = 5, 888 gcc_dwarf_rbp = 6, 889 gcc_dwarf_rsp = 7, 890 gcc_dwarf_r8, 891 gcc_dwarf_r9, 892 gcc_dwarf_r10, 893 gcc_dwarf_r11, 894 gcc_dwarf_r12, 895 gcc_dwarf_r13, 896 gcc_dwarf_r14, 897 gcc_dwarf_r15, 898 gcc_dwarf_rip, 899 gcc_dwarf_xmm0, 900 gcc_dwarf_xmm1, 901 gcc_dwarf_xmm2, 902 gcc_dwarf_xmm3, 903 gcc_dwarf_xmm4, 904 gcc_dwarf_xmm5, 905 gcc_dwarf_xmm6, 906 gcc_dwarf_xmm7, 907 gcc_dwarf_xmm8, 908 gcc_dwarf_xmm9, 909 gcc_dwarf_xmm10, 910 gcc_dwarf_xmm11, 911 gcc_dwarf_xmm12, 912 gcc_dwarf_xmm13, 913 gcc_dwarf_xmm14, 914 gcc_dwarf_xmm15, 915 gcc_dwarf_stmm0, 916 gcc_dwarf_stmm1, 917 gcc_dwarf_stmm2, 918 gcc_dwarf_stmm3, 919 gcc_dwarf_stmm4, 920 gcc_dwarf_stmm5, 921 gcc_dwarf_stmm6, 922 gcc_dwarf_stmm7, 923 gcc_dwarf_ymm0 = gcc_dwarf_xmm0, 924 gcc_dwarf_ymm1 = gcc_dwarf_xmm1, 925 gcc_dwarf_ymm2 = gcc_dwarf_xmm2, 926 gcc_dwarf_ymm3 = gcc_dwarf_xmm3, 927 gcc_dwarf_ymm4 = gcc_dwarf_xmm4, 928 gcc_dwarf_ymm5 = gcc_dwarf_xmm5, 929 gcc_dwarf_ymm6 = gcc_dwarf_xmm6, 930 gcc_dwarf_ymm7 = gcc_dwarf_xmm7, 931 gcc_dwarf_ymm8 = gcc_dwarf_xmm8, 932 gcc_dwarf_ymm9 = gcc_dwarf_xmm9, 933 gcc_dwarf_ymm10 = gcc_dwarf_xmm10, 934 gcc_dwarf_ymm11 = gcc_dwarf_xmm11, 935 gcc_dwarf_ymm12 = gcc_dwarf_xmm12, 936 gcc_dwarf_ymm13 = gcc_dwarf_xmm13, 937 gcc_dwarf_ymm14 = gcc_dwarf_xmm14, 938 gcc_dwarf_ymm15 = gcc_dwarf_xmm15 939}; 940 941enum gdb_regnums 942{ 943 gdb_rax = 0, 944 gdb_rbx = 1, 945 gdb_rcx = 2, 946 gdb_rdx = 3, 947 gdb_rsi = 4, 948 gdb_rdi = 5, 949 gdb_rbp = 6, 950 gdb_rsp = 7, 951 gdb_r8 = 8, 952 gdb_r9 = 9, 953 gdb_r10 = 10, 954 gdb_r11 = 11, 955 gdb_r12 = 12, 956 gdb_r13 = 13, 957 gdb_r14 = 14, 958 gdb_r15 = 15, 959 gdb_rip = 16, 960 gdb_rflags = 17, 961 gdb_cs = 18, 962 gdb_ss = 19, 963 gdb_ds = 20, 964 gdb_es = 21, 965 gdb_fs = 22, 966 gdb_gs = 23, 967 gdb_stmm0 = 24, 968 gdb_stmm1 = 25, 969 gdb_stmm2 = 26, 970 gdb_stmm3 = 27, 971 gdb_stmm4 = 28, 972 gdb_stmm5 = 29, 973 gdb_stmm6 = 30, 974 gdb_stmm7 = 31, 975 gdb_fctrl = 32, gdb_fcw = gdb_fctrl, 976 gdb_fstat = 33, gdb_fsw = gdb_fstat, 977 gdb_ftag = 34, gdb_ftw = gdb_ftag, 978 gdb_fiseg = 35, gdb_fpu_cs = gdb_fiseg, 979 gdb_fioff = 36, gdb_ip = gdb_fioff, 980 gdb_foseg = 37, gdb_fpu_ds = gdb_foseg, 981 gdb_fooff = 38, gdb_dp = gdb_fooff, 982 gdb_fop = 39, 983 gdb_xmm0 = 40, 984 gdb_xmm1 = 41, 985 gdb_xmm2 = 42, 986 gdb_xmm3 = 43, 987 gdb_xmm4 = 44, 988 gdb_xmm5 = 45, 989 gdb_xmm6 = 46, 990 gdb_xmm7 = 47, 991 gdb_xmm8 = 48, 992 gdb_xmm9 = 49, 993 gdb_xmm10 = 50, 994 gdb_xmm11 = 51, 995 gdb_xmm12 = 52, 996 gdb_xmm13 = 53, 997 gdb_xmm14 = 54, 998 gdb_xmm15 = 55, 999 gdb_mxcsr = 56, 1000 gdb_ymm0 = gdb_xmm0, 1001 gdb_ymm1 = gdb_xmm1, 1002 gdb_ymm2 = gdb_xmm2, 1003 gdb_ymm3 = gdb_xmm3, 1004 gdb_ymm4 = gdb_xmm4, 1005 gdb_ymm5 = gdb_xmm5, 1006 gdb_ymm6 = gdb_xmm6, 1007 gdb_ymm7 = gdb_xmm7, 1008 gdb_ymm8 = gdb_xmm8, 1009 gdb_ymm9 = gdb_xmm9, 1010 gdb_ymm10 = gdb_xmm10, 1011 gdb_ymm11 = gdb_xmm11, 1012 gdb_ymm12 = gdb_xmm12, 1013 gdb_ymm13 = gdb_xmm13, 1014 gdb_ymm14 = gdb_xmm14, 1015 gdb_ymm15 = gdb_xmm15 1016}; 1017 1018#define GPR_OFFSET(reg) (offsetof (DNBArchImplX86_64::GPR, __##reg)) 1019#define FPU_OFFSET(reg) (offsetof (DNBArchImplX86_64::FPU, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.no_avx)) 1020#define AVX_OFFSET(reg) (offsetof (DNBArchImplX86_64::AVX, __fpu_##reg) + offsetof (DNBArchImplX86_64::Context, fpu.avx)) 1021#define EXC_OFFSET(reg) (offsetof (DNBArchImplX86_64::EXC, __##reg) + offsetof (DNBArchImplX86_64::Context, exc)) 1022 1023// This does not accurately identify the location of ymm0...7 in 1024// Context.fpu.avx. That is because there is a bunch of padding 1025// in Context.fpu.avx that we don't need. Offset macros lay out 1026// the register state that Debugserver transmits to the debugger 1027// -- not to interpret the thread_get_state info. 1028#define AVX_OFFSET_YMM(n) (AVX_OFFSET(xmm7) + FPU_SIZE_XMM(xmm7) + (32 * n)) 1029 1030#define GPR_SIZE(reg) (sizeof(((DNBArchImplX86_64::GPR *)NULL)->__##reg)) 1031#define FPU_SIZE_UINT(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg)) 1032#define FPU_SIZE_MMST(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__mmst_reg)) 1033#define FPU_SIZE_XMM(reg) (sizeof(((DNBArchImplX86_64::FPU *)NULL)->__fpu_##reg.__xmm_reg)) 1034#define FPU_SIZE_YMM(reg) (32) 1035#define EXC_SIZE(reg) (sizeof(((DNBArchImplX86_64::EXC *)NULL)->__##reg)) 1036 1037// These macros will auto define the register name, alt name, register size, 1038// register offset, encoding, format and native register. This ensures that 1039// the register state structures are defined correctly and have the correct 1040// sizes and offsets. 1041#define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg } 1042#define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg } 1043#define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg } 1044#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg } 1045 1046// General purpose registers for 64 bit 1047const DNBRegisterInfo 1048DNBArchImplX86_64::g_gpr_registers[] = 1049{ 1050 DEFINE_GPR (rax), 1051 DEFINE_GPR (rbx), 1052 DEFINE_GPR_ALT (rcx , "arg4", GENERIC_REGNUM_ARG4), 1053 DEFINE_GPR_ALT (rdx , "arg3", GENERIC_REGNUM_ARG3), 1054 DEFINE_GPR_ALT (rdi , "arg1", GENERIC_REGNUM_ARG1), 1055 DEFINE_GPR_ALT (rsi , "arg2", GENERIC_REGNUM_ARG2), 1056 DEFINE_GPR_ALT (rbp , "fp" , GENERIC_REGNUM_FP), 1057 DEFINE_GPR_ALT (rsp , "sp" , GENERIC_REGNUM_SP), 1058 DEFINE_GPR_ALT (r8 , "arg5", GENERIC_REGNUM_ARG5), 1059 DEFINE_GPR_ALT (r9 , "arg6", GENERIC_REGNUM_ARG6), 1060 DEFINE_GPR (r10), 1061 DEFINE_GPR (r11), 1062 DEFINE_GPR (r12), 1063 DEFINE_GPR (r13), 1064 DEFINE_GPR (r14), 1065 DEFINE_GPR (r15), 1066 DEFINE_GPR_ALT (rip , "pc", GENERIC_REGNUM_PC), 1067 DEFINE_GPR_ALT3 (rflags, "flags", GENERIC_REGNUM_FLAGS), 1068 DEFINE_GPR_ALT2 (cs, NULL), 1069 DEFINE_GPR_ALT2 (fs, NULL), 1070 DEFINE_GPR_ALT2 (gs, NULL), 1071}; 1072 1073// Floating point registers 64 bit 1074const DNBRegisterInfo 1075DNBArchImplX86_64::g_fpu_registers_no_avx[] = 1076{ 1077 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1, -1, -1, -1 }, 1078 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1, -1, -1, -1 }, 1079 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1, -1, -1, -1 }, 1080 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1, -1, -1, -1 }, 1081 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1, -1, -1, -1 }, 1082 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1, -1, -1, -1 }, 1083 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1, -1, -1, -1 }, 1084 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1, -1, -1, -1 }, 1085 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1, -1, -1, -1 }, 1086 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 1087 1088 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 1089 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1090 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1091 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1092 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1093 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 1094 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1095 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 1096 1097 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 1098 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 1099 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 1100 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 1101 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 1102 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 1103 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 1104 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 1105 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 1106 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 1107 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 1108 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1109 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1110 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 1111 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1112 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 1113}; 1114 1115const DNBRegisterInfo 1116DNBArchImplX86_64::g_fpu_registers_avx[] = 1117{ 1118 { e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1, -1, -1, -1 }, 1119 { e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1, -1, -1, -1 }, 1120 { e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1, -1, -1, -1 }, 1121 { e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1, -1, -1, -1 }, 1122 { e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1, -1, -1, -1 }, 1123 { e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1, -1, -1, -1 }, 1124 { e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1, -1, -1, -1 }, 1125 { e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1, -1, -1, -1 }, 1126 { e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1, -1, -1, -1 }, 1127 { e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1, -1, -1, -1 }, 1128 1129 { e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1, gdb_stmm0 }, 1130 { e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1, gdb_stmm1 }, 1131 { e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1, gdb_stmm2 }, 1132 { e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1, gdb_stmm3 }, 1133 { e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1, gdb_stmm4 }, 1134 { e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1, gdb_stmm5 }, 1135 { e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1, gdb_stmm6 }, 1136 { e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1, gdb_stmm7 }, 1137 1138 { e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1, gdb_xmm0 }, 1139 { e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1, gdb_xmm1 }, 1140 { e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1, gdb_xmm2 }, 1141 { e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1, gdb_xmm3 }, 1142 { e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1, gdb_xmm4 }, 1143 { e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1, gdb_xmm5 }, 1144 { e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1, gdb_xmm6 }, 1145 { e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1, gdb_xmm7 }, 1146 { e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1, gdb_xmm8 }, 1147 { e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1, gdb_xmm9 }, 1148 { e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1, gdb_xmm10 }, 1149 { e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1, gdb_xmm11 }, 1150 { e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1, gdb_xmm12 }, 1151 { e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1, gdb_xmm13 }, 1152 { e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1, gdb_xmm14 }, 1153 { e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1, gdb_xmm15 }, 1154 1155 { e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1, gdb_ymm0 }, 1156 { e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1, gdb_ymm1 }, 1157 { e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1, gdb_ymm2 }, 1158 { e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1, gdb_ymm3 }, 1159 { e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1, gdb_ymm4 }, 1160 { e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1, gdb_ymm5 }, 1161 { e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1, gdb_ymm6 }, 1162 { e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1, gdb_ymm7 }, 1163 { e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1, gdb_ymm8 }, 1164 { e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1, gdb_ymm9 }, 1165 { e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1, gdb_ymm10 }, 1166 { e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1, gdb_ymm11 }, 1167 { e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1, gdb_ymm12 }, 1168 { e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1, gdb_ymm13 }, 1169 { e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1, gdb_ymm14 }, 1170 { e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1, gdb_ymm15 } 1171}; 1172 1173// Exception registers 1174 1175const DNBRegisterInfo 1176DNBArchImplX86_64::g_exc_registers[] = 1177{ 1178 { e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1, -1, -1, -1 }, 1179 { e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1, -1, -1, -1 }, 1180 { e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1, -1, -1, -1 } 1181}; 1182 1183// Number of registers in each register set 1184const size_t DNBArchImplX86_64::k_num_gpr_registers = sizeof(g_gpr_registers)/sizeof(DNBRegisterInfo); 1185const size_t DNBArchImplX86_64::k_num_fpu_registers_no_avx = sizeof(g_fpu_registers_no_avx)/sizeof(DNBRegisterInfo); 1186const size_t DNBArchImplX86_64::k_num_fpu_registers_avx = sizeof(g_fpu_registers_avx)/sizeof(DNBRegisterInfo); 1187const size_t DNBArchImplX86_64::k_num_exc_registers = sizeof(g_exc_registers)/sizeof(DNBRegisterInfo); 1188const size_t DNBArchImplX86_64::k_num_all_registers_no_avx = k_num_gpr_registers + k_num_fpu_registers_no_avx + k_num_exc_registers; 1189const size_t DNBArchImplX86_64::k_num_all_registers_avx = k_num_gpr_registers + k_num_fpu_registers_avx + k_num_exc_registers; 1190 1191//---------------------------------------------------------------------- 1192// Register set definitions. The first definitions at register set index 1193// of zero is for all registers, followed by other registers sets. The 1194// register information for the all register set need not be filled in. 1195//---------------------------------------------------------------------- 1196const DNBRegisterSetInfo 1197DNBArchImplX86_64::g_reg_sets_no_avx[] = 1198{ 1199 { "x86_64 Registers", NULL, k_num_all_registers_no_avx }, 1200 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1201 { "Floating Point Registers", g_fpu_registers_no_avx, k_num_fpu_registers_no_avx }, 1202 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1203}; 1204 1205const DNBRegisterSetInfo 1206DNBArchImplX86_64::g_reg_sets_avx[] = 1207{ 1208 { "x86_64 Registers", NULL, k_num_all_registers_avx }, 1209 { "General Purpose Registers", g_gpr_registers, k_num_gpr_registers }, 1210 { "Floating Point Registers", g_fpu_registers_avx, k_num_fpu_registers_avx }, 1211 { "Exception State Registers", g_exc_registers, k_num_exc_registers } 1212}; 1213 1214// Total number of register sets for this architecture 1215const size_t DNBArchImplX86_64::k_num_register_sets = sizeof(g_reg_sets_avx)/sizeof(DNBRegisterSetInfo); 1216 1217 1218DNBArchProtocol * 1219DNBArchImplX86_64::Create (MachThread *thread) 1220{ 1221 return new DNBArchImplX86_64 (thread); 1222} 1223 1224const uint8_t * const 1225DNBArchImplX86_64::SoftwareBreakpointOpcode (nub_size_t byte_size) 1226{ 1227 static const uint8_t g_breakpoint_opcode[] = { 0xCC }; 1228 if (byte_size == 1) 1229 return g_breakpoint_opcode; 1230 return NULL; 1231} 1232 1233const DNBRegisterSetInfo * 1234DNBArchImplX86_64::GetRegisterSetInfo(nub_size_t *num_reg_sets) 1235{ 1236 *num_reg_sets = k_num_register_sets; 1237 1238 if (CPUHasAVX() || FORCE_AVX_REGS) 1239 return g_reg_sets_avx; 1240 else 1241 return g_reg_sets_no_avx; 1242} 1243 1244void 1245DNBArchImplX86_64::Initialize() 1246{ 1247 DNBArchPluginInfo arch_plugin_info = 1248 { 1249 CPU_TYPE_X86_64, 1250 DNBArchImplX86_64::Create, 1251 DNBArchImplX86_64::GetRegisterSetInfo, 1252 DNBArchImplX86_64::SoftwareBreakpointOpcode 1253 }; 1254 1255 // Register this arch plug-in with the main protocol class 1256 DNBArchProtocol::RegisterArchPlugin (arch_plugin_info); 1257} 1258 1259bool 1260DNBArchImplX86_64::GetRegisterValue(int set, int reg, DNBRegisterValue *value) 1261{ 1262 if (set == REGISTER_SET_GENERIC) 1263 { 1264 switch (reg) 1265 { 1266 case GENERIC_REGNUM_PC: // Program Counter 1267 set = e_regSetGPR; 1268 reg = gpr_rip; 1269 break; 1270 1271 case GENERIC_REGNUM_SP: // Stack Pointer 1272 set = e_regSetGPR; 1273 reg = gpr_rsp; 1274 break; 1275 1276 case GENERIC_REGNUM_FP: // Frame Pointer 1277 set = e_regSetGPR; 1278 reg = gpr_rbp; 1279 break; 1280 1281 case GENERIC_REGNUM_FLAGS: // Processor flags register 1282 set = e_regSetGPR; 1283 reg = gpr_rflags; 1284 break; 1285 1286 case GENERIC_REGNUM_RA: // Return Address 1287 default: 1288 return false; 1289 } 1290 } 1291 1292 if (GetRegisterState(set, false) != KERN_SUCCESS) 1293 return false; 1294 1295 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1296 if (regInfo) 1297 { 1298 value->info = *regInfo; 1299 switch (set) 1300 { 1301 case e_regSetGPR: 1302 if (reg < k_num_gpr_registers) 1303 { 1304 value->value.uint64 = ((uint64_t*)(&m_state.context.gpr))[reg]; 1305 return true; 1306 } 1307 break; 1308 1309 case e_regSetFPU: 1310 if (CPUHasAVX() || FORCE_AVX_REGS) 1311 { 1312 switch (reg) 1313 { 1314 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)); return true; 1315 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)); return true; 1316 case fpu_ftw: value->value.uint8 = m_state.context.fpu.avx.__fpu_ftw; return true; 1317 case fpu_fop: value->value.uint16 = m_state.context.fpu.avx.__fpu_fop; return true; 1318 case fpu_ip: value->value.uint32 = m_state.context.fpu.avx.__fpu_ip; return true; 1319 case fpu_cs: value->value.uint16 = m_state.context.fpu.avx.__fpu_cs; return true; 1320 case fpu_dp: value->value.uint32 = m_state.context.fpu.avx.__fpu_dp; return true; 1321 case fpu_ds: value->value.uint16 = m_state.context.fpu.avx.__fpu_ds; return true; 1322 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsr; return true; 1323 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.avx.__fpu_mxcsrmask; return true; 1324 1325 case fpu_stmm0: 1326 case fpu_stmm1: 1327 case fpu_stmm2: 1328 case fpu_stmm3: 1329 case fpu_stmm4: 1330 case fpu_stmm5: 1331 case fpu_stmm6: 1332 case fpu_stmm7: 1333 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1334 return true; 1335 1336 case fpu_xmm0: 1337 case fpu_xmm1: 1338 case fpu_xmm2: 1339 case fpu_xmm3: 1340 case fpu_xmm4: 1341 case fpu_xmm5: 1342 case fpu_xmm6: 1343 case fpu_xmm7: 1344 case fpu_xmm8: 1345 case fpu_xmm9: 1346 case fpu_xmm10: 1347 case fpu_xmm11: 1348 case fpu_xmm12: 1349 case fpu_xmm13: 1350 case fpu_xmm14: 1351 case fpu_xmm15: 1352 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1353 return true; 1354 1355 case fpu_ymm0: 1356 case fpu_ymm1: 1357 case fpu_ymm2: 1358 case fpu_ymm3: 1359 case fpu_ymm4: 1360 case fpu_ymm5: 1361 case fpu_ymm6: 1362 case fpu_ymm7: 1363 case fpu_ymm8: 1364 case fpu_ymm9: 1365 case fpu_ymm10: 1366 case fpu_ymm11: 1367 case fpu_ymm12: 1368 case fpu_ymm13: 1369 case fpu_ymm14: 1370 case fpu_ymm15: 1371 memcpy(&value->value.uint8, &m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), 16); 1372 memcpy((&value->value.uint8) + 16, &m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), 16); 1373 return true; 1374 } 1375 } 1376 else 1377 { 1378 switch (reg) 1379 { 1380 case fpu_fcw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)); return true; 1381 case fpu_fsw: value->value.uint16 = *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)); return true; 1382 case fpu_ftw: value->value.uint8 = m_state.context.fpu.no_avx.__fpu_ftw; return true; 1383 case fpu_fop: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_fop; return true; 1384 case fpu_ip: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_ip; return true; 1385 case fpu_cs: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_cs; return true; 1386 case fpu_dp: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_dp; return true; 1387 case fpu_ds: value->value.uint16 = m_state.context.fpu.no_avx.__fpu_ds; return true; 1388 case fpu_mxcsr: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsr; return true; 1389 case fpu_mxcsrmask: value->value.uint32 = m_state.context.fpu.no_avx.__fpu_mxcsrmask; return true; 1390 1391 case fpu_stmm0: 1392 case fpu_stmm1: 1393 case fpu_stmm2: 1394 case fpu_stmm3: 1395 case fpu_stmm4: 1396 case fpu_stmm5: 1397 case fpu_stmm6: 1398 case fpu_stmm7: 1399 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), 10); 1400 return true; 1401 1402 case fpu_xmm0: 1403 case fpu_xmm1: 1404 case fpu_xmm2: 1405 case fpu_xmm3: 1406 case fpu_xmm4: 1407 case fpu_xmm5: 1408 case fpu_xmm6: 1409 case fpu_xmm7: 1410 case fpu_xmm8: 1411 case fpu_xmm9: 1412 case fpu_xmm10: 1413 case fpu_xmm11: 1414 case fpu_xmm12: 1415 case fpu_xmm13: 1416 case fpu_xmm14: 1417 case fpu_xmm15: 1418 memcpy(&value->value.uint8, &m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), 16); 1419 return true; 1420 } 1421 } 1422 break; 1423 1424 case e_regSetEXC: 1425 switch (reg) 1426 { 1427 case exc_trapno: value->value.uint32 = m_state.context.exc.__trapno; return true; 1428 case exc_err: value->value.uint32 = m_state.context.exc.__err; return true; 1429 case exc_faultvaddr:value->value.uint64 = m_state.context.exc.__faultvaddr; return true; 1430 } 1431 break; 1432 } 1433 } 1434 return false; 1435} 1436 1437 1438bool 1439DNBArchImplX86_64::SetRegisterValue(int set, int reg, const DNBRegisterValue *value) 1440{ 1441 if (set == REGISTER_SET_GENERIC) 1442 { 1443 switch (reg) 1444 { 1445 case GENERIC_REGNUM_PC: // Program Counter 1446 set = e_regSetGPR; 1447 reg = gpr_rip; 1448 break; 1449 1450 case GENERIC_REGNUM_SP: // Stack Pointer 1451 set = e_regSetGPR; 1452 reg = gpr_rsp; 1453 break; 1454 1455 case GENERIC_REGNUM_FP: // Frame Pointer 1456 set = e_regSetGPR; 1457 reg = gpr_rbp; 1458 break; 1459 1460 case GENERIC_REGNUM_FLAGS: // Processor flags register 1461 set = e_regSetGPR; 1462 reg = gpr_rflags; 1463 break; 1464 1465 case GENERIC_REGNUM_RA: // Return Address 1466 default: 1467 return false; 1468 } 1469 } 1470 1471 if (GetRegisterState(set, false) != KERN_SUCCESS) 1472 return false; 1473 1474 bool success = false; 1475 const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg); 1476 if (regInfo) 1477 { 1478 switch (set) 1479 { 1480 case e_regSetGPR: 1481 if (reg < k_num_gpr_registers) 1482 { 1483 ((uint64_t*)(&m_state.context.gpr))[reg] = value->value.uint64; 1484 success = true; 1485 } 1486 break; 1487 1488 case e_regSetFPU: 1489 if (CPUHasAVX() || FORCE_AVX_REGS) 1490 { 1491 switch (reg) 1492 { 1493 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1494 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1495 case fpu_ftw: m_state.context.fpu.avx.__fpu_ftw = value->value.uint8; success = true; break; 1496 case fpu_fop: m_state.context.fpu.avx.__fpu_fop = value->value.uint16; success = true; break; 1497 case fpu_ip: m_state.context.fpu.avx.__fpu_ip = value->value.uint32; success = true; break; 1498 case fpu_cs: m_state.context.fpu.avx.__fpu_cs = value->value.uint16; success = true; break; 1499 case fpu_dp: m_state.context.fpu.avx.__fpu_dp = value->value.uint32; success = true; break; 1500 case fpu_ds: m_state.context.fpu.avx.__fpu_ds = value->value.uint16; success = true; break; 1501 case fpu_mxcsr: m_state.context.fpu.avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1502 case fpu_mxcsrmask: m_state.context.fpu.avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1503 1504 case fpu_stmm0: 1505 case fpu_stmm1: 1506 case fpu_stmm2: 1507 case fpu_stmm3: 1508 case fpu_stmm4: 1509 case fpu_stmm5: 1510 case fpu_stmm6: 1511 case fpu_stmm7: 1512 memcpy (&m_state.context.fpu.avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1513 success = true; 1514 break; 1515 1516 case fpu_xmm0: 1517 case fpu_xmm1: 1518 case fpu_xmm2: 1519 case fpu_xmm3: 1520 case fpu_xmm4: 1521 case fpu_xmm5: 1522 case fpu_xmm6: 1523 case fpu_xmm7: 1524 case fpu_xmm8: 1525 case fpu_xmm9: 1526 case fpu_xmm10: 1527 case fpu_xmm11: 1528 case fpu_xmm12: 1529 case fpu_xmm13: 1530 case fpu_xmm14: 1531 case fpu_xmm15: 1532 memcpy (&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1533 success = true; 1534 break; 1535 1536 case fpu_ymm0: 1537 case fpu_ymm1: 1538 case fpu_ymm2: 1539 case fpu_ymm3: 1540 case fpu_ymm4: 1541 case fpu_ymm5: 1542 case fpu_ymm6: 1543 case fpu_ymm7: 1544 case fpu_ymm8: 1545 case fpu_ymm9: 1546 case fpu_ymm10: 1547 case fpu_ymm11: 1548 case fpu_ymm12: 1549 case fpu_ymm13: 1550 case fpu_ymm14: 1551 case fpu_ymm15: 1552 memcpy(&m_state.context.fpu.avx.__fpu_xmm0 + (reg - fpu_ymm0), &value->value.uint8, 16); 1553 memcpy(&m_state.context.fpu.avx.__fpu_ymmh0 + (reg - fpu_ymm0), (&value->value.uint8) + 16, 16); 1554 return true; 1555 } 1556 } 1557 else 1558 { 1559 switch (reg) 1560 { 1561 case fpu_fcw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fcw)) = value->value.uint16; success = true; break; 1562 case fpu_fsw: *((uint16_t *)(&m_state.context.fpu.no_avx.__fpu_fsw)) = value->value.uint16; success = true; break; 1563 case fpu_ftw: m_state.context.fpu.no_avx.__fpu_ftw = value->value.uint8; success = true; break; 1564 case fpu_fop: m_state.context.fpu.no_avx.__fpu_fop = value->value.uint16; success = true; break; 1565 case fpu_ip: m_state.context.fpu.no_avx.__fpu_ip = value->value.uint32; success = true; break; 1566 case fpu_cs: m_state.context.fpu.no_avx.__fpu_cs = value->value.uint16; success = true; break; 1567 case fpu_dp: m_state.context.fpu.no_avx.__fpu_dp = value->value.uint32; success = true; break; 1568 case fpu_ds: m_state.context.fpu.no_avx.__fpu_ds = value->value.uint16; success = true; break; 1569 case fpu_mxcsr: m_state.context.fpu.no_avx.__fpu_mxcsr = value->value.uint32; success = true; break; 1570 case fpu_mxcsrmask: m_state.context.fpu.no_avx.__fpu_mxcsrmask = value->value.uint32; success = true; break; 1571 1572 case fpu_stmm0: 1573 case fpu_stmm1: 1574 case fpu_stmm2: 1575 case fpu_stmm3: 1576 case fpu_stmm4: 1577 case fpu_stmm5: 1578 case fpu_stmm6: 1579 case fpu_stmm7: 1580 memcpy (&m_state.context.fpu.no_avx.__fpu_stmm0 + (reg - fpu_stmm0), &value->value.uint8, 10); 1581 success = true; 1582 break; 1583 1584 case fpu_xmm0: 1585 case fpu_xmm1: 1586 case fpu_xmm2: 1587 case fpu_xmm3: 1588 case fpu_xmm4: 1589 case fpu_xmm5: 1590 case fpu_xmm6: 1591 case fpu_xmm7: 1592 case fpu_xmm8: 1593 case fpu_xmm9: 1594 case fpu_xmm10: 1595 case fpu_xmm11: 1596 case fpu_xmm12: 1597 case fpu_xmm13: 1598 case fpu_xmm14: 1599 case fpu_xmm15: 1600 memcpy (&m_state.context.fpu.no_avx.__fpu_xmm0 + (reg - fpu_xmm0), &value->value.uint8, 16); 1601 success = true; 1602 break; 1603 } 1604 } 1605 break; 1606 1607 case e_regSetEXC: 1608 switch (reg) 1609 { 1610 case exc_trapno: m_state.context.exc.__trapno = value->value.uint32; success = true; break; 1611 case exc_err: m_state.context.exc.__err = value->value.uint32; success = true; break; 1612 case exc_faultvaddr:m_state.context.exc.__faultvaddr = value->value.uint64; success = true; break; 1613 } 1614 break; 1615 } 1616 } 1617 1618 if (success) 1619 return SetRegisterState(set) == KERN_SUCCESS; 1620 return false; 1621} 1622 1623 1624nub_size_t 1625DNBArchImplX86_64::GetRegisterContext (void *buf, nub_size_t buf_len) 1626{ 1627 nub_size_t size = sizeof (m_state.context); 1628 1629 if (buf && buf_len) 1630 { 1631 if (size > buf_len) 1632 size = buf_len; 1633 1634 bool force = false; 1635 if (GetGPRState(force) | GetFPUState(force) | GetEXCState(force)) 1636 return 0; 1637 ::memcpy (buf, &m_state.context, size); 1638 } 1639 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::GetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1640 // Return the size of the register context even if NULL was passed in 1641 return size; 1642} 1643 1644nub_size_t 1645DNBArchImplX86_64::SetRegisterContext (const void *buf, nub_size_t buf_len) 1646{ 1647 nub_size_t size = sizeof (m_state.context); 1648 if (buf == NULL || buf_len == 0) 1649 size = 0; 1650 1651 if (size) 1652 { 1653 if (size > buf_len) 1654 size = buf_len; 1655 1656 ::memcpy (&m_state.context, buf, size); 1657 SetGPRState(); 1658 SetFPUState(); 1659 SetEXCState(); 1660 } 1661 DNBLogThreadedIf (LOG_THREAD, "DNBArchImplX86_64::SetRegisterContext (buf = %p, len = %zu) => %zu", buf, buf_len, size); 1662 return size; 1663} 1664 1665 1666kern_return_t 1667DNBArchImplX86_64::GetRegisterState(int set, bool force) 1668{ 1669 switch (set) 1670 { 1671 case e_regSetALL: return GetGPRState(force) | GetFPUState(force) | GetEXCState(force); 1672 case e_regSetGPR: return GetGPRState(force); 1673 case e_regSetFPU: return GetFPUState(force); 1674 case e_regSetEXC: return GetEXCState(force); 1675 default: break; 1676 } 1677 return KERN_INVALID_ARGUMENT; 1678} 1679 1680kern_return_t 1681DNBArchImplX86_64::SetRegisterState(int set) 1682{ 1683 // Make sure we have a valid context to set. 1684 if (RegisterSetStateIsValid(set)) 1685 { 1686 switch (set) 1687 { 1688 case e_regSetALL: return SetGPRState() | SetFPUState() | SetEXCState(); 1689 case e_regSetGPR: return SetGPRState(); 1690 case e_regSetFPU: return SetFPUState(); 1691 case e_regSetEXC: return SetEXCState(); 1692 default: break; 1693 } 1694 } 1695 return KERN_INVALID_ARGUMENT; 1696} 1697 1698bool 1699DNBArchImplX86_64::RegisterSetStateIsValid (int set) const 1700{ 1701 return m_state.RegsAreValid(set); 1702} 1703 1704 1705 1706#endif // #if defined (__i386__) || defined (__x86_64__) 1707