TargetTransformInfo.h revision d1b8ef97c47d347f2a2261a0d6de4872f248321f 
1//===- llvm/Analysis/TargetTransformInfo.h ----------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass exposes codegen information to IR-level passes. Every
11// transformation that uses codegen information is broken into three parts:
12// 1. The IR-level analysis pass.
13// 2. The IR-level transformation interface which provides the needed
14//    information.
15// 3. Codegen-level implementation which uses target-specific hooks.
16//
17// This file defines #2, which is the interface that IR-level transformations
18// use for querying the codegen.
19//
20//===----------------------------------------------------------------------===//
21
22#ifndef LLVM_ANALYSIS_TARGET_TRANSFORM_INTERFACE
23#define LLVM_ANALYSIS_TARGET_TRANSFORM_INTERFACE
24
25#include "llvm/IR/GlobalValue.h"
26#include "llvm/IR/Intrinsics.h"
27#include "llvm/IR/Type.h"
28#include "llvm/Pass.h"
29#include "llvm/Support/DataTypes.h"
30
31namespace llvm {
32
33/// TargetTransformInfo - This pass provides access to the codegen
34/// interfaces that are needed for IR-level transformations.
35class TargetTransformInfo {
36protected:
37  /// \brief The TTI instance one level down the stack.
38  ///
39  /// This is used to implement the default behavior all of the methods which
40  /// is to delegate up through the stack of TTIs until one can answer the
41  /// query.
42  TargetTransformInfo *PrevTTI;
43
44  /// \brief The top of the stack of TTI analyses available.
45  ///
46  /// This is a convenience routine maintained as TTI analyses become available
47  /// that complements the PrevTTI delegation chain. When one part of an
48  /// analysis pass wants to query another part of the analysis pass it can use
49  /// this to start back at the top of the stack.
50  TargetTransformInfo *TopTTI;
51
52  /// All pass subclasses must in their initializePass routine call
53  /// pushTTIStack with themselves to update the pointers tracking the previous
54  /// TTI instance in the analysis group's stack, and the top of the analysis
55  /// group's stack.
56  void pushTTIStack(Pass *P);
57
58  /// All pass subclasses must in their finalizePass routine call popTTIStack
59  /// to update the pointers tracking the previous TTI instance in the analysis
60  /// group's stack, and the top of the analysis group's stack.
61  void popTTIStack();
62
63  /// All pass subclasses must call TargetTransformInfo::getAnalysisUsage.
64  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
65
66public:
67  /// This class is intended to be subclassed by real implementations.
68  virtual ~TargetTransformInfo() = 0;
69
70  /// \name Scalar Target Information
71  /// @{
72
73  /// \brief Flags indicating the kind of support for population count.
74  ///
75  /// Compared to the SW implementation, HW support is supposed to
76  /// significantly boost the performance when the population is dense, and it
77  /// may or may not degrade performance if the population is sparse. A HW
78  /// support is considered as "Fast" if it can outperform, or is on a par
79  /// with, SW implementaion when the population is sparse; otherwise, it is
80  /// considered as "Slow".
81  enum PopcntSupportKind {
82    PSK_Software,
83    PSK_SlowHardware,
84    PSK_FastHardware
85  };
86
87  /// isLegalAddImmediate - Return true if the specified immediate is legal
88  /// add immediate, that is the target has add instructions which can add
89  /// a register with the immediate without having to materialize the
90  /// immediate into a register.
91  virtual bool isLegalAddImmediate(int64_t Imm) const;
92
93  /// isLegalICmpImmediate - Return true if the specified immediate is legal
94  /// icmp immediate, that is the target has icmp instructions which can compare
95  /// a register against the immediate without having to materialize the
96  /// immediate into a register.
97  virtual bool isLegalICmpImmediate(int64_t Imm) const;
98
99  /// isLegalAddressingMode - Return true if the addressing mode represented by
100  /// AM is legal for this target, for a load/store of the specified type.
101  /// The type may be VoidTy, in which case only return true if the addressing
102  /// mode is legal for a load/store of any legal type.
103  /// TODO: Handle pre/postinc as well.
104  virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
105                                     int64_t BaseOffset, bool HasBaseReg,
106                                     int64_t Scale) const;
107
108  /// isTruncateFree - Return true if it's free to truncate a value of
109  /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
110  /// register EAX to i16 by referencing its sub-register AX.
111  virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
112
113  /// Is this type legal.
114  virtual bool isTypeLegal(Type *Ty) const;
115
116  /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
117  virtual unsigned getJumpBufAlignment() const;
118
119  /// getJumpBufSize - returns the target's jmp_buf size in bytes.
120  virtual unsigned getJumpBufSize() const;
121
122  /// shouldBuildLookupTables - Return true if switches should be turned into
123  /// lookup tables for the target.
124  virtual bool shouldBuildLookupTables() const;
125
126  /// getPopcntSupport - Return hardware support for population count.
127  virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
128
129  /// getIntImmCost - Return the expected cost of materializing the given
130  /// integer immediate of the specified type.
131  virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
132
133  /// @}
134
135  /// \name Vector Target Information
136  /// @{
137
138  enum ShuffleKind {
139    Broadcast,       // Broadcast element 0 to all other elements.
140    Reverse,         // Reverse the order of the vector.
141    InsertSubvector, // InsertSubvector. Index indicates start offset.
142    ExtractSubvector // ExtractSubvector Index indicates start offset.
143  };
144
145  /// \return The number of scalar or vector registers that the target has.
146  /// If 'Vectors' is true, it returns the number of vector registers. If it is
147  /// set to false, it returns the number of scalar registers.
148  virtual unsigned getNumberOfRegisters(bool Vector) const;
149
150  /// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
151  virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const;
152
153  /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
154  /// The index and subtype parameters are used by the subvector insertion and
155  /// extraction shuffle kinds.
156  virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, int Index = 0,
157                                  Type *SubTp = 0) const;
158
159  /// \return The expected cost of cast instructions, such as bitcast, trunc,
160  /// zext, etc.
161  virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
162                                    Type *Src) const;
163
164  /// \return The expected cost of control-flow related instrutctions such as
165  /// Phi, Ret, Br.
166  virtual unsigned getCFInstrCost(unsigned Opcode) const;
167
168  /// \returns The expected cost of compare and select instructions.
169  virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
170                                      Type *CondTy = 0) const;
171
172  /// \return The expected cost of vector Insert and Extract.
173  /// Use -1 to indicate that there is no information on the index value.
174  virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
175                                      unsigned Index = -1) const;
176
177  /// \return The cost of Load and Store instructions.
178  virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
179                                   unsigned Alignment,
180                                   unsigned AddressSpace) const;
181
182  /// \returns The cost of Intrinsic instructions.
183  virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
184                                         ArrayRef<Type *> Tys) const;
185
186  /// \returns The number of pieces into which the provided type must be
187  /// split during legalization. Zero is returned when the answer is unknown.
188  virtual unsigned getNumberOfParts(Type *Tp) const;
189
190  /// @}
191
192  /// Analysis group identification.
193  static char ID;
194};
195
196/// \brief Create the base case instance of a pass in the TTI analysis group.
197///
198/// This class provides the base case for the stack of TTI analyses. It doesn't
199/// delegate to anything and uses the STTI and VTTI objects passed in to
200/// satisfy the queries.
201ImmutablePass *createNoTargetTransformInfoPass();
202
203} // End llvm namespace
204
205#endif
206