FastISel.h revision e50ed30282bb5b4a9ed952580523f2dda16215ac 
1//===-- FastISel.h - Definition of the FastISel class ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FASTISEL_H
15#define LLVM_CODEGEN_FASTISEL_H
16
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/SmallSet.h"
19#include "llvm/CodeGen/SelectionDAGNodes.h"
20
21namespace llvm {
22
23class AllocaInst;
24class ConstantFP;
25class Instruction;
26class MachineBasicBlock;
27class MachineConstantPool;
28class MachineFunction;
29class MachineFrameInfo;
30class MachineModuleInfo;
31class DwarfWriter;
32class MachineRegisterInfo;
33class TargetData;
34class TargetInstrInfo;
35class TargetLowering;
36class TargetMachine;
37class TargetRegisterClass;
38
39/// FastISel - This is a fast-path instruction selection class that
40/// generates poor code and doesn't support illegal types or non-trivial
41/// lowering, but runs quickly.
42class FastISel {
43protected:
44  MachineBasicBlock *MBB;
45  DenseMap<const Value *, unsigned> LocalValueMap;
46  DenseMap<const Value *, unsigned> &ValueMap;
47  DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
48  DenseMap<const AllocaInst *, int> &StaticAllocaMap;
49#ifndef NDEBUG
50  SmallSet<Instruction*, 8> &CatchInfoLost;
51#endif
52  MachineFunction &MF;
53  MachineModuleInfo *MMI;
54  DwarfWriter *DW;
55  MachineRegisterInfo &MRI;
56  MachineFrameInfo &MFI;
57  MachineConstantPool &MCP;
58  DebugLoc DL;
59  const TargetMachine &TM;
60  const TargetData &TD;
61  const TargetInstrInfo &TII;
62  const TargetLowering &TLI;
63
64public:
65  /// startNewBlock - Set the current block to which generated machine
66  /// instructions will be appended, and clear the local CSE map.
67  ///
68  void startNewBlock(MachineBasicBlock *mbb) {
69    setCurrentBlock(mbb);
70    LocalValueMap.clear();
71  }
72
73  /// setCurrentBlock - Set the current block to which generated machine
74  /// instructions will be appended.
75  ///
76  void setCurrentBlock(MachineBasicBlock *mbb) {
77    MBB = mbb;
78  }
79
80  /// setCurDebugLoc - Set the current debug location information, which is used
81  /// when creating a machine instruction.
82  ///
83  void setCurDebugLoc(DebugLoc dl) { DL = dl; }
84
85  /// getCurDebugLoc() - Return current debug location information.
86  DebugLoc getCurDebugLoc() const { return DL; }
87
88  /// SelectInstruction - Do "fast" instruction selection for the given
89  /// LLVM IR instruction, and append generated machine instructions to
90  /// the current block. Return true if selection was successful.
91  ///
92  bool SelectInstruction(Instruction *I);
93
94  /// SelectInstruction - Do "fast" instruction selection for the given
95  /// LLVM IR operator (Instruction or ConstantExpr), and append
96  /// generated machine instructions to the current block. Return true
97  /// if selection was successful.
98  ///
99  bool SelectOperator(User *I, unsigned Opcode);
100
101  /// TargetSelectInstruction - This method is called by target-independent
102  /// code when the normal FastISel process fails to select an instruction.
103  /// This gives targets a chance to emit code for anything that doesn't
104  /// fit into FastISel's framework. It returns true if it was successful.
105  ///
106  virtual bool
107  TargetSelectInstruction(Instruction *I) = 0;
108
109  /// getRegForValue - Create a virtual register and arrange for it to
110  /// be assigned the value for the given LLVM value.
111  unsigned getRegForValue(Value *V);
112
113  /// lookUpRegForValue - Look up the value to see if its value is already
114  /// cached in a register. It may be defined by instructions across blocks or
115  /// defined locally.
116  unsigned lookUpRegForValue(Value *V);
117
118  /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
119  /// takes care of truncating or sign-extending the given getelementptr
120  /// index value.
121  unsigned getRegForGEPIndex(Value *V);
122
123  virtual ~FastISel();
124
125protected:
126  FastISel(MachineFunction &mf,
127           MachineModuleInfo *mmi,
128           DwarfWriter *dw,
129           DenseMap<const Value *, unsigned> &vm,
130           DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
131           DenseMap<const AllocaInst *, int> &am
132#ifndef NDEBUG
133           , SmallSet<Instruction*, 8> &cil
134#endif
135           );
136
137  /// FastEmit_r - This method is called by target-independent code
138  /// to request that an instruction with the given type and opcode
139  /// be emitted.
140  virtual unsigned FastEmit_(EVT::SimpleValueType VT,
141                             EVT::SimpleValueType RetVT,
142                             ISD::NodeType Opcode);
143
144  /// FastEmit_r - This method is called by target-independent code
145  /// to request that an instruction with the given type, opcode, and
146  /// register operand be emitted.
147  ///
148  virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
149                              EVT::SimpleValueType RetVT,
150                              ISD::NodeType Opcode, unsigned Op0);
151
152  /// FastEmit_rr - This method is called by target-independent code
153  /// to request that an instruction with the given type, opcode, and
154  /// register operands be emitted.
155  ///
156  virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
157                               EVT::SimpleValueType RetVT,
158                               ISD::NodeType Opcode,
159                               unsigned Op0, unsigned Op1);
160
161  /// FastEmit_ri - This method is called by target-independent code
162  /// to request that an instruction with the given type, opcode, and
163  /// register and immediate operands be emitted.
164  ///
165  virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
166                               EVT::SimpleValueType RetVT,
167                               ISD::NodeType Opcode,
168                               unsigned Op0, uint64_t Imm);
169
170  /// FastEmit_rf - This method is called by target-independent code
171  /// to request that an instruction with the given type, opcode, and
172  /// register and floating-point immediate operands be emitted.
173  ///
174  virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
175                               EVT::SimpleValueType RetVT,
176                               ISD::NodeType Opcode,
177                               unsigned Op0, ConstantFP *FPImm);
178
179  /// FastEmit_rri - This method is called by target-independent code
180  /// to request that an instruction with the given type, opcode, and
181  /// register and immediate operands be emitted.
182  ///
183  virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
184                                EVT::SimpleValueType RetVT,
185                                ISD::NodeType Opcode,
186                                unsigned Op0, unsigned Op1, uint64_t Imm);
187
188  /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
189  /// to emit an instruction with an immediate operand using FastEmit_ri.
190  /// If that fails, it materializes the immediate into a register and try
191  /// FastEmit_rr instead.
192  unsigned FastEmit_ri_(EVT::SimpleValueType VT,
193                        ISD::NodeType Opcode,
194                        unsigned Op0, uint64_t Imm,
195                        EVT::SimpleValueType ImmType);
196
197  /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
198  /// to emit an instruction with an immediate operand using FastEmit_rf.
199  /// If that fails, it materializes the immediate into a register and try
200  /// FastEmit_rr instead.
201  unsigned FastEmit_rf_(EVT::SimpleValueType VT,
202                        ISD::NodeType Opcode,
203                        unsigned Op0, ConstantFP *FPImm,
204                        EVT::SimpleValueType ImmType);
205
206  /// FastEmit_i - This method is called by target-independent code
207  /// to request that an instruction with the given type, opcode, and
208  /// immediate operand be emitted.
209  virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
210                              EVT::SimpleValueType RetVT,
211                              ISD::NodeType Opcode,
212                              uint64_t Imm);
213
214  /// FastEmit_f - This method is called by target-independent code
215  /// to request that an instruction with the given type, opcode, and
216  /// floating-point immediate operand be emitted.
217  virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
218                              EVT::SimpleValueType RetVT,
219                              ISD::NodeType Opcode,
220                              ConstantFP *FPImm);
221
222  /// FastEmitInst_ - Emit a MachineInstr with no operands and a
223  /// result register in the given register class.
224  ///
225  unsigned FastEmitInst_(unsigned MachineInstOpcode,
226                         const TargetRegisterClass *RC);
227
228  /// FastEmitInst_r - Emit a MachineInstr with one register operand
229  /// and a result register in the given register class.
230  ///
231  unsigned FastEmitInst_r(unsigned MachineInstOpcode,
232                          const TargetRegisterClass *RC,
233                          unsigned Op0);
234
235  /// FastEmitInst_rr - Emit a MachineInstr with two register operands
236  /// and a result register in the given register class.
237  ///
238  unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
239                           const TargetRegisterClass *RC,
240                           unsigned Op0, unsigned Op1);
241
242  /// FastEmitInst_ri - Emit a MachineInstr with two register operands
243  /// and a result register in the given register class.
244  ///
245  unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
246                           const TargetRegisterClass *RC,
247                           unsigned Op0, uint64_t Imm);
248
249  /// FastEmitInst_rf - Emit a MachineInstr with two register operands
250  /// and a result register in the given register class.
251  ///
252  unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
253                           const TargetRegisterClass *RC,
254                           unsigned Op0, ConstantFP *FPImm);
255
256  /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
257  /// an immediate, and a result register in the given register class.
258  ///
259  unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
260                            const TargetRegisterClass *RC,
261                            unsigned Op0, unsigned Op1, uint64_t Imm);
262
263  /// FastEmitInst_i - Emit a MachineInstr with a single immediate
264  /// operand, and a result register in the given register class.
265  unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
266                          const TargetRegisterClass *RC,
267                          uint64_t Imm);
268
269  /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
270  /// from a specified index of a superregister to a specified type.
271  unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
272                                      unsigned Op0, uint32_t Idx);
273
274  /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
275  /// with all but the least significant bit set to zero.
276  unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
277                              unsigned Op);
278
279  /// FastEmitBranch - Emit an unconditional branch to the given block,
280  /// unless it is the immediate (fall-through) successor, and update
281  /// the CFG.
282  void FastEmitBranch(MachineBasicBlock *MBB);
283
284  unsigned UpdateValueMap(Value* I, unsigned Reg);
285
286  unsigned createResultReg(const TargetRegisterClass *RC);
287
288  /// TargetMaterializeConstant - Emit a constant in a register using
289  /// target-specific logic, such as constant pool loads.
290  virtual unsigned TargetMaterializeConstant(Constant* C) {
291    return 0;
292  }
293
294  /// TargetMaterializeAlloca - Emit an alloca address in a register using
295  /// target-specific logic.
296  virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
297    return 0;
298  }
299
300private:
301  bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
302
303  bool SelectGetElementPtr(User *I);
304
305  bool SelectCall(User *I);
306
307  bool SelectBitCast(User *I);
308
309  bool SelectCast(User *I, ISD::NodeType Opcode);
310};
311
312}
313
314#endif
315