MachineInstrBuilder.h revision d68a07650cdb2e18f18f362ba533459aa10e01b6 
1//===-- CodeGen/MachineInstBuilder.h - Simplify creation of MIs -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file exposes a function named BuildMI, which is useful for dramatically
11// simplifying how MachineInstr's are created.  It allows use of code like this:
12//
13//   M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
18#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19
20#include "llvm/CodeGen/MachineFunction.h"
21
22namespace llvm {
23
24class TargetInstrDesc;
25
26class MachineInstrBuilder {
27  MachineInstr *MI;
28public:
29  explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}
30
31  /// Allow automatic conversion to the machine instruction we are working on.
32  ///
33  operator MachineInstr*() const { return MI; }
34  operator MachineBasicBlock::iterator() const { return MI; }
35
36  /// addReg - Add a new virtual register operand...
37  ///
38  const
39  MachineInstrBuilder &addReg(unsigned RegNo, bool isDef = false,
40                              bool isImp = false, bool isKill = false,
41                              bool isDead = false, unsigned SubReg = 0) const {
42    MI->addOperand(MachineOperand::CreateReg(RegNo, isDef, isImp, isKill,
43                                             isDead, SubReg));
44    return *this;
45  }
46
47  /// addImm - Add a new immediate operand.
48  ///
49  const MachineInstrBuilder &addImm(int64_t Val) const {
50    MI->addOperand(MachineOperand::CreateImm(Val));
51    return *this;
52  }
53
54  const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
55    MI->addOperand(MachineOperand::CreateFPImm(Val));
56    return *this;
57  }
58
59  const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB) const {
60    MI->addOperand(MachineOperand::CreateMBB(MBB));
61    return *this;
62  }
63
64  const MachineInstrBuilder &addFrameIndex(unsigned Idx) const {
65    MI->addOperand(MachineOperand::CreateFI(Idx));
66    return *this;
67  }
68
69  const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
70                                                  int Offset = 0) const {
71    MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
72    return *this;
73  }
74
75  const MachineInstrBuilder &addJumpTableIndex(unsigned Idx) const {
76    MI->addOperand(MachineOperand::CreateJTI(Idx));
77    return *this;
78  }
79
80  const MachineInstrBuilder &addGlobalAddress(GlobalValue *GV,
81                                              int64_t Offset = 0) const {
82    MI->addOperand(MachineOperand::CreateGA(GV, Offset));
83    return *this;
84  }
85
86  const MachineInstrBuilder &addExternalSymbol(const char *FnName,
87                                               int64_t Offset = 0) const {
88    MI->addOperand(MachineOperand::CreateES(FnName, Offset));
89    return *this;
90  }
91
92  const MachineInstrBuilder &addMemOperand(const MachineMemOperand &MMO) const {
93    MI->addMemOperand(*MI->getParent()->getParent(), MMO);
94    return *this;
95  }
96};
97
98/// BuildMI - Builder interface.  Specify how to create the initial instruction
99/// itself.
100///
101inline MachineInstrBuilder BuildMI(MachineFunction &MF,
102                                   const TargetInstrDesc &TID) {
103  return MachineInstrBuilder(MF.CreateMachineInstr(TID));
104}
105
106/// BuildMI - This version of the builder sets up the first operand as a
107/// destination virtual register.
108///
109inline MachineInstrBuilder  BuildMI(MachineFunction &MF,
110                                    const TargetInstrDesc &TID,
111                                    unsigned DestReg) {
112  return MachineInstrBuilder(MF.CreateMachineInstr(TID)).addReg(DestReg, true);
113}
114
115/// BuildMI - This version of the builder inserts the newly-built
116/// instruction before the given position in the given MachineBasicBlock, and
117/// sets up the first operand as a destination virtual register.
118///
119inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
120                                   MachineBasicBlock::iterator I,
121                                   const TargetInstrDesc &TID,
122                                   unsigned DestReg) {
123  MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID);
124  BB.insert(I, MI);
125  return MachineInstrBuilder(MI).addReg(DestReg, true);
126}
127
128/// BuildMI - This version of the builder inserts the newly-built
129/// instruction before the given position in the given MachineBasicBlock, and
130/// does NOT take a destination register.
131///
132inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
133                                   MachineBasicBlock::iterator I,
134                                   const TargetInstrDesc &TID) {
135  MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID);
136  BB.insert(I, MI);
137  return MachineInstrBuilder(MI);
138}
139
140/// BuildMI - This version of the builder inserts the newly-built
141/// instruction at the end of the given MachineBasicBlock, and does NOT take a
142/// destination register.
143///
144inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
145                                   const TargetInstrDesc &TID) {
146  return BuildMI(*BB, BB->end(), TID);
147}
148
149/// BuildMI - This version of the builder inserts the newly-built
150/// instruction at the end of the given MachineBasicBlock, and sets up the first
151/// operand as a destination virtual register.
152///
153inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
154                                   const TargetInstrDesc &TID,
155                                   unsigned DestReg) {
156  return BuildMI(*BB, BB->end(), TID, DestReg);
157}
158
159} // End llvm namespace
160
161#endif
162