MachineRegisterInfo.h revision 00ffd505d327782eb51fa55e47967fd8e62ba40a
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 1943d1fd449f1a0ac9d9dafa0b9569bb6b2e976198Anton Korobeynikov#include "llvm/ADT/iterator.h" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 2984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 306f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 3511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 3611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 3711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers. For each target register class, it keeps a list of 3811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers belonging to the class. 3911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<std::vector<unsigned> > RegClass2VRegMap; 4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 4362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 4484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 4584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 4684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 4784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 4884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 4984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 5184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 5962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 6062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 636f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 6462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 6562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 666c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 676c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 686c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 716c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 726c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 73c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool Uses, bool Defs> 74c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 75c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 76c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 77c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 78c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,true> reg_iterator; 796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 816c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 83c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 8400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 8500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 8600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 8700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 88c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 89c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<false,true> def_iterator; 90c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 91c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 92c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 93c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 94c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 9500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 9600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 9700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 9800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 99c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 100c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,false> use_iterator; 101c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 102c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 103c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 104c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 105c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 106ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 107ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 108ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 109ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1106c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 111e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 112e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 113e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 114e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 115e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 11662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 11762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 11862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1196f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 12062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 1216f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 12262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 12362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 12484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1266f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1276c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 1286f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1296c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 1306c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1311eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1321eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1331eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1341eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1351eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 1361eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1371eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1381eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1391eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 14084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 14184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 14284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 14384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 14484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 14584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 14611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 1471eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 1486f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 14984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 15062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 15184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 152bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 153bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 15411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 155bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng void setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 15611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng unsigned VR = Reg; 157bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 158bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 15911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 160bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng VRegInfo[Reg].first = RC; 16111a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 16211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng // Remove from old register class's vregs list. This may be slow but 16311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng // fortunately this operation is rarely needed. 16411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 16511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 16611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng VRegs.erase(I); 16711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 16811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng // Add to new register class's vregs list. 16911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng RegClass2VRegMap[RC->getID()].push_back(VR); 170bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng } 17162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 17284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 17384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 17484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 1752e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 17684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 17784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 17884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 17984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 18034cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 18184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 18211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 18311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// getRegClassVirtRegs - Return the list of virtual registers of the given 18411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// target register class. 18511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 18611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng return RegClass2VRegMap[RC->getID()]; 18711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng } 188a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 18984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 19084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 19184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 19284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 19384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 19484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 19584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 19684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 19784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 19884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 19984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 20084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 20284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 20384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 20484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 20784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 20884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 20984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 21184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 21284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 21384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 21484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 21584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 21684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 21884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 21984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 22084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 22184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 22284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 22384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 22484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 22584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 22684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 22784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 2286d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 2296d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman bool isLiveIn(unsigned Reg) const { 2306d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2316d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman if (I->first == Reg || I->second == Reg) 2326d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return true; 2336d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return false; 2346d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman } 2356d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 23662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 23762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 2386c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2396c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 240c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 241c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 242c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 243c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 244c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns end(). 245c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool ReturnUses, bool ReturnDefs> 246c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 247c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner : public forward_iterator<MachineInstr, ptrdiff_t> { 2486c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 2491327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 250c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 251c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 252c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 253ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 254ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && op->isDef())) 255c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 256c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 257c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 2586c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 2596c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 260e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference; 261e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer; 2626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 263c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 264c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 2656c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 266c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 2676c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 2686c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 269c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 2706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 2716c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2726c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 2746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 2756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 277c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 2786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 2796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 280c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 281c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 282ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 283ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && Op->isDef()))) 284c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 285c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 2866c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 2876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 288c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 289c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 2906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 292e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 2936c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 2946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 2956c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2966c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 297e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 298e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 299e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 300e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 301e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 302e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 303e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 304e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 305e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 306e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 307e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 308e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 309e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 310e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 311e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 312e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 313e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 3146c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 3156c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 31684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 31784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 31884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 31984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 32084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 321