MachineRegisterInfo.h revision 03fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 18994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen#include "llvm/ADT/IndexedMap.h" 19255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/CodeGen/MachineInstrBundle.h" 20d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling#include "llvm/Target/TargetMachine.h" 21255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/Target/TargetRegisterInfo.h" 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2590019479f9a3868d8be90564695097a61a725438Andrew Trick 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 271213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 281213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 3003fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Laceypublic: 3103fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey class Delegate { 3203fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey public: 3303fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey virtual void MRI_NoteNewVirtualRegister(unsigned Reg) {} 3403fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey 3503fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey virtual ~Delegate() {} 3603fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey }; 3703fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey 3803fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Laceyprivate: 39d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling const TargetMachine &TM; 4003fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey Delegate *TheDelegate; 41e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 4273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// IsSSA - True when the machine function is in SSA form and virtual 4373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// registers have a single def. 4473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool IsSSA; 4573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 46aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// TracksLiveness - True while register liveness is being tracked accurately. 47aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// Basic block live-in lists, kill flags, and implicit defs may not be 48aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// accurate when after this flag is cleared. 49aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen bool TracksLiveness; 50aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen 51994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen /// VRegInfo - Information we keep for each virtual register. 5262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 5362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 5462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 55994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 56994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VirtReg2IndexFunctor> VRegInfo; 5711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 5890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 59358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 60358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 61358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 62358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 63358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 6490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 65994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 6690019479f9a3868d8be90564695097a61a725438Andrew Trick 6762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 6862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 6990019479f9a3868d8be90564695097a61a725438Andrew Trick MachineOperand **PhysRegUseDefLists; 7090019479f9a3868d8be90564695097a61a725438Andrew Trick 71ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen /// getRegUseDefListHead - Return the head pointer for the register use/def 72ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen /// list for the specified virtual or physical register. 73ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 74ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 75ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen return VRegInfo[RegNo].second; 76ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 77ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen } 78ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 79ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 80ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 81ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen return VRegInfo[RegNo].second; 82ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 83ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen } 84ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 85fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen /// Get the next element in the use-def chain. 86fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 87fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen assert(MO && MO->isReg() && "This is not a register operand!"); 88fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen return MO->Contents.Reg.Next; 89fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen } 90fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen 914b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// UsedRegUnits - This is a bit vector that is computed and set by the 9284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 9384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 9484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 9584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 964b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// This vector has bits set for register units that are modified in the 974b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// current function. It doesn't include registers clobbered by function 984b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// calls with register mask operands. 994b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen BitVector UsedRegUnits; 1004b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen 1014b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// UsedPhysRegMask - Additional used physregs including aliases. 1024b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// This bit vector represents all the registers clobbered by function calls. 1034b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// It can model things that UsedRegUnits can't, such as function calls that 1044b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen /// clobber ymm7 but preserve the low half in xmm7. 105d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen BitVector UsedPhysRegMask; 106d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 107d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// ReservedRegs - This is a bit vector of reserved registers. The target 108d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// may change its mind about which registers should be reserved. This 109d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// vector is the frozen set of reserved registers when register allocation 110d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// started. 111d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen BitVector ReservedRegs; 112d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 113e6dc59891fc53d65b3f6d19772d26e23e0cc1cacJakob Stoklund Olesen /// Keep track of the physical registers that are live in to the function. 1146acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky /// Live in values are typically arguments in registers. LiveIn values are 1156acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky /// allowed to have virtual registers associated with them, stored in the 1166acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky /// second element. 11784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 11890019479f9a3868d8be90564695097a61a725438Andrew Trick 119001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 120001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 12184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 122d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling explicit MachineRegisterInfo(const TargetMachine &TM); 12362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 12473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 12503dca5e4b6c41e1e7fa4edad3d7ff8d5f6de7008Andrew Trick const TargetRegisterInfo *getTargetRegisterInfo() const { 12603dca5e4b6c41e1e7fa4edad3d7ff8d5f6de7008Andrew Trick return TM.getRegisterInfo(); 12703dca5e4b6c41e1e7fa4edad3d7ff8d5f6de7008Andrew Trick } 12803dca5e4b6c41e1e7fa4edad3d7ff8d5f6de7008Andrew Trick 12903fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey void resetDelegate(Delegate *delegate) { 13003fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey // Ensure another delegate does not take over unless the current 13103fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey // delegate first unattaches itself. If we ever need to multicast 13203fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey // notifications, we will need to change to using a list. 13303fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey assert(TheDelegate == delegate && 13403fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey "Only the current delegate can perform reset!"); 13503fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey TheDelegate = 0; 13603fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey } 13703fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey 13803fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey void setDelegate(Delegate *delegate) { 13903fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey assert(delegate && !TheDelegate && 14003fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey "Attempted to set delegate to null, or to change it without " 14103fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey "first resetting it!"); 14203fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey 14303fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey TheDelegate = delegate; 14403fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey } 14503fe68e0a9c0fdd196f62899cb44b6f9a56dd7c8Mark Lacey 14673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 14773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // Function State 14873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 14973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 15073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // isSSA - Returns true when the machine function is in SSA form. Early 15173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // passes require the machine function to be in SSA form where every virtual 15273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register has a single defining instruction. 15373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // 15473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // The TwoAddressInstructionPass and PHIElimination passes take the machine 15573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // function out of SSA form when they introduce multiple defs per virtual 15673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register. 15773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool isSSA() const { return IsSSA; } 15873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 15973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // leaveSSA - Indicates that the machine function is no longer in SSA form. 16073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen void leaveSSA() { IsSSA = false; } 16173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 162aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// tracksLiveness - Returns true when tracking register liveness accurately. 163aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// 164aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// While this flag is true, register liveness information in basic block 165aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// live-in lists and machine instruction operands is accurate. This means it 166aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// can be used to change the code in ways that affect the values in 167aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// registers, for example by the register scavenger. 168aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// 169aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// When this flag is false, liveness is no longer reliable. 170aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen bool tracksLiveness() const { return TracksLiveness; } 171aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen 172aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// invalidateLiveness - Indicates that register liveness is no longer being 173aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// tracked accurately. 174aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// 175aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// This should be called by late passes that invalidate the liveness 176aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// information. 177aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen void invalidateLiveness() { TracksLiveness = false; } 178aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen 1796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 1806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 1816c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 1826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 183ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen // Strictly for use by MachineInstr.cpp. 184ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen void addRegOperandToUseList(MachineOperand *MO); 185ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 186ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen // Strictly for use by MachineInstr.cpp. 187ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen void removeRegOperandFromUseList(MachineOperand *MO); 188ff2b99afc8cbc6cfa73181072888e0f9f07deb7eJakob Stoklund Olesen 189bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen // Strictly for use by MachineInstr.cpp. 190bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 191bced5cd924e47818d67e33b3ae1550ab96fc239aJakob Stoklund Olesen 192a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen /// Verify the sanity of the use list for Reg. 193a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen void verifyUseList(unsigned Reg) const; 194a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 195a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen /// Verify the use list of all registers. 196a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen void verifyUseLists() const; 197a58d67af29d38fa37c94f59af37db9df75f349beJakob Stoklund Olesen 1986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 1996c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 2006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 201a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 202c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 203c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 204fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen // Make it a friend so it can access getNextOperandForReg(). 205fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen template<bool, bool, bool> friend class defusechain_iterator; 206fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen 207c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 208c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 209a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 2106c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 2116c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 2126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 214c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 21500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 21600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 21700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 21800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 219c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 220c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// of the specified register, skipping those marked as Debug. 221c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 222c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 223c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 224c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 225c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 226c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 227c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_empty - Return true if the only instructions using or defining 228c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// Reg are Debug instructions. 229c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen bool reg_nodbg_empty(unsigned RegNo) const { 230c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 231c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 232c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 233c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 234a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 235c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 236c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 237c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 238c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 239c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 24000ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 24100ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 24200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 24300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 2440492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick /// hasOneDef - Return true if there is exactly one instruction defining the 2450492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick /// specified register. 2460492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick bool hasOneDef(unsigned RegNo) const { 2470492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick def_iterator DI = def_begin(RegNo); 2480492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick if (DI == def_end()) 2490492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick return false; 2500492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick return ++DI == def_end(); 2510492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick } 2520492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick 253c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 254a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 255c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 256c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 257c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 258c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 25990019479f9a3868d8be90564695097a61a725438Andrew Trick 260ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 261ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 262ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 263ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 2641423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneUse - Return true if there is exactly one instruction using the 2651423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// specified register. 266269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick bool hasOneUse(unsigned RegNo) const { 267269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick use_iterator UI = use_begin(RegNo); 268269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick if (UI == use_end()) 269269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick return false; 270269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick return ++UI == use_end(); 271269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick } 2721423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 273a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 274a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 275a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 276a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 277a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 278a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 279a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 28090019479f9a3868d8be90564695097a61a725438Andrew Trick 281a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 282a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 283a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 284a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 285a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 286a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 2871423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 2881423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// instruction using the specified register. 2891423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneNonDBGUse(unsigned RegNo) const; 2901423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 291e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 292e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 293e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 2944007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 2954007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// Note that it is usually necessary to first constrain ToReg's register 2964007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// class to match the FromReg constraints using: 2974007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 2984007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// constrainRegClass(ToReg, getRegClass(FromReg)) 2994007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 3004007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// That function will return NULL if the virtual registers have incompatible 3014007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// constraints. 302e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 30390019479f9a3868d8be90564695097a61a725438Andrew Trick 3041eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 3051eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 3061eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 3071eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 30849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 30954d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren /// getUniqueVRegDef - Return the unique machine instr that defines the 31054d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren /// specified virtual register or null if none is found. If there are 31154d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren /// multiple definitions or no definition, return null. 31254d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren MachineInstr *getUniqueVRegDef(unsigned Reg) const; 31354d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren 31449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clearKillFlags - Iterate over all the uses of the given register and 31549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clear the kill flag from the MachineOperand. This function is used by 31649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// optimization passes which extend register lifetimes and need only 31749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// preserve conservative kill flag information. 31849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman void clearKillFlags(unsigned Reg) const; 31990019479f9a3868d8be90564695097a61a725438Andrew Trick 3201eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 3211eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 3221eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 323c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 324c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 325c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// throughout the function. It is safe to move instructions that read such 326c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// a physreg. 327c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 328c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 32984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 33084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 33184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 33290019479f9a3868d8be90564695097a61a725438Andrew Trick 33384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 33411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 3351eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 33662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 33784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 338bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 339bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 34011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 34133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 34211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 343bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// constrainRegClass - Constrain the register class of the specified virtual 34491fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// register to be a common subclass of RC and the current register class, 34591fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// but only if the new class has at least MinNumRegs registers. Return the 34691fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// new register class, or NULL if no such class exists. 347bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// This should only be used when the constraint is known to be trivial, like 348bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 3496d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 350bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *constrainRegClass(unsigned Reg, 35191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 35291fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs = 0); 353bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 3546d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// recomputeRegClass - Try to find a legal super-class of Reg's register 3556d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// class that still satisfies the constraints from the instructions using 3566d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// Reg. Returns true if Reg was upgraded. 3576d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 3586d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// This method can be used after constraints have been removed from a 3596d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// virtual register, for example after removing instructions or splitting 3606d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// the live range. 3616d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 3626d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen bool recomputeRegClass(unsigned Reg, const TargetMachine&); 3636d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 36484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 36584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 36684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 3672e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 36884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 369b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// getNumVirtRegs - Return the number of virtual registers created. 370b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// 371b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen unsigned getNumVirtRegs() const { return VRegInfo.size(); } 372b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 37319273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 37419273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick void clearVirtRegs(); 37519273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 37690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 37790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 378358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 37990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 38090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 38190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 38290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 38390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 38490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 385358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 38690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 38790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 38890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 38990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 39051458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 39151458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// standard simple hint (Type == 0) is not set. 39251458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen unsigned getSimpleHint(unsigned Reg) const { 39351458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 39451458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen return Hint.first ? 0 : Hint.second; 39551458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen } 39651458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 39751458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 39884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 39984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 40084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 40190019479f9a3868d8be90564695097a61a725438Andrew Trick 40284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 4039aa6e0a134358c681cc5918ec65b1ec9726b778eJakob Stoklund Olesen /// function. Also check for clobbered aliases and registers clobbered by 4049aa6e0a134358c681cc5918ec65b1ec9726b778eJakob Stoklund Olesen /// function calls with register mask operands. 4059aa6e0a134358c681cc5918ec65b1ec9726b778eJakob Stoklund Olesen /// 4069aa6e0a134358c681cc5918ec65b1ec9726b778eJakob Stoklund Olesen /// This only works after register allocation. It is primarily used by 4079aa6e0a134358c681cc5918ec65b1ec9726b778eJakob Stoklund Olesen /// PrologEpilogInserter to determine which callee-saved registers need 4089aa6e0a134358c681cc5918ec65b1ec9726b778eJakob Stoklund Olesen /// spilling. 409d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen bool isPhysRegUsed(unsigned Reg) const { 410d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen if (UsedPhysRegMask.test(Reg)) 411d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen return true; 412d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 413d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling Units.isValid(); ++Units) 4144b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen if (UsedRegUnits.test(*Units)) 415a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen return true; 416a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen return false; 417a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen } 418a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen 419601158a18e325879b224bd1979d824407ed98bc7Jakob Stoklund Olesen /// Mark the specified register unit as used in this function. 420601158a18e325879b224bd1979d824407ed98bc7Jakob Stoklund Olesen /// This should only be called during and after register allocation. 421601158a18e325879b224bd1979d824407ed98bc7Jakob Stoklund Olesen void setRegUnitUsed(unsigned RegUnit) { 422601158a18e325879b224bd1979d824407ed98bc7Jakob Stoklund Olesen UsedRegUnits.set(RegUnit); 423601158a18e325879b224bd1979d824407ed98bc7Jakob Stoklund Olesen } 424601158a18e325879b224bd1979d824407ed98bc7Jakob Stoklund Olesen 42584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 42684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 4274b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen void setPhysRegUsed(unsigned Reg) { 428d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 429d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling Units.isValid(); ++Units) 4304b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen UsedRegUnits.set(*Units); 4314b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen } 43282b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 433d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 434d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// This corresponds to the bit mask attached to register mask operands. 435d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 436d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.setBitsNotInMask(RegMask); 437d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen } 438d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 43984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 44084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 441d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen void setPhysRegUnused(unsigned Reg) { 442d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.reset(Reg); 443d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 444d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling Units.isValid(); ++Units) 4454b1aa961fdbb75035a963f8c6a01c8c5f1dc3f16Jakob Stoklund Olesen UsedRegUnits.reset(*Units); 446d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen } 44784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 448d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 449d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 450d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // Reserved Register Info 451d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 452d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // 453d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // The set of reserved registers must be invariant during register 454d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // allocation. For example, the target cannot suddenly decide it needs a 455d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // frame pointer when the register allocator has already used the frame 456d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // pointer register for something else. 457d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // 458d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // These methods can be used by target hooks like hasFP() to avoid changing 459d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // the reserved register set during register allocation. 460d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 461d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// freezeReservedRegs - Called by the register allocator to freeze the set 462d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// of reserved registers before allocation begins. 463d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen void freezeReservedRegs(const MachineFunction&); 464d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 465d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 466d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// to ensure the set of reserved registers stays constant. 467d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen bool reservedRegsFrozen() const { 468d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen return !ReservedRegs.empty(); 469d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen } 470d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 471d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// canReserveReg - Returns true if PhysReg can be used as a reserved 472d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// register. Any register can be reserved before freezeReservedRegs() is 473d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// called. 474d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen bool canReserveReg(unsigned PhysReg) const { 475d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 476d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen } 477d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 478e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// getReservedRegs - Returns a reference to the frozen set of reserved 479e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// registers. This method should always be preferred to calling 480e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// TRI::getReservedRegs() when possible. 481e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen const BitVector &getReservedRegs() const { 482e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen assert(reservedRegsFrozen() && 483e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen "Reserved registers haven't been frozen yet. " 484e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen "Use TRI::getReservedRegs()."); 485e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen return ReservedRegs; 486e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen } 487e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen 488e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// isReserved - Returns true when PhysReg is a reserved register. 489e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// 490e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// Reserved registers may belong to an allocatable register class, but the 491e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// target has explicitly requested that they are not used. 492e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// 493e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen bool isReserved(unsigned PhysReg) const { 494e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen return getReservedRegs().test(PhysReg); 495e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen } 496e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen 497e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// isAllocatable - Returns true when PhysReg belongs to an allocatable 498e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// register class and it hasn't been reserved. 499e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// 500e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// Allocatable registers may show up in the allocation order of some virtual 501e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// register, so a register allocator needs to track its liveness and 502e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen /// availability. 503e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen bool isAllocatable(unsigned PhysReg) const { 504d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 505d10fa8b1caf010fe4943ae5526c2c3b921339f72Bill Wendling !isReserved(PhysReg); 506e4f273908bd37df5f0f6b2c575dcb2af99f6b85bJakob Stoklund Olesen } 507d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 50884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 5096acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky // LiveIn Management 51084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 51190019479f9a3868d8be90564695097a61a725438Andrew Trick 5126acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky /// addLiveIn - Add the specified register as a live-in. Note that it 51384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 51484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 51584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 51684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 51790019479f9a3868d8be90564695097a61a725438Andrew Trick 5186acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky // Iteration support for the live-ins set. It's kept in sorted order 5196acbcd423b2ace94bb13c0de9d98ea66c5dbe00cEli Bendersky // by register number. 52084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 52184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 52284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 52384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 52484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 5256d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 52613e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveIn(unsigned Reg) const; 5276d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 5282ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 5292ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// corresponding live-in physical register. 5302ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng unsigned getLiveInPhysReg(unsigned VReg) const; 5312ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 5323946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// getLiveInVirtReg - If PReg is a live-in physical register, return the 5333946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// corresponding live-in physical register. 5343946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng unsigned getLiveInVirtReg(unsigned PReg) const; 5353946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 53698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 53798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// into the given entry block. 53898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 53998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 54098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII); 54198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 542c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 543c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 544c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 545c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 546a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 547a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 548a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 549c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 550f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 5516c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 5521327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 553c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 554c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 555c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 556ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 557a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 558a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 559c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 560c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 561c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 5626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 5636c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 5647362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 5657362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 5667362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 5677362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 56890019479f9a3868d8be90564695097a61a725438Andrew Trick 569c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 570c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 57190019479f9a3868d8be90564695097a61a725438Andrew Trick 572c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 5736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 5746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 575c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 5766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 5776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 57890019479f9a3868d8be90564695097a61a725438Andrew Trick 5796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 5806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 58190019479f9a3868d8be90564695097a61a725438Andrew Trick 5826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 583c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 5846c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 585fdd6484b41ef0fa7eb8c995fb34b728b193c6258Jakob Stoklund Olesen Op = getNextOperandForReg(Op); 58690019479f9a3868d8be90564695097a61a725438Andrew Trick 587c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // All defs come before the uses, so stop def_iterator early. 588c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (!ReturnUses) { 589c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (Op) { 590c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen if (Op->isUse()) 591c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Op = 0; 592c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen else 593c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen assert(!Op->isDebug() && "Can't have debug defs"); 594c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } 595c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } else { 596c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen // If this is an operand we don't care about, skip it. 597c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen while (Op && ((!ReturnDefs && Op->isDef()) || 598c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen (SkipDebug && Op->isDebug()))) 599c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen Op = getNextOperandForReg(Op); 600c7908037d87c8f6866b872e9f6b5a7fffae5b63eJakob Stoklund Olesen } 60190019479f9a3868d8be90564695097a61a725438Andrew Trick 6026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 6036c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 604c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 605c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 6066c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 607914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 608914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// skipInstruction - move forward until reaching a different instruction. 609914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// Return the skipped instruction that is no longer pointed to, or NULL if 610914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// already pointing to end(). 611914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *skipInstruction() { 612914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen if (!Op) return 0; 613914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *MI = Op->getParent(); 614914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen do ++*this; 615914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen while (Op && Op->getParent() == MI); 616914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen return MI; 617914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen } 618914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 61966c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen MachineInstr *skipBundle() { 62066c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen if (!Op) return 0; 62166c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen MachineInstr *MI = getBundleStart(Op->getParent()); 62266c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen do ++*this; 62366c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen while (Op && getBundleStart(Op->getParent()) == MI); 62466c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen return MI; 62566c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen } 62666c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen 627e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 6286c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 6296c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 6306c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 63190019479f9a3868d8be90564695097a61a725438Andrew Trick 632e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 633e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 634e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 635e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 636e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 637e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 63890019479f9a3868d8be90564695097a61a725438Andrew Trick 639e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 640e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 641e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 642e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 643e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 64490019479f9a3868d8be90564695097a61a725438Andrew Trick 645e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 646e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 647e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 648e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 6496c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 65090019479f9a3868d8be90564695097a61a725438Andrew Trick 65184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 65284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 65384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 65484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 65584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 656