MachineRegisterInfo.h revision 0492a8c530df6c7b2ebcfa91fed930c1a1bf664d
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1866c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen#include "llvm/CodeGen/MachineInstrBundle.h" 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 20994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen#include "llvm/ADT/IndexedMap.h" 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2490019479f9a3868d8be90564695097a61a725438Andrew Trick 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 271213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 29e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterInfo *const TRI; 30e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 3173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// IsSSA - True when the machine function is in SSA form and virtual 3273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// registers have a single def. 3373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool IsSSA; 3473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 35aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// TracksLiveness - True while register liveness is being tracked accurately. 36aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// Basic block live-in lists, kill flags, and implicit defs may not be 37aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// accurate when after this flag is cleared. 38aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen bool TracksLiveness; 39aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen 40994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen /// VRegInfo - Information we keep for each virtual register. 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 4362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 44994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 45994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VirtReg2IndexFunctor> VRegInfo; 4611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 4790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 48358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 49358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 50358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 51358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 52358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 5390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 54994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 5590019479f9a3868d8be90564695097a61a725438Andrew Trick 5662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 5762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 5890019479f9a3868d8be90564695097a61a725438Andrew Trick MachineOperand **PhysRegUseDefLists; 5990019479f9a3868d8be90564695097a61a725438Andrew Trick 6084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 6184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 6384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 6484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 65d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// This vector only has bits set for registers explicitly used, not their 66d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// aliases. 6784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 68d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 69d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// UsedPhysRegMask - Additional used physregs, but including aliases. 70d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen BitVector UsedPhysRegMask; 71d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 72d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// ReservedRegs - This is a bit vector of reserved registers. The target 73d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// may change its mind about which registers should be reserved. This 74d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// vector is the frozen set of reserved registers when register allocation 75d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// started. 76d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen BitVector ReservedRegs; 77d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 78c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// AllocatableRegs - From TRI->getAllocatableSet. 79c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen mutable BitVector AllocatableRegs; 80c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 8184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 8284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 8384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 8484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 8584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 8684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 8784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 8890019479f9a3868d8be90564695097a61a725438Andrew Trick 8962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 9062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 9184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 926f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 9362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 9473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 9573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 9673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // Function State 9773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 9873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 9973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // isSSA - Returns true when the machine function is in SSA form. Early 10073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // passes require the machine function to be in SSA form where every virtual 10173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register has a single defining instruction. 10273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // 10373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // The TwoAddressInstructionPass and PHIElimination passes take the machine 10473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // function out of SSA form when they introduce multiple defs per virtual 10573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register. 10673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool isSSA() const { return IsSSA; } 10773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 10873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // leaveSSA - Indicates that the machine function is no longer in SSA form. 10973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen void leaveSSA() { IsSSA = false; } 11073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 111aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// tracksLiveness - Returns true when tracking register liveness accurately. 112aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// 113aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// While this flag is true, register liveness information in basic block 114aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// live-in lists and machine instruction operands is accurate. This means it 115aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// can be used to change the code in ways that affect the values in 116aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// registers, for example by the register scavenger. 117aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// 118aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// When this flag is false, liveness is no longer reliable. 119aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen bool tracksLiveness() const { return TracksLiveness; } 120aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen 121aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// invalidateLiveness - Indicates that register liveness is no longer being 122aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// tracked accurately. 123aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// 124aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// This should be called by late passes that invalidate the liveness 125aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen /// information. 126aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen void invalidateLiveness() { TracksLiveness = false; } 127aba6559370c3d453588103fb667ffa3b11b76652Jakob Stoklund Olesen 1286c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 1296c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 1306c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 1316c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 1326c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 1336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 1346c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 135a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 136c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 137c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 138c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 139c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 140a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 1416c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 1426c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 1436c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1446c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 145c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 14600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 14700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 14800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 14900ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 150c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 151c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// of the specified register, skipping those marked as Debug. 152c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 153c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 154c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 155c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 156c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 157c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 158c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_empty - Return true if the only instructions using or defining 159c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// Reg are Debug instructions. 160c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen bool reg_nodbg_empty(unsigned RegNo) const { 161c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 162c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 163c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 164c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 165a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 166c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 167c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 168c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 169c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 170c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 17100ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 17200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 17300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 17400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 1750492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick /// hasOneDef - Return true if there is exactly one instruction defining the 1760492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick /// specified register. 1770492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick bool hasOneDef(unsigned RegNo) const { 1780492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick def_iterator DI = def_begin(RegNo); 1790492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick if (DI == def_end()) 1800492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick return false; 1810492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick return ++DI == def_end(); 1820492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick } 1830492a8c530df6c7b2ebcfa91fed930c1a1bf664dAndrew Trick 184c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 185a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 186c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 187c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 188c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 189c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 19090019479f9a3868d8be90564695097a61a725438Andrew Trick 191ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 192ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 193ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 194ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1951423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneUse - Return true if there is exactly one instruction using the 1961423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// specified register. 197269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick bool hasOneUse(unsigned RegNo) const { 198269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick use_iterator UI = use_begin(RegNo); 199269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick if (UI == use_end()) 200269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick return false; 201269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick return ++UI == use_end(); 202269120cd9b45b24665433ea28eb7d092c138ca76Andrew Trick } 2031423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 204a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 205a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 206a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 207a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 208a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 209a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 210a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 21190019479f9a3868d8be90564695097a61a725438Andrew Trick 212a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 213a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 214a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 215a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 216a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 217a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 2181423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 2191423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// instruction using the specified register. 2201423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneNonDBGUse(unsigned RegNo) const; 2211423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 222e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 223e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 224e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 2254007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 2264007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// Note that it is usually necessary to first constrain ToReg's register 2274007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// class to match the FromReg constraints using: 2284007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 2294007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// constrainRegClass(ToReg, getRegClass(FromReg)) 2304007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 2314007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// That function will return NULL if the virtual registers have incompatible 2324007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// constraints. 233e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 23490019479f9a3868d8be90564695097a61a725438Andrew Trick 23562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 23662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 23762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 238c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 239c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 240c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 24162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 24290019479f9a3868d8be90564695097a61a725438Andrew Trick 2436c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 244c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 245c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 246c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 2476c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2481eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 2491eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 2501eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 2511eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 2521eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 25349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 25454d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren /// getUniqueVRegDef - Return the unique machine instr that defines the 25554d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren /// specified virtual register or null if none is found. If there are 25654d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren /// multiple definitions or no definition, return null. 25754d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren MachineInstr *getUniqueVRegDef(unsigned Reg) const; 25854d69668b22b8c37aa6e45f14445f3988cc430d4Manman Ren 25949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clearKillFlags - Iterate over all the uses of the given register and 26049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clear the kill flag from the MachineOperand. This function is used by 26149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// optimization passes which extend register lifetimes and need only 26249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// preserve conservative kill flag information. 26349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman void clearKillFlags(unsigned Reg) const; 26490019479f9a3868d8be90564695097a61a725438Andrew Trick 2651eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2661eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 2671eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 268c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 269c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 270c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// throughout the function. It is safe to move instructions that read such 271c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen /// a physreg. 272c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 273c035c940a656f34a58ebe22fcc5f9b2a7d8e97fbJakob Stoklund Olesen 27484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 27584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 27684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 27790019479f9a3868d8be90564695097a61a725438Andrew Trick 27884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 27911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 2801eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 28162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 28284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 283bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 284bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 28511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 28633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 28711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 288bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// constrainRegClass - Constrain the register class of the specified virtual 28991fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// register to be a common subclass of RC and the current register class, 29091fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// but only if the new class has at least MinNumRegs registers. Return the 29191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// new register class, or NULL if no such class exists. 292bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// This should only be used when the constraint is known to be trivial, like 293bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 2946d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 295bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *constrainRegClass(unsigned Reg, 29691fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 29791fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs = 0); 298bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 2996d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// recomputeRegClass - Try to find a legal super-class of Reg's register 3006d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// class that still satisfies the constraints from the instructions using 3016d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// Reg. Returns true if Reg was upgraded. 3026d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 3036d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// This method can be used after constraints have been removed from a 3046d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// virtual register, for example after removing instructions or splitting 3056d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// the live range. 3066d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 3076d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen bool recomputeRegClass(unsigned Reg, const TargetMachine&); 3086d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 30984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 31084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 31184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 3122e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 31384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 314b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// getNumVirtRegs - Return the number of virtual registers created. 315b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// 316b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen unsigned getNumVirtRegs() const { return VRegInfo.size(); } 317b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 31819273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 31919273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick void clearVirtRegs(); 32019273aec441411b4d571fdb87c6daa0fbe7a33a0Andrew Trick 32190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 32290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 323358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 32490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 32590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 32690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 32790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 32890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 32990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 330358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 33190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 33290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 33390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 33490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 33551458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 33651458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// standard simple hint (Type == 0) is not set. 33751458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen unsigned getSimpleHint(unsigned Reg) const { 33851458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 33951458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen return Hint.first ? 0 : Hint.second; 34051458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen } 34151458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 34251458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 34384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 34484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 34584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 34690019479f9a3868d8be90564695097a61a725438Andrew Trick 34784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 34884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 349d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen bool isPhysRegUsed(unsigned Reg) const { 350d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen return UsedPhysRegs.test(Reg) || UsedPhysRegMask.test(Reg); 351d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen } 352a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen 353a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register 354a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen /// is used in this function. 355a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen bool isPhysRegOrOverlapUsed(unsigned Reg) const { 356d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen if (UsedPhysRegMask.test(Reg)) 357d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen return true; 358396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 359d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen if (UsedPhysRegs.test(*AI)) 360a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen return true; 361a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen return false; 362a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen } 363a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen 36484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 36584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 366d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); } 36782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 36882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// addPhysRegsUsed - Mark the specified registers used in this function. 36982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// This should only be called during and after register allocation. 37082b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 37182b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 372d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 373d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen /// This corresponds to the bit mask attached to register mask operands. 374d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 375d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.setBitsNotInMask(RegMask); 376d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen } 377d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen 37884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 37984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 380d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen void setPhysRegUnused(unsigned Reg) { 381d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegs.reset(Reg); 382d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen UsedPhysRegMask.reset(Reg); 383d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5Jakob Stoklund Olesen } 38484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 385d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 386d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 387d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // Reserved Register Info 388d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 389d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // 390d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // The set of reserved registers must be invariant during register 391d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // allocation. For example, the target cannot suddenly decide it needs a 392d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // frame pointer when the register allocator has already used the frame 393d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // pointer register for something else. 394d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // 395d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // These methods can be used by target hooks like hasFP() to avoid changing 396d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // the reserved register set during register allocation. 397d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 398d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// freezeReservedRegs - Called by the register allocator to freeze the set 399d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// of reserved registers before allocation begins. 400d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen void freezeReservedRegs(const MachineFunction&); 401d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 402d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 403d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// to ensure the set of reserved registers stays constant. 404d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen bool reservedRegsFrozen() const { 405d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen return !ReservedRegs.empty(); 406d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen } 407d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 408d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// canReserveReg - Returns true if PhysReg can be used as a reserved 409d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// register. Any register can be reserved before freezeReservedRegs() is 410d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// called. 411d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen bool canReserveReg(unsigned PhysReg) const { 412d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 413d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen } 414d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 415d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 41684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 41784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 41884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 41990019479f9a3868d8be90564695097a61a725438Andrew Trick 42084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 42184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 42284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 42384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 42484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 42584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 42690019479f9a3868d8be90564695097a61a725438Andrew Trick 42784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 42884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 42984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 43084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 43184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 43284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 43384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 43484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 43584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 43684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 43784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 4386d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 43913e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveIn(unsigned Reg) const; 44013e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveOut(unsigned Reg) const; 4416d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 4422ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 4432ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// corresponding live-in physical register. 4442ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng unsigned getLiveInPhysReg(unsigned VReg) const; 4452ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 4463946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// getLiveInVirtReg - If PReg is a live-in physical register, return the 4473946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// corresponding live-in physical register. 4483946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng unsigned getLiveInVirtReg(unsigned PReg) const; 4493946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 45098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 45198708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// into the given entry block. 45298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 45398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 45498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII); 45598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 45662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 45762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 45890019479f9a3868d8be90564695097a61a725438Andrew Trick 4596c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 460c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 461c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 462c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 463c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 464a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 465a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 466a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 467c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 468f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 4696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 4701327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 471c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 472c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 473c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 474ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 475a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 476a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 477c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 478c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 479c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 4806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 4816c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 4827362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 4837362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 4847362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 4857362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 48690019479f9a3868d8be90564695097a61a725438Andrew Trick 487c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 488c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 48990019479f9a3868d8be90564695097a61a725438Andrew Trick 490c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 4916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 4926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 493c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 4946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 4956c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 49690019479f9a3868d8be90564695097a61a725438Andrew Trick 4976c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 4986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 49990019479f9a3868d8be90564695097a61a725438Andrew Trick 5006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 501c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 5026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 5036c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 50490019479f9a3868d8be90564695097a61a725438Andrew Trick 505c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 50690019479f9a3868d8be90564695097a61a725438Andrew Trick while (Op && ((!ReturnUses && Op->isUse()) || 507a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && Op->isDef()) || 508a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && Op->isDebug()))) 509c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 51090019479f9a3868d8be90564695097a61a725438Andrew Trick 5116c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 5126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 513c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 514c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 5156c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 516914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 517914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// skipInstruction - move forward until reaching a different instruction. 518914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// Return the skipped instruction that is no longer pointed to, or NULL if 519914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// already pointing to end(). 520914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *skipInstruction() { 521914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen if (!Op) return 0; 522914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *MI = Op->getParent(); 523914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen do ++*this; 524914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen while (Op && Op->getParent() == MI); 525914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen return MI; 526914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen } 527914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 52866c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen MachineInstr *skipBundle() { 52966c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen if (!Op) return 0; 53066c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen MachineInstr *MI = getBundleStart(Op->getParent()); 53166c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen do ++*this; 53266c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen while (Op && getBundleStart(Op->getParent()) == MI); 53366c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen return MI; 53466c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen } 53566c994c2dbd1a76418fdd0acb138aa029538ffe5Jakob Stoklund Olesen 536e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 5376c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 5386c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 5396c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 54090019479f9a3868d8be90564695097a61a725438Andrew Trick 541e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 542e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 543e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 544e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 545e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 546e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 54790019479f9a3868d8be90564695097a61a725438Andrew Trick 548e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 549e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 550e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 551e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 552e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 55390019479f9a3868d8be90564695097a61a725438Andrew Trick 554e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 555e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 556e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 557e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 5586c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 55990019479f9a3868d8be90564695097a61a725438Andrew Trick 56084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 56184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 56284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 56384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 56484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 565