MachineRegisterInfo.h revision 238bf5ada19ee411c1decff68e140966f7baf479
1a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// 3a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// The LLVM Compiler Infrastructure 4a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// 5a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// License. See LICENSE.TXT for details. 7a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// 85d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)//===----------------------------------------------------------------------===// 95d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)// 10a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// This file defines the MachineRegisterInfo class. 11a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)// 12a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)//===----------------------------------------------------------------------===// 13a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 14a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles)#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1603b57e008b61dfcb1fbad3aea950ae0e001748b0Torne (Richard Coles) 17a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#include "llvm/ADT/BitVector.h" 18a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#include "llvm/ADT/IndexedMap.h" 19a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#include "llvm/CodeGen/MachineInstrBundle.h" 20a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#include "llvm/Target/TargetMachine.h" 21a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#include "llvm/Target/TargetRegisterInfo.h" 22a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)#include <vector> 23a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 24a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)namespace llvm { 25a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)class PSetIterator; 26a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 27a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)/// MachineRegisterInfo - Keep track of information for virtual and physical 28ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch/// registers, including vreg register classes, use/def chains for registers, 29a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)/// etc. 30a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)class MachineRegisterInfo { 31a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)public: 32a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) class Delegate { 33a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) public: 34a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) virtual void MRI_NoteNewVirtualRegister(unsigned Reg) {} 35a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 36a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) virtual ~Delegate() {} 37a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) }; 38a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 39a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)private: 40a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) const TargetMachine &TM; 41a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) Delegate *TheDelegate; 42a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 43a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// IsSSA - True when the machine function is in SSA form and virtual 44a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// registers have a single def. 45a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool IsSSA; 46a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 47a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// TracksLiveness - True while register liveness is being tracked accurately. 48a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Basic block live-in lists, kill flags, and implicit defs may not be 49116680a4aac90f2aa7413d9095a592090648e557Ben Murdoch /// accurate when after this flag is cleared. 50a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool TracksLiveness; 51a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 52a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// VRegInfo - Information we keep for each virtual register. 53a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 54a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Each element in this list contains the register class of the vreg and the 55a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// start of the use/def list for the register. 56a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 57a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) VirtReg2IndexFunctor> VRegInfo; 58a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 59a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// RegAllocHints - This vector records register allocation hints for virtual 60a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// registers. For each virtual register, it keeps a register and hint type 61a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// pair making up the allocation hint. Hint type is target specific except 62a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// for the value 0 which means the second value of the pair is the preferred 63a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// register for allocation. For example, if the hint is <0, 1024>, it means 64a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// the allocator should prefer the physical register allocated to the virtual 65a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// register of the hint. 66a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 67a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 68a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// PhysRegUseDefLists - This is an array of the head of the use/def list for 69a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// physical registers. 70a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) MachineOperand **PhysRegUseDefLists; 71a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 72a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// getRegUseDefListHead - Return the head pointer for the register use/def 73a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// list for the specified virtual or physical register. 74a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 75a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) if (TargetRegisterInfo::isVirtualRegister(RegNo)) 76a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return VRegInfo[RegNo].second; 77a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return PhysRegUseDefLists[RegNo]; 78a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) } 79ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch 80a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 81a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) if (TargetRegisterInfo::isVirtualRegister(RegNo)) 82a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return VRegInfo[RegNo].second; 83a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return PhysRegUseDefLists[RegNo]; 84a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 85a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 86a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Get the next element in the use-def chain. 87a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 88a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) assert(MO && MO->isReg() && "This is not a register operand!"); 89a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return MO->Contents.Reg.Next; 90a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 91a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 92a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// UsedRegUnits - This is a bit vector that is computed and set by the 9368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// register allocator, and must be kept up to date by passes that run after 9468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// register allocation (though most don't modify this). This is used 95a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// so that the code generator knows which callee save registers to save and 96a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// for other target specific uses. 97ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch /// This vector has bits set for register units that are modified in the 98a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// current function. It doesn't include registers clobbered by function 99a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// calls with register mask operands. 100a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) BitVector UsedRegUnits; 101a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 102a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// UsedPhysRegMask - Additional used physregs including aliases. 103a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// This bit vector represents all the registers clobbered by function calls. 104a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// It can model things that UsedRegUnits can't, such as function calls that 105a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// clobber ymm7 but preserve the low half in xmm7. 106a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) BitVector UsedPhysRegMask; 107a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 108a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// ReservedRegs - This is a bit vector of reserved registers. The target 109a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// may change its mind about which registers should be reserved. This 110a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// vector is the frozen set of reserved registers when register allocation 111a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// started. 112a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) BitVector ReservedRegs; 113a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 114a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Keep track of the physical registers that are live in to the function. 115a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// Live in values are typically arguments in registers. LiveIn values are 116a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// allowed to have virtual registers associated with them, stored in the 117a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// second element. 118a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) std::vector<std::pair<unsigned, unsigned> > LiveIns; 119a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 120a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 121a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 122a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)public: 123a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) explicit MachineRegisterInfo(const TargetMachine &TM); 124a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) ~MachineRegisterInfo(); 125a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 126a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) const TargetRegisterInfo *getTargetRegisterInfo() const { 127a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return TM.getRegisterInfo(); 128a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) } 129a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 130a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) void resetDelegate(Delegate *delegate) { 13168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) // Ensure another delegate does not take over unless the current 13268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) // delegate first unattaches itself. If we ever need to multicast 133a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // notifications, we will need to change to using a list. 134a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) assert(TheDelegate == delegate && 135a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) "Only the current delegate can perform reset!"); 1365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) TheDelegate = 0; 1375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 1385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) void setDelegate(Delegate *delegate) { 1405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) assert(delegate && !TheDelegate && 1415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) "Attempted to set delegate to null, or to change it without " 1425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) "first resetting it!"); 1435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) TheDelegate = delegate; 1455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 1465d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1475d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) //===--------------------------------------------------------------------===// 1485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Function State 1495d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) //===--------------------------------------------------------------------===// 1505d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 1515d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // isSSA - Returns true when the machine function is in SSA form. Early 1525d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // passes require the machine function to be in SSA form where every virtual 153a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // register has a single defining instruction. 154a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // 155a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // The TwoAddressInstructionPass and PHIElimination passes take the machine 156a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // function out of SSA form when they introduce multiple defs per virtual 157a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // register. 158a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool isSSA() const { return IsSSA; } 159a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 16068043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) // leaveSSA - Indicates that the machine function is no longer in SSA form. 16168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) void leaveSSA() { IsSSA = false; } 16268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 16368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// tracksLiveness - Returns true when tracking register liveness accurately. 16468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// 16568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// While this flag is true, register liveness information in basic block 166a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// live-in lists and machine instruction operands is accurate. This means it 167a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// can be used to change the code in ways that affect the values in 168a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// registers, for example by the register scavenger. 169a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 170a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// When this flag is false, liveness is no longer reliable. 171a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool tracksLiveness() const { return TracksLiveness; } 172a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 173a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// invalidateLiveness - Indicates that register liveness is no longer being 174a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// tracked accurately. 175a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 176a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// This should be called by late passes that invalidate the liveness 177a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// information. 178a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void invalidateLiveness() { TracksLiveness = false; } 179a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 180a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) //===--------------------------------------------------------------------===// 181ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch // Register Info 1825d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) //===--------------------------------------------------------------------===// 1835d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 184a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // Strictly for use by MachineInstr.cpp. 185a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void addRegOperandToUseList(MachineOperand *MO); 186a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 187ba5b9a6411cb1792fd21f0a078d7a25cd1ceec16Ben Murdoch // Strictly for use by MachineInstr.cpp. 188a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void removeRegOperandFromUseList(MachineOperand *MO); 189a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 190a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // Strictly for use by MachineInstr.cpp. 191a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); 192a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 193a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Verify the sanity of the use list for Reg. 194a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void verifyUseList(unsigned Reg) const; 195a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 196a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Verify the use list of all registers. 197a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void verifyUseLists() const; 198a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 199a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// reg_begin/reg_end - Provide iteration support to walk over all definitions 200a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// and uses of a register within the MachineFunction that corresponds to this 201a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// MachineRegisterInfo object. 202a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) template<bool Uses, bool Defs, bool SkipDebug> 203a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) class defusechain_iterator; 204a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 205a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) // Make it a friend so it can access getNextOperandForReg(). 206a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) template<bool, bool, bool> friend class defusechain_iterator; 207a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 208a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 209a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// register. 210a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) typedef defusechain_iterator<true,true,false> reg_iterator; 211a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) reg_iterator reg_begin(unsigned RegNo) const { 212a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) return reg_iterator(getRegUseDefListHead(RegNo)); 213a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 214a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) static reg_iterator reg_end() { return reg_iterator(0); } 215a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 216a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// reg_empty - Return true if there are no instructions using or defining the 217a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// specified register (it may be live-in). 218a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 219a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 220a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 221a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// of the specified register, skipping those marked as Debug. 222a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 223a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 224a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 225a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 226a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 227a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 228a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// reg_nodbg_empty - Return true if the only instructions using or defining 229a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// Reg are Debug instructions. 230a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool reg_nodbg_empty(unsigned RegNo) const { 231a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 232a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 233a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 234a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 2353551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) typedef defusechain_iterator<false,true,false> def_iterator; 2363551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) def_iterator def_begin(unsigned RegNo) const { 2373551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) return def_iterator(getRegUseDefListHead(RegNo)); 2383551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) } 2393551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) static def_iterator def_end() { return def_iterator(0); } 240a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 24168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// def_empty - Return true if there are no instructions defining the 242a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// specified register (it may be live-in). 243a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 244a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 245a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// hasOneDef - Return true if there is exactly one instruction defining the 246a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// specified register. 247a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool hasOneDef(unsigned RegNo) const { 248a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) def_iterator DI = def_begin(RegNo); 249a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) if (DI == def_end()) 250a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return false; 251a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return ++DI == def_end(); 252a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 253a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 254a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 255a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) typedef defusechain_iterator<true,false,false> use_iterator; 256a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) use_iterator use_begin(unsigned RegNo) const { 257a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return use_iterator(getRegUseDefListHead(RegNo)); 258a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) } 259a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) static use_iterator use_end() { return use_iterator(0); } 260a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 261a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// use_empty - Return true if there are no instructions using the specified 262a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// register. 263a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 26468043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 26568043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// hasOneUse - Return true if there is exactly one instruction using the 26668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// specified register. 26768043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) bool hasOneUse(unsigned RegNo) const { 268a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) use_iterator UI = use_begin(RegNo); 269a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) if (UI == use_end()) 270a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return false; 271a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return ++UI == use_end(); 272a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) } 273a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 274a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 275a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// specified register, skipping those marked as Debug. 276a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 277a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 278a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 279a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) } 28058537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 28158537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 28258537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) /// use_nodbg_empty - Return true if there are no non-Debug instructions 283a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// using the specified register. 28458537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) bool use_nodbg_empty(unsigned RegNo) const { 28558537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) return use_nodbg_begin(RegNo) == use_nodbg_end(); 28658537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) } 28758537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) 288a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 289a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// instruction using the specified register. 290a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool hasOneNonDBGUse(unsigned RegNo) const; 29168043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) 292a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// replaceRegWith - Replace all instances of FromReg with ToReg in the 293a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 294a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// except that it also changes any definitions of the register as well. 295a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 2965d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// Note that it is usually necessary to first constrain ToReg's register 2975d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// class to match the FromReg constraints using: 2985d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 2995d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// constrainRegClass(ToReg, getRegClass(FromReg)) 3005d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 3015d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// That function will return NULL if the virtual registers have incompatible 3025d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// constraints. 3035d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) void replaceRegWith(unsigned FromReg, unsigned ToReg); 3045d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3055d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// getVRegDef - Return the machine instr that defines the specified virtual 3065d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// register or null if none is found. This assumes that the code is in SSA 3075d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// form, so there should only be one definition. 3085d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) MachineInstr *getVRegDef(unsigned Reg) const; 3095d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3105d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// getUniqueVRegDef - Return the unique machine instr that defines the 3115d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// specified virtual register or null if none is found. If there are 3125d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// multiple definitions or no definition, return null. 3135d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) MachineInstr *getUniqueVRegDef(unsigned Reg) const; 3145d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3155d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// clearKillFlags - Iterate over all the uses of the given register and 3165d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// clear the kill flag from the MachineOperand. This function is used by 3175d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// optimization passes which extend register lifetimes and need only 3185d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// preserve conservative kill flag information. 3195d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) void clearKillFlags(unsigned Reg) const; 3205d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3215d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#ifndef NDEBUG 3225d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) void dumpUses(unsigned RegNo) const; 3235d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles)#endif 3245d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3255d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 3265d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// throughout the function. It is safe to move instructions that read such 3275d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// a physreg. 328a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 3295d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3305d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// Get an iterator over the pressure sets affected by the given physical or 3315d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// virtual register. If RegUnit is physical, it must be a register unit (from 3325d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// MCRegUnitIterator). 3335d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) PSetIterator getPressureSets(unsigned RegUnit) const; 3345d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3355d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) //===--------------------------------------------------------------------===// 3365d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) // Virtual Register Info 3375d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) //===--------------------------------------------------------------------===// 3385d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3395d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// getRegClass - Return the register class of the specified virtual register. 3405d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// 3415d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) const TargetRegisterClass *getRegClass(unsigned Reg) const { 3425d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) return VRegInfo[Reg].first; 3435d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) } 3445d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 3455d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) /// setRegClass - Set the register class of the specified virtual register. 346a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 347a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 3485d1f7b1de12d16ceb2c938c56701a3e8bfa558f7Torne (Richard Coles) 349a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// constrainRegClass - Constrain the register class of the specified virtual 350a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// register to be a common subclass of RC and the current register class, 351a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// but only if the new class has at least MinNumRegs registers. Return the 352a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// new register class, or NULL if no such class exists. 353a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// This should only be used when the constraint is known to be trivial, like 354a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 355a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 356a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) const TargetRegisterClass *constrainRegClass(unsigned Reg, 357a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) const TargetRegisterClass *RC, 358a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) unsigned MinNumRegs = 0); 359a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 360a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// recomputeRegClass - Try to find a legal super-class of Reg's register 361a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// class that still satisfies the constraints from the instructions using 362a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// Reg. Returns true if Reg was upgraded. 363a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// 364a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// This method can be used after constraints have been removed from a 365a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// virtual register, for example after removing instructions or splitting 366a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// the live range. 367a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// 36858537e28ecd584eab876aee8be7156509866d23aTorne (Richard Coles) bool recomputeRegClass(unsigned Reg, const TargetMachine&); 369a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 370a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) /// createVirtualRegister - Create and return a new virtual register in the 371 /// function with the specified register class. 372 /// 373 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 374 375 /// getNumVirtRegs - Return the number of virtual registers created. 376 /// 377 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 378 379 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 380 void clearVirtRegs(); 381 382 /// setRegAllocationHint - Specify a register allocation hint for the 383 /// specified virtual register. 384 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 385 RegAllocHints[Reg].first = Type; 386 RegAllocHints[Reg].second = PrefReg; 387 } 388 389 /// getRegAllocationHint - Return the register allocation hint for the 390 /// specified virtual register. 391 std::pair<unsigned, unsigned> 392 getRegAllocationHint(unsigned Reg) const { 393 return RegAllocHints[Reg]; 394 } 395 396 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 397 /// standard simple hint (Type == 0) is not set. 398 unsigned getSimpleHint(unsigned Reg) const { 399 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 400 return Hint.first ? 0 : Hint.second; 401 } 402 403 404 //===--------------------------------------------------------------------===// 405 // Physical Register Use Info 406 //===--------------------------------------------------------------------===// 407 408 /// isPhysRegUsed - Return true if the specified register is used in this 409 /// function. Also check for clobbered aliases and registers clobbered by 410 /// function calls with register mask operands. 411 /// 412 /// This only works after register allocation. It is primarily used by 413 /// PrologEpilogInserter to determine which callee-saved registers need 414 /// spilling. 415 bool isPhysRegUsed(unsigned Reg) const { 416 if (UsedPhysRegMask.test(Reg)) 417 return true; 418 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 419 Units.isValid(); ++Units) 420 if (UsedRegUnits.test(*Units)) 421 return true; 422 return false; 423 } 424 425 /// Mark the specified register unit as used in this function. 426 /// This should only be called during and after register allocation. 427 void setRegUnitUsed(unsigned RegUnit) { 428 UsedRegUnits.set(RegUnit); 429 } 430 431 /// setPhysRegUsed - Mark the specified register used in this function. 432 /// This should only be called during and after register allocation. 433 void setPhysRegUsed(unsigned Reg) { 434 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 435 Units.isValid(); ++Units) 436 UsedRegUnits.set(*Units); 437 } 438 439 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 440 /// This corresponds to the bit mask attached to register mask operands. 441 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 442 UsedPhysRegMask.setBitsNotInMask(RegMask); 443 } 444 445 /// setPhysRegUnused - Mark the specified register unused in this function. 446 /// This should only be called during and after register allocation. 447 void setPhysRegUnused(unsigned Reg) { 448 UsedPhysRegMask.reset(Reg); 449 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo()); 450 Units.isValid(); ++Units) 451 UsedRegUnits.reset(*Units); 452 } 453 454 455 //===--------------------------------------------------------------------===// 456 // Reserved Register Info 457 //===--------------------------------------------------------------------===// 458 // 459 // The set of reserved registers must be invariant during register 460 // allocation. For example, the target cannot suddenly decide it needs a 461 // frame pointer when the register allocator has already used the frame 462 // pointer register for something else. 463 // 464 // These methods can be used by target hooks like hasFP() to avoid changing 465 // the reserved register set during register allocation. 466 467 /// freezeReservedRegs - Called by the register allocator to freeze the set 468 /// of reserved registers before allocation begins. 469 void freezeReservedRegs(const MachineFunction&); 470 471 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 472 /// to ensure the set of reserved registers stays constant. 473 bool reservedRegsFrozen() const { 474 return !ReservedRegs.empty(); 475 } 476 477 /// canReserveReg - Returns true if PhysReg can be used as a reserved 478 /// register. Any register can be reserved before freezeReservedRegs() is 479 /// called. 480 bool canReserveReg(unsigned PhysReg) const { 481 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 482 } 483 484 /// getReservedRegs - Returns a reference to the frozen set of reserved 485 /// registers. This method should always be preferred to calling 486 /// TRI::getReservedRegs() when possible. 487 const BitVector &getReservedRegs() const { 488 assert(reservedRegsFrozen() && 489 "Reserved registers haven't been frozen yet. " 490 "Use TRI::getReservedRegs()."); 491 return ReservedRegs; 492 } 493 494 /// isReserved - Returns true when PhysReg is a reserved register. 495 /// 496 /// Reserved registers may belong to an allocatable register class, but the 497 /// target has explicitly requested that they are not used. 498 /// 499 bool isReserved(unsigned PhysReg) const { 500 return getReservedRegs().test(PhysReg); 501 } 502 503 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 504 /// register class and it hasn't been reserved. 505 /// 506 /// Allocatable registers may show up in the allocation order of some virtual 507 /// register, so a register allocator needs to track its liveness and 508 /// availability. 509 bool isAllocatable(unsigned PhysReg) const { 510 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) && 511 !isReserved(PhysReg); 512 } 513 514 //===--------------------------------------------------------------------===// 515 // LiveIn Management 516 //===--------------------------------------------------------------------===// 517 518 /// addLiveIn - Add the specified register as a live-in. Note that it 519 /// is an error to add the same register to the same set more than once. 520 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 521 LiveIns.push_back(std::make_pair(Reg, vreg)); 522 } 523 524 // Iteration support for the live-ins set. It's kept in sorted order 525 // by register number. 526 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 527 livein_iterator; 528 livein_iterator livein_begin() const { return LiveIns.begin(); } 529 livein_iterator livein_end() const { return LiveIns.end(); } 530 bool livein_empty() const { return LiveIns.empty(); } 531 532 bool isLiveIn(unsigned Reg) const; 533 534 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 535 /// corresponding live-in physical register. 536 unsigned getLiveInPhysReg(unsigned VReg) const; 537 538 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 539 /// corresponding live-in physical register. 540 unsigned getLiveInVirtReg(unsigned PReg) const; 541 542 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 543 /// into the given entry block. 544 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 545 const TargetRegisterInfo &TRI, 546 const TargetInstrInfo &TII); 547 548 /// defusechain_iterator - This class provides iterator support for machine 549 /// operands in the function that use or define a specific register. If 550 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 551 /// returns defs. If neither are true then you are silly and it always 552 /// returns end(). If SkipDebug is true it skips uses marked Debug 553 /// when incrementing. 554 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 555 class defusechain_iterator 556 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 557 MachineOperand *Op; 558 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 559 // If the first node isn't one we're interested in, advance to one that 560 // we are interested in. 561 if (op) { 562 if ((!ReturnUses && op->isUse()) || 563 (!ReturnDefs && op->isDef()) || 564 (SkipDebug && op->isDebug())) 565 ++*this; 566 } 567 } 568 friend class MachineRegisterInfo; 569 public: 570 typedef std::iterator<std::forward_iterator_tag, 571 MachineInstr, ptrdiff_t>::reference reference; 572 typedef std::iterator<std::forward_iterator_tag, 573 MachineInstr, ptrdiff_t>::pointer pointer; 574 575 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 576 defusechain_iterator() : Op(0) {} 577 578 bool operator==(const defusechain_iterator &x) const { 579 return Op == x.Op; 580 } 581 bool operator!=(const defusechain_iterator &x) const { 582 return !operator==(x); 583 } 584 585 /// atEnd - return true if this iterator is equal to reg_end() on the value. 586 bool atEnd() const { return Op == 0; } 587 588 // Iterator traversal: forward iteration only 589 defusechain_iterator &operator++() { // Preincrement 590 assert(Op && "Cannot increment end iterator!"); 591 Op = getNextOperandForReg(Op); 592 593 // All defs come before the uses, so stop def_iterator early. 594 if (!ReturnUses) { 595 if (Op) { 596 if (Op->isUse()) 597 Op = 0; 598 else 599 assert(!Op->isDebug() && "Can't have debug defs"); 600 } 601 } else { 602 // If this is an operand we don't care about, skip it. 603 while (Op && ((!ReturnDefs && Op->isDef()) || 604 (SkipDebug && Op->isDebug()))) 605 Op = getNextOperandForReg(Op); 606 } 607 608 return *this; 609 } 610 defusechain_iterator operator++(int) { // Postincrement 611 defusechain_iterator tmp = *this; ++*this; return tmp; 612 } 613 614 /// skipInstruction - move forward until reaching a different instruction. 615 /// Return the skipped instruction that is no longer pointed to, or NULL if 616 /// already pointing to end(). 617 MachineInstr *skipInstruction() { 618 if (!Op) return 0; 619 MachineInstr *MI = Op->getParent(); 620 do ++*this; 621 while (Op && Op->getParent() == MI); 622 return MI; 623 } 624 625 MachineInstr *skipBundle() { 626 if (!Op) return 0; 627 MachineInstr *MI = getBundleStart(Op->getParent()); 628 do ++*this; 629 while (Op && getBundleStart(Op->getParent()) == MI); 630 return MI; 631 } 632 633 MachineOperand &getOperand() const { 634 assert(Op && "Cannot dereference end iterator!"); 635 return *Op; 636 } 637 638 /// getOperandNo - Return the operand # of this MachineOperand in its 639 /// MachineInstr. 640 unsigned getOperandNo() const { 641 assert(Op && "Cannot dereference end iterator!"); 642 return Op - &Op->getParent()->getOperand(0); 643 } 644 645 // Retrieve a reference to the current operand. 646 MachineInstr &operator*() const { 647 assert(Op && "Cannot dereference end iterator!"); 648 return *Op->getParent(); 649 } 650 651 MachineInstr *operator->() const { 652 assert(Op && "Cannot dereference end iterator!"); 653 return Op->getParent(); 654 } 655 }; 656}; 657 658/// Iterate over the pressure sets affected by the given physical or virtual 659/// register. If Reg is physical, it must be a register unit (from 660/// MCRegUnitIterator). 661class PSetIterator { 662 const int *PSet; 663 unsigned Weight; 664public: 665 PSetIterator(): PSet(0), Weight(0) {} 666 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { 667 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); 668 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { 669 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); 670 PSet = TRI->getRegClassPressureSets(RC); 671 Weight = TRI->getRegClassWeight(RC).RegWeight; 672 } 673 else { 674 PSet = TRI->getRegUnitPressureSets(RegUnit); 675 Weight = TRI->getRegUnitWeight(RegUnit); 676 } 677 if (*PSet == -1) 678 PSet = 0; 679 } 680 bool isValid() const { return PSet; } 681 682 unsigned getWeight() const { return Weight; } 683 684 unsigned operator*() const { return *PSet; } 685 686 void operator++() { 687 assert(isValid() && "Invalid PSetIterator."); 688 ++PSet; 689 if (*PSet == -1) 690 PSet = 0; 691 } 692}; 693 694inline PSetIterator MachineRegisterInfo:: 695getPressureSets(unsigned RegUnit) const { 696 return PSetIterator(RegUnit, this); 697} 698 699} // End llvm namespace 700 701#endif 702