MachineRegisterInfo.h revision 6d1fd0b979cb88809ebb77a24f4da69e1d67606b
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 19994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen#include "llvm/ADT/IndexedMap.h" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// IsSSA - True when the machine function is in SSA form and virtual 2973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// registers have a single def. 3073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool IsSSA; 3173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 32994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen /// VRegInfo - Information we keep for each virtual register. 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 36994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 37994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VirtReg2IndexFunctor> VRegInfo; 3811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 3990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 40358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 41358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 42358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 43358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 44358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 4590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 46994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 4762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 4962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 5062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 5184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 6084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 6184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 6384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 6484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 6584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 6668e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel 6762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 706f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 7162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 7273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 7373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 7473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // Function State 7573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 7673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 7773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // isSSA - Returns true when the machine function is in SSA form. Early 7873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // passes require the machine function to be in SSA form where every virtual 7973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register has a single defining instruction. 8073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // 8173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // The TwoAddressInstructionPass and PHIElimination passes take the machine 8273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // function out of SSA form when they introduce multiple defs per virtual 8373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register. 8473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool isSSA() const { return IsSSA; } 8573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 8673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // leaveSSA - Indicates that the machine function is no longer in SSA form. 8773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen void leaveSSA() { IsSSA = false; } 8873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 936c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 956c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 96a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 97c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 98c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 99c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 100c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 101a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 1026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 1036c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 1046c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1056c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 106c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 10700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 10800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 10900ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 11000ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 111c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 112c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// of the specified register, skipping those marked as Debug. 113c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 114c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 115c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 116c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 117c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 118c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 119c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_empty - Return true if the only instructions using or defining 120c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// Reg are Debug instructions. 121c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen bool reg_nodbg_empty(unsigned RegNo) const { 122c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 123c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 124c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 125c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 126a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 127c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 128c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 129c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 130c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 131c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 13200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 13300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 13400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 13500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 136c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 137a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 138c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 139c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 140c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 141c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 142c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 143ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 144ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 145ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 146ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1471423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneUse - Return true if there is exactly one instruction using the 1481423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// specified register. 1491423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneUse(unsigned RegNo) const; 1501423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 151a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 152a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 153a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 154a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 155a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 156a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 157a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1586c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 159a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 160a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 161a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 162a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 163a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 164a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 1651423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 1661423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// instruction using the specified register. 1671423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneNonDBGUse(unsigned RegNo) const; 1681423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 169e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 170e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 171e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 172e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 173e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 17462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 17562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 17662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 177c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 178c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 179c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 18062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 18184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 183c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 184c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 185c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 1866c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1871eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1881eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1891eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1901eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1911eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 19249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 19349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clearKillFlags - Iterate over all the uses of the given register and 19449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clear the kill flag from the MachineOperand. This function is used by 19549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// optimization passes which extend register lifetimes and need only 19649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// preserve conservative kill flag information. 19749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman void clearKillFlags(unsigned Reg) const; 1981eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1991eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2001eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 2011eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 20284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 20484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 20584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 20684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 20784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 20811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 2091eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 21062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 21184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 212bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 213bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 21411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 21533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 21611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 217bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// constrainRegClass - Constrain the register class of the specified virtual 218bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// register to be a common subclass of RC and the current register class. 219bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// Return the new register class, or NULL if no such class exists. 220bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// This should only be used when the constraint is known to be trivial, like 221bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 2226d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 223bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *constrainRegClass(unsigned Reg, 224bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *RC); 225bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 2266d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// recomputeRegClass - Try to find a legal super-class of Reg's register 2276d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// class that still satisfies the constraints from the instructions using 2286d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// Reg. Returns true if Reg was upgraded. 2296d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 2306d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// This method can be used after constraints have been removed from a 2316d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// virtual register, for example after removing instructions or splitting 2326d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// the live range. 2336d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 2346d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen bool recomputeRegClass(unsigned Reg, const TargetMachine&); 2356d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 23684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 23784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 23884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 2392e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 24084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 241b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// getNumVirtRegs - Return the number of virtual registers created. 242b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// 243b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen unsigned getNumVirtRegs() const { return VRegInfo.size(); } 244b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 24590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 24690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 247358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 24890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 24990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 25090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 25190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 25290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 25390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 254358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 25590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 25690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 25790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 25890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 25951458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 26051458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// standard simple hint (Type == 0) is not set. 26151458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen unsigned getSimpleHint(unsigned Reg) const { 26251458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 26351458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen return Hint.first ? 0 : Hint.second; 26451458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen } 26551458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 26651458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 26784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 26884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 26984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 27084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 27184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 27284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 27384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 27484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 27584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 27684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 27784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 27882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 27982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// addPhysRegsUsed - Mark the specified registers used in this function. 28082b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// This should only be called during and after register allocation. 28182b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 28282b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 28384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 28484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 28584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 28682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 28782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 28882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// subregisters. That means that if R is used, so are all subregisters. 28982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void closePhysRegsUsed(const TargetRegisterInfo&); 29084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 29184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 29284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 29384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 29484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 29584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 29684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 29784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 29884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 29984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 30084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 30168e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel 30284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 30384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 30484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 30584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 30684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 30784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 30884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 30984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 31084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 31184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 31284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 3136d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 31413e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveIn(unsigned Reg) const; 31513e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveOut(unsigned Reg) const; 3166d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 3172ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 3182ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// corresponding live-in physical register. 3192ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng unsigned getLiveInPhysReg(unsigned VReg) const; 3202ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 3213946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// getLiveInVirtReg - If PReg is a live-in physical register, return the 3223946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// corresponding live-in physical register. 3233946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng unsigned getLiveInVirtReg(unsigned PReg) const; 3243946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 32598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 32698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// into the given entry block. 32798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 32898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 32998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII); 33098708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 33162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 33262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 3336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3346c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 335c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 336c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 337c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 338c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 339a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 340a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 341a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 342c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 343f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 3446c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 3451327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 346c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 347c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 348c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 349ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 350a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 351a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 352c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 353c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 354c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 3556c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 3566c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 3577362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 3587362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 3597362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 3607362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 3616c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 362c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 363c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 3646c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 365c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 3666c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 3676c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 368c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 3696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 3706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3716c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3726c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 3736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 3746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 376c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 3776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 3786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 379c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 380c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 381ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 382a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && Op->isDef()) || 383a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && Op->isDebug()))) 384c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 385c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 3866c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 3876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 388c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 389c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 3906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 391914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 392914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// skipInstruction - move forward until reaching a different instruction. 393914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// Return the skipped instruction that is no longer pointed to, or NULL if 394914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// already pointing to end(). 395914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *skipInstruction() { 396914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen if (!Op) return 0; 397914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *MI = Op->getParent(); 398914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen do ++*this; 399914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen while (Op && Op->getParent() == MI); 400914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen return MI; 401914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen } 402914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 403e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 4046c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 4056c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 4066c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 4076c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 408e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 409e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 410e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 411e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 412e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 413e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 414e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 415e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 416e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 417e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 418e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 419e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 420e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 421e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 422e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 423e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 424e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 4256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 4266c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 42784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 42884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 42984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 43084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 43184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 432