MachineRegisterInfo.h revision 73e7dced3892f2abb4344526147d4df0f62aee61
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/IndexedMap.h" 20#include <vector> 21 22namespace llvm { 23 24/// MachineRegisterInfo - Keep track of information for virtual and physical 25/// registers, including vreg register classes, use/def chains for registers, 26/// etc. 27class MachineRegisterInfo { 28 /// IsSSA - True when the machine function is in SSA form and virtual 29 /// registers have a single def. 30 bool IsSSA; 31 32 /// VRegInfo - Information we keep for each virtual register. 33 /// 34 /// Each element in this list contains the register class of the vreg and the 35 /// start of the use/def list for the register. 36 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 37 VirtReg2IndexFunctor> VRegInfo; 38 39 /// RegAllocHints - This vector records register allocation hints for virtual 40 /// registers. For each virtual register, it keeps a register and hint type 41 /// pair making up the allocation hint. Hint type is target specific except 42 /// for the value 0 which means the second value of the pair is the preferred 43 /// register for allocation. For example, if the hint is <0, 1024>, it means 44 /// the allocator should prefer the physical register allocated to the virtual 45 /// register of the hint. 46 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 47 48 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 49 /// physical registers. 50 MachineOperand **PhysRegUseDefLists; 51 52 /// UsedPhysRegs - This is a bit vector that is computed and set by the 53 /// register allocator, and must be kept up to date by passes that run after 54 /// register allocation (though most don't modify this). This is used 55 /// so that the code generator knows which callee save registers to save and 56 /// for other target specific uses. 57 BitVector UsedPhysRegs; 58 59 /// LiveIns/LiveOuts - Keep track of the physical registers that are 60 /// livein/liveout of the function. Live in values are typically arguments in 61 /// registers, live out values are typically return values in registers. 62 /// LiveIn values are allowed to have virtual registers associated with them, 63 /// stored in the second element. 64 std::vector<std::pair<unsigned, unsigned> > LiveIns; 65 std::vector<unsigned> LiveOuts; 66 67 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 68 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69public: 70 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 71 ~MachineRegisterInfo(); 72 73 //===--------------------------------------------------------------------===// 74 // Function State 75 //===--------------------------------------------------------------------===// 76 77 // isSSA - Returns true when the machine function is in SSA form. Early 78 // passes require the machine function to be in SSA form where every virtual 79 // register has a single defining instruction. 80 // 81 // The TwoAddressInstructionPass and PHIElimination passes take the machine 82 // function out of SSA form when they introduce multiple defs per virtual 83 // register. 84 bool isSSA() const { return IsSSA; } 85 86 // leaveSSA - Indicates that the machine function is no longer in SSA form. 87 void leaveSSA() { IsSSA = false; } 88 89 //===--------------------------------------------------------------------===// 90 // Register Info 91 //===--------------------------------------------------------------------===// 92 93 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 94 /// and uses of a register within the MachineFunction that corresponds to this 95 /// MachineRegisterInfo object. 96 template<bool Uses, bool Defs, bool SkipDebug> 97 class defusechain_iterator; 98 99 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 100 /// register. 101 typedef defusechain_iterator<true,true,false> reg_iterator; 102 reg_iterator reg_begin(unsigned RegNo) const { 103 return reg_iterator(getRegUseDefListHead(RegNo)); 104 } 105 static reg_iterator reg_end() { return reg_iterator(0); } 106 107 /// reg_empty - Return true if there are no instructions using or defining the 108 /// specified register (it may be live-in). 109 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 110 111 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 112 /// of the specified register, skipping those marked as Debug. 113 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 114 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 115 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 116 } 117 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 118 119 /// reg_nodbg_empty - Return true if the only instructions using or defining 120 /// Reg are Debug instructions. 121 bool reg_nodbg_empty(unsigned RegNo) const { 122 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 123 } 124 125 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 126 typedef defusechain_iterator<false,true,false> def_iterator; 127 def_iterator def_begin(unsigned RegNo) const { 128 return def_iterator(getRegUseDefListHead(RegNo)); 129 } 130 static def_iterator def_end() { return def_iterator(0); } 131 132 /// def_empty - Return true if there are no instructions defining the 133 /// specified register (it may be live-in). 134 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 135 136 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 137 typedef defusechain_iterator<true,false,false> use_iterator; 138 use_iterator use_begin(unsigned RegNo) const { 139 return use_iterator(getRegUseDefListHead(RegNo)); 140 } 141 static use_iterator use_end() { return use_iterator(0); } 142 143 /// use_empty - Return true if there are no instructions using the specified 144 /// register. 145 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 146 147 /// hasOneUse - Return true if there is exactly one instruction using the 148 /// specified register. 149 bool hasOneUse(unsigned RegNo) const; 150 151 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 152 /// specified register, skipping those marked as Debug. 153 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 154 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 155 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 156 } 157 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 158 159 /// use_nodbg_empty - Return true if there are no non-Debug instructions 160 /// using the specified register. 161 bool use_nodbg_empty(unsigned RegNo) const { 162 return use_nodbg_begin(RegNo) == use_nodbg_end(); 163 } 164 165 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 166 /// instruction using the specified register. 167 bool hasOneNonDBGUse(unsigned RegNo) const; 168 169 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 170 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 171 /// except that it also changes any definitions of the register as well. 172 void replaceRegWith(unsigned FromReg, unsigned ToReg); 173 174 /// getRegUseDefListHead - Return the head pointer for the register use/def 175 /// list for the specified virtual or physical register. 176 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 177 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 178 return VRegInfo[RegNo].second; 179 return PhysRegUseDefLists[RegNo]; 180 } 181 182 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 183 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 184 return VRegInfo[RegNo].second; 185 return PhysRegUseDefLists[RegNo]; 186 } 187 188 /// getVRegDef - Return the machine instr that defines the specified virtual 189 /// register or null if none is found. This assumes that the code is in SSA 190 /// form, so there should only be one definition. 191 MachineInstr *getVRegDef(unsigned Reg) const; 192 193 /// clearKillFlags - Iterate over all the uses of the given register and 194 /// clear the kill flag from the MachineOperand. This function is used by 195 /// optimization passes which extend register lifetimes and need only 196 /// preserve conservative kill flag information. 197 void clearKillFlags(unsigned Reg) const; 198 199#ifndef NDEBUG 200 void dumpUses(unsigned RegNo) const; 201#endif 202 203 //===--------------------------------------------------------------------===// 204 // Virtual Register Info 205 //===--------------------------------------------------------------------===// 206 207 /// getRegClass - Return the register class of the specified virtual register. 208 /// 209 const TargetRegisterClass *getRegClass(unsigned Reg) const { 210 return VRegInfo[Reg].first; 211 } 212 213 /// setRegClass - Set the register class of the specified virtual register. 214 /// 215 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 216 217 /// constrainRegClass - Constrain the register class of the specified virtual 218 /// register to be a common subclass of RC and the current register class. 219 /// Return the new register class, or NULL if no such class exists. 220 /// This should only be used when the constraint is known to be trivial, like 221 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 222 const TargetRegisterClass *constrainRegClass(unsigned Reg, 223 const TargetRegisterClass *RC); 224 225 /// createVirtualRegister - Create and return a new virtual register in the 226 /// function with the specified register class. 227 /// 228 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 229 230 /// getNumVirtRegs - Return the number of virtual registers created. 231 /// 232 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 233 234 /// setRegAllocationHint - Specify a register allocation hint for the 235 /// specified virtual register. 236 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 237 RegAllocHints[Reg].first = Type; 238 RegAllocHints[Reg].second = PrefReg; 239 } 240 241 /// getRegAllocationHint - Return the register allocation hint for the 242 /// specified virtual register. 243 std::pair<unsigned, unsigned> 244 getRegAllocationHint(unsigned Reg) const { 245 return RegAllocHints[Reg]; 246 } 247 248 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 249 /// standard simple hint (Type == 0) is not set. 250 unsigned getSimpleHint(unsigned Reg) const { 251 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 252 return Hint.first ? 0 : Hint.second; 253 } 254 255 256 //===--------------------------------------------------------------------===// 257 // Physical Register Use Info 258 //===--------------------------------------------------------------------===// 259 260 /// isPhysRegUsed - Return true if the specified register is used in this 261 /// function. This only works after register allocation. 262 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 263 264 /// setPhysRegUsed - Mark the specified register used in this function. 265 /// This should only be called during and after register allocation. 266 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 267 268 /// addPhysRegsUsed - Mark the specified registers used in this function. 269 /// This should only be called during and after register allocation. 270 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 271 272 /// setPhysRegUnused - Mark the specified register unused in this function. 273 /// This should only be called during and after register allocation. 274 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 275 276 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 277 /// subregisters. That means that if R is used, so are all subregisters. 278 void closePhysRegsUsed(const TargetRegisterInfo&); 279 280 //===--------------------------------------------------------------------===// 281 // LiveIn/LiveOut Management 282 //===--------------------------------------------------------------------===// 283 284 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 285 /// is an error to add the same register to the same set more than once. 286 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 287 LiveIns.push_back(std::make_pair(Reg, vreg)); 288 } 289 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 290 291 // Iteration support for live in/out sets. These sets are kept in sorted 292 // order by their register number. 293 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 294 livein_iterator; 295 typedef std::vector<unsigned>::const_iterator liveout_iterator; 296 livein_iterator livein_begin() const { return LiveIns.begin(); } 297 livein_iterator livein_end() const { return LiveIns.end(); } 298 bool livein_empty() const { return LiveIns.empty(); } 299 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 300 liveout_iterator liveout_end() const { return LiveOuts.end(); } 301 bool liveout_empty() const { return LiveOuts.empty(); } 302 303 bool isLiveIn(unsigned Reg) const; 304 bool isLiveOut(unsigned Reg) const; 305 306 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 307 /// corresponding live-in physical register. 308 unsigned getLiveInPhysReg(unsigned VReg) const; 309 310 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 311 /// corresponding live-in physical register. 312 unsigned getLiveInVirtReg(unsigned PReg) const; 313 314 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 315 /// into the given entry block. 316 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 317 const TargetRegisterInfo &TRI, 318 const TargetInstrInfo &TII); 319 320private: 321 void HandleVRegListReallocation(); 322 323public: 324 /// defusechain_iterator - This class provides iterator support for machine 325 /// operands in the function that use or define a specific register. If 326 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 327 /// returns defs. If neither are true then you are silly and it always 328 /// returns end(). If SkipDebug is true it skips uses marked Debug 329 /// when incrementing. 330 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 331 class defusechain_iterator 332 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 333 MachineOperand *Op; 334 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 335 // If the first node isn't one we're interested in, advance to one that 336 // we are interested in. 337 if (op) { 338 if ((!ReturnUses && op->isUse()) || 339 (!ReturnDefs && op->isDef()) || 340 (SkipDebug && op->isDebug())) 341 ++*this; 342 } 343 } 344 friend class MachineRegisterInfo; 345 public: 346 typedef std::iterator<std::forward_iterator_tag, 347 MachineInstr, ptrdiff_t>::reference reference; 348 typedef std::iterator<std::forward_iterator_tag, 349 MachineInstr, ptrdiff_t>::pointer pointer; 350 351 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 352 defusechain_iterator() : Op(0) {} 353 354 bool operator==(const defusechain_iterator &x) const { 355 return Op == x.Op; 356 } 357 bool operator!=(const defusechain_iterator &x) const { 358 return !operator==(x); 359 } 360 361 /// atEnd - return true if this iterator is equal to reg_end() on the value. 362 bool atEnd() const { return Op == 0; } 363 364 // Iterator traversal: forward iteration only 365 defusechain_iterator &operator++() { // Preincrement 366 assert(Op && "Cannot increment end iterator!"); 367 Op = Op->getNextOperandForReg(); 368 369 // If this is an operand we don't care about, skip it. 370 while (Op && ((!ReturnUses && Op->isUse()) || 371 (!ReturnDefs && Op->isDef()) || 372 (SkipDebug && Op->isDebug()))) 373 Op = Op->getNextOperandForReg(); 374 375 return *this; 376 } 377 defusechain_iterator operator++(int) { // Postincrement 378 defusechain_iterator tmp = *this; ++*this; return tmp; 379 } 380 381 /// skipInstruction - move forward until reaching a different instruction. 382 /// Return the skipped instruction that is no longer pointed to, or NULL if 383 /// already pointing to end(). 384 MachineInstr *skipInstruction() { 385 if (!Op) return 0; 386 MachineInstr *MI = Op->getParent(); 387 do ++*this; 388 while (Op && Op->getParent() == MI); 389 return MI; 390 } 391 392 MachineOperand &getOperand() const { 393 assert(Op && "Cannot dereference end iterator!"); 394 return *Op; 395 } 396 397 /// getOperandNo - Return the operand # of this MachineOperand in its 398 /// MachineInstr. 399 unsigned getOperandNo() const { 400 assert(Op && "Cannot dereference end iterator!"); 401 return Op - &Op->getParent()->getOperand(0); 402 } 403 404 // Retrieve a reference to the current operand. 405 MachineInstr &operator*() const { 406 assert(Op && "Cannot dereference end iterator!"); 407 return *Op->getParent(); 408 } 409 410 MachineInstr *operator->() const { 411 assert(Op && "Cannot dereference end iterator!"); 412 return Op->getParent(); 413 } 414 }; 415 416}; 417 418} // End llvm namespace 419 420#endif 421