MachineRegisterInfo.h revision 84bc5427d6883f73cfeae3da640acd011d35c006
1b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// 3b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// The LLVM Compiler Infrastructure 4b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// 5b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// This file is distributed under the University of Illinois Open Source 6b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// License. See LICENSE.TXT for details. 7b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// 8b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot//===----------------------------------------------------------------------===// 9b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// 10b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// This file defines the MachineRegisterInfo class. 11b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot// 12b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot//===----------------------------------------------------------------------===// 13b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot 14b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot 17b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot#include "llvm/Target/MRegisterInfo.h" 18b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot#include "llvm/ADT/BitVector.h" 19b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot#include <vector> 20b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot 21b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabotnamespace llvm { 22b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot 23b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot/// MachineRegisterInfo - Keep track of information for each virtual register, 24b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot/// including its register class. 25b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabotclass MachineRegisterInfo { 26b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// VRegInfo - Information we keep for each virtual register. The entries in 27b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// this vector are actually converted to vreg numbers by adding the 28b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// MRegisterInfo::FirstVirtualRegister delta to their index. 29b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot std::vector<const TargetRegisterClass*> VRegInfo; 30b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot 31b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// UsedPhysRegs - This is a bit vector that is computed and set by the 32b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// register allocator, and must be kept up to date by passes that run after 33b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// register allocation (though most don't modify this). This is used 34b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// so that the code generator knows which callee save registers to save and 35b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// for other target specific uses. 36b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot BitVector UsedPhysRegs; 37b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot 38b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// LiveIns/LiveOuts - Keep track of the physical registers that are 39b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// livein/liveout of the function. Live in values are typically arguments in 40b3823db9f1192d8c81345740b3e65bd6738ba55bBrett Chabot /// registers, live out values are typically return values in registers. 41 /// LiveIn values are allowed to have virtual registers associated with them, 42 /// stored in the second element. 43 std::vector<std::pair<unsigned, unsigned> > LiveIns; 44 std::vector<unsigned> LiveOuts; 45public: 46 MachineRegisterInfo(const MRegisterInfo &MRI); 47 48 49 //===--------------------------------------------------------------------===// 50 // Virtual Register Info 51 //===--------------------------------------------------------------------===// 52 53 /// getRegClass - Return the register class of the specified virtual register. 54 const TargetRegisterClass *getRegClass(unsigned Reg) { 55 Reg -= MRegisterInfo::FirstVirtualRegister; 56 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 57 return VRegInfo[Reg]; 58 } 59 60 /// createVirtualRegister - Create and return a new virtual register in the 61 /// function with the specified register class. 62 /// 63 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { 64 assert(RegClass && "Cannot create register without RegClass!"); 65 VRegInfo.push_back(RegClass); 66 return getLastVirtReg(); 67 } 68 69 /// getLastVirtReg - Return the highest currently assigned virtual register. 70 /// 71 unsigned getLastVirtReg() const { 72 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1; 73 } 74 75 //===--------------------------------------------------------------------===// 76 // Physical Register Use Info 77 //===--------------------------------------------------------------------===// 78 79 /// isPhysRegUsed - Return true if the specified register is used in this 80 /// function. This only works after register allocation. 81 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 82 83 /// setPhysRegUsed - Mark the specified register used in this function. 84 /// This should only be called during and after register allocation. 85 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 86 87 /// setPhysRegUnused - Mark the specified register unused in this function. 88 /// This should only be called during and after register allocation. 89 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 90 91 92 //===--------------------------------------------------------------------===// 93 // LiveIn/LiveOut Management 94 //===--------------------------------------------------------------------===// 95 96 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 97 /// is an error to add the same register to the same set more than once. 98 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 99 LiveIns.push_back(std::make_pair(Reg, vreg)); 100 } 101 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 102 103 // Iteration support for live in/out sets. These sets are kept in sorted 104 // order by their register number. 105 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 106 livein_iterator; 107 typedef std::vector<unsigned>::const_iterator liveout_iterator; 108 livein_iterator livein_begin() const { return LiveIns.begin(); } 109 livein_iterator livein_end() const { return LiveIns.end(); } 110 bool livein_empty() const { return LiveIns.empty(); } 111 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 112 liveout_iterator liveout_end() const { return LiveOuts.end(); } 113 bool liveout_empty() const { return LiveOuts.empty(); } 114}; 115 116} // End llvm namespace 117 118#endif 119