MachineRegisterInfo.h revision 90f95f88c6ce09c6744777dc9d140c3c77203b92
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 1943d1fd449f1a0ac9d9dafa0b9569bb6b2e976198Anton Korobeynikov#include "llvm/ADT/iterator.h" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Chengpublic: 2990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// Register allocation hints. 3090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng enum RegAllocHintType { 3190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RA_None, /// No preference 3290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RA_Preference, /// Prefer a particular register 3390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RA_PairEven, /// Even register of a register pair 3490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RA_PairOdd /// Odd register of a register pair 3590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng }; 3690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 3790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Chengprivate: 3884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 3984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 406f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 4362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 4462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 4511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 4611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 4711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers. For each target register class, it keeps a list of 4811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers belonging to the class. 4911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<std::vector<unsigned> > RegClass2VRegMap; 5090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 5190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 5290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// registers. For each virtual register, it keeps a register and type enum 5390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// pair making up the allocation hint. For example, if the hint type is 5490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RA_Specified, it means the virtual register prefers the specified physical 5590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint or the physical register allocated to the virtual 5690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 5790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng std::vector<std::pair<RegAllocHintType, unsigned> > RegAllocHints; 5862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 5962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 6062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 6162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 6384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 6484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 6584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 6684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 6784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 6884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 6984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 7084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 7184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 7284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 7384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 7484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 7584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 7684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 7762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 7862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 7962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 8084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 816f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 8262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 8362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 846c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 856c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 866c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 886c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 91c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool Uses, bool Defs> 92c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 93c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 94c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 95c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 96c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,true> reg_iterator; 976c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 996c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 101c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 10200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 10300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 10400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 10500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 106c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 107c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<false,true> def_iterator; 108c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 109c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 110c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 111c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 112c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 11300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 11400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 11500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 11600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 117c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 118c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,false> use_iterator; 119c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 120c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 121c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 122c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 123c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 124ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 125ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 126ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 127ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1286c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 129e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 130e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 131e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 132e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 133e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 13462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 13562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 13662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1376f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 13862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 1396f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 14062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 14162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 14284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1436c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1446f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1456c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 1466f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1476c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 1486c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1491eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1501eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1511eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1521eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1531eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 1541eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1551eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1561eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1571eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 15884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 15984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 16084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 16184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 16284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 16384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 16411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 1651eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 1666f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 16784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 16862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 16984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 170bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 171bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 17211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 17333f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 17411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 17584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 17684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 17784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 1782e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 17984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 18084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 18184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 18284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 18334cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 18484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 18511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 18611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// getRegClassVirtRegs - Return the list of virtual registers of the given 18711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// target register class. 18811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 18911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng return RegClass2VRegMap[RC->getID()]; 19011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng } 19190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 19290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 19390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 19490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng void setRegAllocationHint(unsigned Reg, 19590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHintType Type, unsigned PrefReg) { 19690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 19790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 19890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 19990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 20090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 20190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 20290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 20390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 20490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng std::pair<RegAllocHintType, unsigned> 20590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 20690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 20790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 20890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 20990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 21090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 21184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 21284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 21384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 21484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 21684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 21784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 21884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 22084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 22184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 22284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 22484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 22584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 22684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 22984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 23084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 23184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 23284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 23384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 23484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 23584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 23684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 23784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 23884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 23984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 24084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 24184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 24284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 24384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 24484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 24584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 24684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 24784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 24884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 24984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 2506d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 2516d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman bool isLiveIn(unsigned Reg) const { 2526d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2536d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman if (I->first == Reg || I->second == Reg) 2546d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return true; 2556d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return false; 2566d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman } 2576d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 25862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 25962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 2606c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2616c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 262c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 263c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 264c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 265c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 266c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns end(). 267c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool ReturnUses, bool ReturnDefs> 268c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 269c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner : public forward_iterator<MachineInstr, ptrdiff_t> { 2706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 2711327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 272c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 273c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 274c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 275ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 276ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && op->isDef())) 277c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 278c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 279c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 2806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 2816c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 282e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference; 283e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer; 2846c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 285c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 286c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 2876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 288c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 2896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 2906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 291c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 2926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 2936c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2956c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 2966c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 2976c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 299c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 3006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 3016c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 302c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 303c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 304ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 305ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && Op->isDef()))) 306c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 307c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 3086c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 3096c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 310c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 311c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 3126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 314e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 3156c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 3166c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 3176c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3186c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 319e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 320e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 321e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 322e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 323e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 324e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 325e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 326e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 327e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 328e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 329e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 330e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 331e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 332e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 333e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 334e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 335e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 3366c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 3376c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 33884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 33984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 34084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 34184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 34284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 343