MachineRegisterInfo.h revision a65aa0f0bba1ef2322d63d05c074a92168684c63
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 231213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 3411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 3511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 3611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers. For each target register class, it keeps a list of 3711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers belonging to the class. 3811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<std::vector<unsigned> > RegClass2VRegMap; 3990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 4090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 41358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 42358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 43358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 44358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 45358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 4690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 47358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 4862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 5062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 5162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 5984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 6084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 6184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 6384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 6484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 6584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 6684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 6762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 6862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 7084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 716f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 7262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 7362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 81a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 82c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 83c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 84c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 86a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 886c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 91c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 9200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 9300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 9400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 9500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 96c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 97a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 98c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 99c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 100c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 101c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 102c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 10300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 10400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 10500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 10600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 107c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 108a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 109c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 110c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 111c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 112c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 113c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 114ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 115ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 116ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 117ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 118a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 119a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 120a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 121a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 122a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 123a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 124a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 126a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 127a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 128a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 129a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 130a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 131a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 132e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 133e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 134e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 135e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 136e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 13762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 13862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 13962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1406f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 14162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 1426f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 14362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 14462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 14584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1466c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1476f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1486c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 1496f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1506c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 1516c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1521eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1531eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1541eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1551eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1561eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 1571eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1581eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1591eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1601eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 16184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 16284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 16384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 16484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 16584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 16684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 16711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 1681eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 1696f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 17084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 17162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 17284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 173bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 174bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 17511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 17633f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 17711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 17884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 17984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 18084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 1812e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 18284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 18384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 18484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 18584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 18634cd4a484e532cc463fd5a4bf59b88d13c5467c1Evan Cheng return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 18784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 18811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 18911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// getRegClassVirtRegs - Return the list of virtual registers of the given 19011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// target register class. 19111a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 19211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng return RegClass2VRegMap[RC->getID()]; 19311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng } 19490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 19590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 19690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 197358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 19890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 19990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 20090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 20190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 20290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 20390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 20490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 20590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 206358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 20790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 20890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 20990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 21090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 21190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 21290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 21384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 21484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 21584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 21684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 21884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 21984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 22084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 22284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 22384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 22484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 22684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 22784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 22884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 23084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 23184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 23284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 23384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 23484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 23584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 23684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 23784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 23884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 23984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 24084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 24184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 24284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 24384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 24484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 24584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 24684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 24784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 24884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 24984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 25084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 25184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 2526d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 2536d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman bool isLiveIn(unsigned Reg) const { 2546d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 2556d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman if (I->first == Reg || I->second == Reg) 2566d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return true; 2576d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman return false; 2586d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman } 25980f6c5898113806130975fd56d24929b06bf54f8Dan Gohman bool isLiveOut(unsigned Reg) const { 26080f6c5898113806130975fd56d24929b06bf54f8Dan Gohman for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 26180f6c5898113806130975fd56d24929b06bf54f8Dan Gohman if (*I == Reg) 26280f6c5898113806130975fd56d24929b06bf54f8Dan Gohman return true; 26380f6c5898113806130975fd56d24929b06bf54f8Dan Gohman return false; 26480f6c5898113806130975fd56d24929b06bf54f8Dan Gohman } 2656d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 26662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 26762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 2686c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 270c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 271c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 272c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 273c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 274a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 275a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 276a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 277c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 278f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 2796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 2801327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 281c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 282c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 283c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 284ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 285a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 286a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 287c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 288c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 289c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 2906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 2916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 2927362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 2937362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 2947362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 2957362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 2966c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 297c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 298c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 2996c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 300c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 3016c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 3026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 303c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 3046c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 3056c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3066c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3076c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 3086c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 3096c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3106c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 311c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 3126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 3136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 314c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 315c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 316ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 317a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && Op->isDef()) || 318a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && Op->isDebug()))) 319c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 320c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 3216c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 3226c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 323c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 324c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 3256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3266c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 327e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 3286c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 3296c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 3306c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3316c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 332e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 333e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 334e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 335e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 336e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 337e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 338e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 339e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 340e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 341e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 342e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 343e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 344e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 345e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 346e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 347e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 348e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 3496c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 3506c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 35184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 35284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 35384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 35484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 35584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 356