MachineRegisterInfo.h revision ae9f3a3b7c915f725aef5a7250e88eaeddda03c6
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 196c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner#include "llvm/ADT/iterator" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner/// MachineRegisterInfo - Keep track of information for each virtual register, 2584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner/// including its register class. 2684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 3662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 3884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 3984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 4084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 4184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 4284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 4384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 4484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 4584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 4684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 4784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 4884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 4984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 5084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 5184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 5362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 5462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 5562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 576f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 5862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 5962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 606c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 616c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 636c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 646c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 656c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 666c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 67c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool Uses, bool Defs> 68c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 69c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 70c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 71c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 72c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,true> reg_iterator; 736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 77c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 78c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 79c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<false,true> def_iterator; 80c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 81c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 82c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 83c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 84c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 85c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 86c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner typedef defusechain_iterator<true,false> use_iterator; 87c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 88c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 89c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 90c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 91c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 93e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 94e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 95e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 96e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 97e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 9862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 9962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 10062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1016f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 10262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 1036f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 10462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 10562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 10684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1076c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1086f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1096c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 1106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1116c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 1126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1131eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1141eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1151eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1161eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1171eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 1181eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1191eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1201eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1211eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 12284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 12384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 12484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 12584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 12684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 12784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 1281eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 1296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 13084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 13162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 13284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 13362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 13484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 13584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 13684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 13784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { 13884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(RegClass && "Cannot create register without RegClass!"); 13962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Add a reg, but keep track of whether the vector reallocated or not. 1409848ced5d0eec8cbc44f9fbe5ce273189b0b9b2bChris Lattner void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 14162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 14262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 1439848ced5d0eec8cbc44f9fbe5ce273189b0b9b2bChris Lattner if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1) 14462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return getLastVirtReg(); 14562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 14662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Otherwise, the vector reallocated, handle this now. 14762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner HandleVRegListReallocation(); 14884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner return getLastVirtReg(); 14984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 15084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 15184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 15284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 15384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 1546f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman return VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 15584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 15684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 157a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 15884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 15984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 16084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 16184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 16284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 16384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 16484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 16584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 16684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 16784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 16884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 16984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 17084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 17184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 17284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 17384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 17484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 17584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 17684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 17784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 17884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 17984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 18084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 18184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 18284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 18384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 18484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 18584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 18684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 18784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 18884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 18984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 19084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 19184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 19284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 19384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 19484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 19584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 19684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 19762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 19862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 1996c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 201c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 202c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 203c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 204c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 205c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns end(). 206c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner template<bool ReturnUses, bool ReturnDefs> 207c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 208c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner : public forward_iterator<MachineInstr, ptrdiff_t> { 2096c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 2101327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 211c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 212c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 213c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 214ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 215ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && op->isDef())) 216c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 217c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 218c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 2196c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 2206c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 221e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference; 222e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer; 2236c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 224c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 225c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 2266c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 227c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 2286c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 2296c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 230c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 2316c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 2326c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2346c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 2356c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 2366c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2376c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 238c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 2396c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 2406c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 241c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 242c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 243ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 244ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov (!ReturnDefs && Op->isDef()))) 245c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 246c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 2476c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 2486c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 249c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 250c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 2516c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2526c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 253e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 2546c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 2556c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 2566c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2576c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 258e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 259e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 260e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 261e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 262e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 263e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 264e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 265e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 266e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 267e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 268e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 269e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 270e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 271e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 272e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 273e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 274e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 2756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 2766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 27784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 27884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 27984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 28084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 28184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 282