MachineRegisterInfo.h revision b421c566f512ed0ec87851866d335e9086c3f8be
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 1984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 231213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 296f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 3411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 3511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 3611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers. For each target register class, it keeps a list of 3711a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// virtual registers belonging to the class. 38a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman std::vector<unsigned> *RegClass2VRegMap; 3990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 4090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 41358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 42358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 43358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 44358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 45358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 4690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 47358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 4862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 5062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 5162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 5984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 6084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 6184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 6284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 6384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 6484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 6584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 6684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 6762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 6862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 7084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 716f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 7262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 7362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 796c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 81a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 82c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 83c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 84c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 86a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 886c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 91c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 9200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 9300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 9400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 9500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 96c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 97c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// of the specified register, skipping those marked as Debug. 98c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 99c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 100c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 101c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 102c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 103c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 104c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_empty - Return true if the only instructions using or defining 105c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// Reg are Debug instructions. 106c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen bool reg_nodbg_empty(unsigned RegNo) const { 107c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 108c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 109c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 110c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 111a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 112c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 113c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 114c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 115c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 116c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 11700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 11800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 11900ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 12000ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 121c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 122a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 123c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 124c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 125c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 126c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 127c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 128ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 129ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 130ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 131ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1321423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneUse - Return true if there is exactly one instruction using the 1331423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// specified register. 1341423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneUse(unsigned RegNo) const; 1351423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 136a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 137a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 138a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 139a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 140a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 141a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 142a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1436c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 144a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 145a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 146a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 147a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 148a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 149a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 1501423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 1511423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// instruction using the specified register. 1521423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneNonDBGUse(unsigned RegNo) const; 1531423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 154e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 155e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 156e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 157e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 158e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 15962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 16062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 16162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1626f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 16362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 1646f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 16562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 16662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 16784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1686c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1696f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 1716f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1726c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 1736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1741eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1751eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1761eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1771eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1781eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 17949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 18049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clearKillFlags - Iterate over all the uses of the given register and 18149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clear the kill flag from the MachineOperand. This function is used by 18249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// optimization passes which extend register lifetimes and need only 18349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// preserve conservative kill flag information. 18449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman void clearKillFlags(unsigned Reg) const; 1851eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1861eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1871eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1881eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 18984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 19084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 19184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 19284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 19384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 19484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 19511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 1961eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 1976f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman Reg -= TargetRegisterInfo::FirstVirtualRegister; 19884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 19962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 20084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 201bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 202bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 20311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 20433f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 20511a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 206bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// constrainRegClass - Constrain the register class of the specified virtual 207bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// register to be a common subclass of RC and the current register class. 208bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// Return the new register class, or NULL if no such class exists. 209bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// This should only be used when the constraint is known to be trivial, like 210bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 211bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *constrainRegClass(unsigned Reg, 212bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *RC); 213bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 21484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 21584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 21684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 2172e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 21884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 219b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// getNumVirtRegs - Return the number of virtual registers created. 220b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// 221b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen unsigned getNumVirtRegs() const { return VRegInfo.size(); } 222b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 22384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 22484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 22584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 226b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen return TargetRegisterInfo::index2VirtReg(getNumVirtRegs() - 1); 22784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 22811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 22911a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// getRegClassVirtRegs - Return the list of virtual registers of the given 23011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// target register class. 23165569b8ddff9d4b8647377291f8f0f2cb647bfb9Chris Lattner const std::vector<unsigned> & 23265569b8ddff9d4b8647377291f8f0f2cb647bfb9Chris Lattner getRegClassVirtRegs(const TargetRegisterClass *RC) const { 23311a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng return RegClass2VRegMap[RC->getID()]; 23411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng } 23590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 23690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 23790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 238358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 23990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 24090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 24190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 24290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 24390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 24490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 24590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 24690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 247358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 24890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 24990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng Reg -= TargetRegisterInfo::FirstVirtualRegister; 25090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng assert(Reg < VRegInfo.size() && "Invalid vreg!"); 25190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 25290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 25390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 25484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 25584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 25684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 25784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 25884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 25984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 26084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 26184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 26284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 26384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 26484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 26582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 26682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// addPhysRegsUsed - Mark the specified registers used in this function. 26782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// This should only be called during and after register allocation. 26882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 26982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 27084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 27184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 27284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 27382b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 27482b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 27582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// subregisters. That means that if R is used, so are all subregisters. 27682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void closePhysRegsUsed(const TargetRegisterInfo&); 27784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 27884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 27984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 28084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 28184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 28284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 28384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 28484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 28584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 28684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 28784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 28884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 28984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 29084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 29184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 29284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 29384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 29484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 29584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 29684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 29784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 29884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 29984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 3006d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 30113e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveIn(unsigned Reg) const; 30213e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveOut(unsigned Reg) const; 3036d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 3042ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 3052ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// corresponding live-in physical register. 3062ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng unsigned getLiveInPhysReg(unsigned VReg) const; 3072ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 3083946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// getLiveInVirtReg - If PReg is a live-in physical register, return the 3093946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// corresponding live-in physical register. 3103946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng unsigned getLiveInVirtReg(unsigned PReg) const; 3113946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 31298708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 31398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// into the given entry block. 31498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 31598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 31698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII); 31798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 31862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 31962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 3206c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3216c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 322c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 323c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 324c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 325c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 326a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 327a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 328a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 329c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 330f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 3316c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 3321327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 333c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 334c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 335c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 336ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 337a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 338a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 339c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 340c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 341c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 3426c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 3436c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 3447362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 3457362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 3467362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 3477362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 3486c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 349c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 350c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 3516c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 352c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 3536c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 3546c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 355c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 3566c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 3576c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3586c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3596c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 3606c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 3616c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 363c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 3646c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 3656c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 366c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 367c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 368ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 369a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && Op->isDef()) || 370a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && Op->isDebug()))) 371c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 372c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 3736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 3746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 375c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 376c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 3776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 378914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 379914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// skipInstruction - move forward until reaching a different instruction. 380914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// Return the skipped instruction that is no longer pointed to, or NULL if 381914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// already pointing to end(). 382914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *skipInstruction() { 383914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen if (!Op) return 0; 384914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *MI = Op->getParent(); 385914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen do ++*this; 386914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen while (Op && Op->getParent() == MI); 387914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen return MI; 388914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen } 389914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 390e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 3916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 3926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 3936c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 395e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 396e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 397e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 398e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 399e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 400e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 401e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 402e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 403e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 404e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 405e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 406e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 407e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 408e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 409e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 410e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 411e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 4126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 4136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 41484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 41584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 41684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 41784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 41884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 419