MachineRegisterInfo.h revision d9e5c764bfea339fc5082bf17e558db959fd6d28
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 19994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen#include "llvm/ADT/IndexedMap.h" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 28e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen const TargetRegisterInfo *const TRI; 29e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund Olesen 3073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// IsSSA - True when the machine function is in SSA form and virtual 3173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen /// registers have a single def. 3273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool IsSSA; 3373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 34994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen /// VRegInfo - Information we keep for each virtual register. 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 38994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 39994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VirtReg2IndexFunctor> VRegInfo; 4011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 4190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 42358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 43358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 44358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 45358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 46358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 4790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 48994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 4962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 5062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 5162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 5262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 60d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 61d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// ReservedRegs - This is a bit vector of reserved registers. The target 62d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// may change its mind about which registers should be reserved. This 63d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// vector is the frozen set of reserved registers when register allocation 64d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// started. 65d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen BitVector ReservedRegs; 66d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 6784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 6884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 6984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 7084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 7184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 7284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 7384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 7468e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel 7562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 7662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 7784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 786f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 7962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 8073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 8173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 8273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // Function State 8373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 8473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 8573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // isSSA - Returns true when the machine function is in SSA form. Early 8673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // passes require the machine function to be in SSA form where every virtual 8773e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register has a single defining instruction. 8873e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // 8973e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // The TwoAddressInstructionPass and PHIElimination passes take the machine 9073e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // function out of SSA form when they introduce multiple defs per virtual 9173e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // register. 9273e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen bool isSSA() const { return IsSSA; } 9373e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 9473e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen // leaveSSA - Indicates that the machine function is no longer in SSA form. 9573e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen void leaveSSA() { IsSSA = false; } 9673e7dced3892f2abb4344526147d4df0f62aee61Jakob Stoklund Olesen 976c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 996c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 1006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 1016c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 1026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 1036c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 104a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 105c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 106c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 107c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 108c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 109a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 1106c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 1116c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 1126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 114c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 11500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 11600ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 11700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 11800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 119c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 120c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// of the specified register, skipping those marked as Debug. 121c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 122c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 123c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 124c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 125c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 126c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 127c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_empty - Return true if the only instructions using or defining 128c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// Reg are Debug instructions. 129c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen bool reg_nodbg_empty(unsigned RegNo) const { 130c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 131c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 132c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 133c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 134a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 135c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 136c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 137c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 138c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 139c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 14000ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 14100ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 14200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 14300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 144c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 145a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 146c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 147c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 148c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 149c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 150c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 151ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 152ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 153ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 154ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1551423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneUse - Return true if there is exactly one instruction using the 1561423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// specified register. 1571423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneUse(unsigned RegNo) const; 1581423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 159a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 160a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 161a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 162a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 163a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 164a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 165a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1666c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 167a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 168a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 169a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 170a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 171a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 172a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 1731423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 1741423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// instruction using the specified register. 1751423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneNonDBGUse(unsigned RegNo) const; 1761423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 177e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 178e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 179e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 1804007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 1814007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// Note that it is usually necessary to first constrain ToReg's register 1824007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// class to match the FromReg constraints using: 1834007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 1844007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// constrainRegClass(ToReg, getRegClass(FromReg)) 1854007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// 1864007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// That function will return NULL if the virtual registers have incompatible 1874007529d4b014f43a1c7089f9b285a67c1c9b853Jakob Stoklund Olesen /// constraints. 188e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 189e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 19062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 19162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 19262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 193c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 194c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 195c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 19662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 19784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 199c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 200c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 201c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 2026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2031eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 2041eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 2051eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 2061eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 2071eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 20849b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 20949b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clearKillFlags - Iterate over all the uses of the given register and 21049b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clear the kill flag from the MachineOperand. This function is used by 21149b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// optimization passes which extend register lifetimes and need only 21249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// preserve conservative kill flag information. 21349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman void clearKillFlags(unsigned Reg) const; 2141eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 2151eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 2161eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 2171eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 21884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 21984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 22084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 22184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 22284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 22384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 22411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 2251eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 22662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 22784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 228bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 229bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 23011a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 23133f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 23211a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 233bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// constrainRegClass - Constrain the register class of the specified virtual 23491fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// register to be a common subclass of RC and the current register class, 23591fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// but only if the new class has at least MinNumRegs registers. Return the 23691fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen /// new register class, or NULL if no such class exists. 237bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// This should only be used when the constraint is known to be trivial, like 238bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 2396d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 240bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *constrainRegClass(unsigned Reg, 24191fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen const TargetRegisterClass *RC, 24291fb536a345dc268e5b73dbddb9bee4cba87b28fJakob Stoklund Olesen unsigned MinNumRegs = 0); 243bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 2446d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// recomputeRegClass - Try to find a legal super-class of Reg's register 2456d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// class that still satisfies the constraints from the instructions using 2466d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// Reg. Returns true if Reg was upgraded. 2476d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 2486d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// This method can be used after constraints have been removed from a 2496d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// virtual register, for example after removing instructions or splitting 2506d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// the live range. 2516d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen /// 2526d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen bool recomputeRegClass(unsigned Reg, const TargetMachine&); 2536d1fd0b979cb88809ebb77a24f4da69e1d67606bJakob Stoklund Olesen 25484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 25584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 25684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 2572e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 25884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 259b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// getNumVirtRegs - Return the number of virtual registers created. 260b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// 261b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen unsigned getNumVirtRegs() const { return VRegInfo.size(); } 262b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 26390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 26490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 265358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 26690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 26790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 26890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 26990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 27090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 27190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 272358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 27390f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 27490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 27590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 27690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 27751458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 27851458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// standard simple hint (Type == 0) is not set. 27951458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen unsigned getSimpleHint(unsigned Reg) const { 28051458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 28151458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen return Hint.first ? 0 : Hint.second; 28251458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen } 28351458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 28451458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 28584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 28684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 28784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 28884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 28984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 29084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 29184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 292a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen 293a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register 294a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen /// is used in this function. 295a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen bool isPhysRegOrOverlapUsed(unsigned Reg) const { 296a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen for (const unsigned *AI = TRI->getOverlaps(Reg); *AI; ++AI) 297a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen if (isPhysRegUsed(*AI)) 298a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen return true; 299a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen return false; 300a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen } 301a2a98fd0ddd2ae277be7cdd62aae92f6c5155e07Jakob Stoklund Olesen 30284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 30384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 30484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 30582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 30682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// addPhysRegsUsed - Mark the specified registers used in this function. 30782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// This should only be called during and after register allocation. 30882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 30982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 31084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 31184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 31284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 31382b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 31482b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 31582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// subregisters. That means that if R is used, so are all subregisters. 31682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void closePhysRegsUsed(const TargetRegisterInfo&); 31784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 318d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 319d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 320d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // Reserved Register Info 321d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen //===--------------------------------------------------------------------===// 322d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // 323d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // The set of reserved registers must be invariant during register 324d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // allocation. For example, the target cannot suddenly decide it needs a 325d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // frame pointer when the register allocator has already used the frame 326d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // pointer register for something else. 327d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // 328d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // These methods can be used by target hooks like hasFP() to avoid changing 329d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen // the reserved register set during register allocation. 330d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 331d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// freezeReservedRegs - Called by the register allocator to freeze the set 332d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// of reserved registers before allocation begins. 333d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen void freezeReservedRegs(const MachineFunction&); 334d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 335d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 336d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// to ensure the set of reserved registers stays constant. 337d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen bool reservedRegsFrozen() const { 338d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen return !ReservedRegs.empty(); 339d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen } 340d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 341d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// canReserveReg - Returns true if PhysReg can be used as a reserved 342d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// register. Any register can be reserved before freezeReservedRegs() is 343d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen /// called. 344d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen bool canReserveReg(unsigned PhysReg) const { 345d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 346d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen } 347d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 348d9e5c764bfea339fc5082bf17e558db959fd6d28Jakob Stoklund Olesen 34984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 35084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 35184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 35284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 35384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 35484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 35584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 35684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 35784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 35884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 35968e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel 36084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 36184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 36284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 36384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 36484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 36584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 36684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 36784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 36884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 36984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 37084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 3716d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 37213e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveIn(unsigned Reg) const; 37313e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveOut(unsigned Reg) const; 3746d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 3752ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 3762ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// corresponding live-in physical register. 3772ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng unsigned getLiveInPhysReg(unsigned VReg) const; 3782ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 3793946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// getLiveInVirtReg - If PReg is a live-in physical register, return the 3803946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// corresponding live-in physical register. 3813946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng unsigned getLiveInVirtReg(unsigned PReg) const; 3823946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 38398708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 38498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// into the given entry block. 38598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 38698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 38798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII); 38898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 38962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 39062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 3916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 393c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 394c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 395c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 396c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 397a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 398a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 399a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 400c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 401f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 4026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 4031327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 404c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 405c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 406c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 407ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 408a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 409a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 410c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 411c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 412c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 4136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 4146c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 4157362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 4167362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 4177362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 4187362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 4196c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 420c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 421c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 4226c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 423c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 4246c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 4256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 426c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 4276c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 4286c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 4296c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 4306c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 4316c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 4326c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 4336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 434c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 4356c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 4366c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 437c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 438c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 439ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 440a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && Op->isDef()) || 441a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && Op->isDebug()))) 442c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 443c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 4446c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 4456c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 446c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 447c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 4486c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 449914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 450914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// skipInstruction - move forward until reaching a different instruction. 451914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// Return the skipped instruction that is no longer pointed to, or NULL if 452914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// already pointing to end(). 453914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *skipInstruction() { 454914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen if (!Op) return 0; 455914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *MI = Op->getParent(); 456914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen do ++*this; 457914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen while (Op && Op->getParent() == MI); 458914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen return MI; 459914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen } 460914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 461e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 4626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 4636c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 4646c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 4656c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 466e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 467e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 468e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 469e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 470e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 471e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 472e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 473e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 474e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 475e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 476e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 477e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 478e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 479e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 480e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 481e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 482e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 4836c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 4846c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 48584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 48684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 48784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 48884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 48984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 490