MachineRegisterInfo.h revision e138b3dd1ff02d826233482831318708a166ed93
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/Target/MRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 196c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner#include "llvm/ADT/iterator" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner/// MachineRegisterInfo - Keep track of information for each virtual register, 2584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner/// including its register class. 2684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// VRegInfo - Information we keep for each virtual register. The entries in 2884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// this vector are actually converted to vreg numbers by adding the 2984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// MRegisterInfo::FirstVirtualRegister delta to their index. 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 3662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 3884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 3984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 4084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 4184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 4284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 4384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 4484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 4584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 4684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 4784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 4884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 4984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 5084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 5184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 5362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 5462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 5562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner MachineRegisterInfo(const MRegisterInfo &MRI); 5862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 5962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 606c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 616c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 636c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 646c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 656c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 666c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 676c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner class reg_iterator; 686c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 716c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 726c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 73e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 74e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 75e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 76e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 77e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 7862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 7962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 8062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 8162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (RegNo < MRegisterInfo::FirstVirtualRegister) 8262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return PhysRegUseDefLists[RegNo]; 8362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner RegNo -= MRegisterInfo::FirstVirtualRegister; 8462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[RegNo].second; 8562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 8684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 886c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner if (RegNo < MRegisterInfo::FirstVirtualRegister) 896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return PhysRegUseDefLists[RegNo]; 906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner RegNo -= MRegisterInfo::FirstVirtualRegister; 916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return VRegInfo[RegNo].second; 926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 9384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 9484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 9584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 9684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 9784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 9884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 9984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner const TargetRegisterClass *getRegClass(unsigned Reg) { 10084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner Reg -= MRegisterInfo::FirstVirtualRegister; 10184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(Reg < VRegInfo.size() && "Invalid vreg!"); 10262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 10384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 10462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 10584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 10684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 10784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 10884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned createVirtualRegister(const TargetRegisterClass *RegClass) { 10984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner assert(RegClass && "Cannot create register without RegClass!"); 11062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Add a reg, but keep track of whether the vector reallocated or not. 11162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void *ArrayBase = &VRegInfo[0]; 11262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 11362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 11462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner if (&VRegInfo[0] == ArrayBase) 11562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return getLastVirtReg(); 11662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 11762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner // Otherwise, the vector reallocated, handle this now. 11862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner HandleVRegListReallocation(); 11984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner return getLastVirtReg(); 12084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 12184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 12284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getLastVirtReg - Return the highest currently assigned virtual register. 12384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 12484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner unsigned getLastVirtReg() const { 12584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1; 12684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 12784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 128a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner /// getVRegDef - Return the machine instr that defines the specified virtual 129a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner /// register or null if none is found. This assumes that the code is in SSA 130a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner /// form, so there should only be one definition. 131a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner MachineInstr *getVRegDef(unsigned Reg) const; 132a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 133a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner 13484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 13584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 13684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 13784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 13884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 13984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 14084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 14184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 14284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 14384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 14484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 14584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 14684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 14784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 14884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 14984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 15084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 15184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 15284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 15384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 15484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 15584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 15684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 15784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 15884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 15984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 16084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 16184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 16284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 16384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 16484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 16584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 16684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 16784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 16884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 16984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 17084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 17184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 17284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 17362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 17462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 1756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 1766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 1776c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_iterator - This class provides iterator support for machine 1786c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// operands in the function that use or define a specific register. 179e138b3dd1ff02d826233482831318708a166ed93Chris Lattner class reg_iterator : public forward_iterator<MachineInstr, ptrdiff_t> { 1806c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 1816c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator(MachineOperand *op) : Op(op) {} 1826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 1836c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 184e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference; 185e138b3dd1ff02d826233482831318708a166ed93Chris Lattner typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer; 1866c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 1876c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator(const reg_iterator &I) : Op(I.Op) {} 1886c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator() : Op(0) {} 1896c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 1906c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool operator==(const reg_iterator &x) const { 1916c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 1926c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1936c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool operator!=(const reg_iterator &x) const { 1946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 1956c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1966c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 1976c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 1986c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 1996c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 2006c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 2016c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator &operator++() { // Preincrement 2026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 2036c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 2046c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 2056c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2066c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator operator++(int) { // Postincrement 2076c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator tmp = *this; ++*this; return tmp; 2086c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2096c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 210e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 2116c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 2126c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 2136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 2146c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 215e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 216e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 217e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 218e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 219e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 220e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 221e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 222e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 223e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 224e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 225e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 226e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 227e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 228e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 229e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 230e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 231e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 2326c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 2336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 23484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 23584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 23684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 23784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 23884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 239