MachineRegisterInfo.h revision 6d1fd0b979cb88809ebb77a24f4da69e1d67606b
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/IndexedMap.h" 20#include <vector> 21 22namespace llvm { 23 24/// MachineRegisterInfo - Keep track of information for virtual and physical 25/// registers, including vreg register classes, use/def chains for registers, 26/// etc. 27class MachineRegisterInfo { 28 /// IsSSA - True when the machine function is in SSA form and virtual 29 /// registers have a single def. 30 bool IsSSA; 31 32 /// VRegInfo - Information we keep for each virtual register. 33 /// 34 /// Each element in this list contains the register class of the vreg and the 35 /// start of the use/def list for the register. 36 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 37 VirtReg2IndexFunctor> VRegInfo; 38 39 /// RegAllocHints - This vector records register allocation hints for virtual 40 /// registers. For each virtual register, it keeps a register and hint type 41 /// pair making up the allocation hint. Hint type is target specific except 42 /// for the value 0 which means the second value of the pair is the preferred 43 /// register for allocation. For example, if the hint is <0, 1024>, it means 44 /// the allocator should prefer the physical register allocated to the virtual 45 /// register of the hint. 46 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 47 48 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 49 /// physical registers. 50 MachineOperand **PhysRegUseDefLists; 51 52 /// UsedPhysRegs - This is a bit vector that is computed and set by the 53 /// register allocator, and must be kept up to date by passes that run after 54 /// register allocation (though most don't modify this). This is used 55 /// so that the code generator knows which callee save registers to save and 56 /// for other target specific uses. 57 BitVector UsedPhysRegs; 58 59 /// LiveIns/LiveOuts - Keep track of the physical registers that are 60 /// livein/liveout of the function. Live in values are typically arguments in 61 /// registers, live out values are typically return values in registers. 62 /// LiveIn values are allowed to have virtual registers associated with them, 63 /// stored in the second element. 64 std::vector<std::pair<unsigned, unsigned> > LiveIns; 65 std::vector<unsigned> LiveOuts; 66 67 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 68 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69public: 70 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 71 ~MachineRegisterInfo(); 72 73 //===--------------------------------------------------------------------===// 74 // Function State 75 //===--------------------------------------------------------------------===// 76 77 // isSSA - Returns true when the machine function is in SSA form. Early 78 // passes require the machine function to be in SSA form where every virtual 79 // register has a single defining instruction. 80 // 81 // The TwoAddressInstructionPass and PHIElimination passes take the machine 82 // function out of SSA form when they introduce multiple defs per virtual 83 // register. 84 bool isSSA() const { return IsSSA; } 85 86 // leaveSSA - Indicates that the machine function is no longer in SSA form. 87 void leaveSSA() { IsSSA = false; } 88 89 //===--------------------------------------------------------------------===// 90 // Register Info 91 //===--------------------------------------------------------------------===// 92 93 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 94 /// and uses of a register within the MachineFunction that corresponds to this 95 /// MachineRegisterInfo object. 96 template<bool Uses, bool Defs, bool SkipDebug> 97 class defusechain_iterator; 98 99 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 100 /// register. 101 typedef defusechain_iterator<true,true,false> reg_iterator; 102 reg_iterator reg_begin(unsigned RegNo) const { 103 return reg_iterator(getRegUseDefListHead(RegNo)); 104 } 105 static reg_iterator reg_end() { return reg_iterator(0); } 106 107 /// reg_empty - Return true if there are no instructions using or defining the 108 /// specified register (it may be live-in). 109 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 110 111 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 112 /// of the specified register, skipping those marked as Debug. 113 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 114 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 115 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 116 } 117 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 118 119 /// reg_nodbg_empty - Return true if the only instructions using or defining 120 /// Reg are Debug instructions. 121 bool reg_nodbg_empty(unsigned RegNo) const { 122 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 123 } 124 125 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 126 typedef defusechain_iterator<false,true,false> def_iterator; 127 def_iterator def_begin(unsigned RegNo) const { 128 return def_iterator(getRegUseDefListHead(RegNo)); 129 } 130 static def_iterator def_end() { return def_iterator(0); } 131 132 /// def_empty - Return true if there are no instructions defining the 133 /// specified register (it may be live-in). 134 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 135 136 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 137 typedef defusechain_iterator<true,false,false> use_iterator; 138 use_iterator use_begin(unsigned RegNo) const { 139 return use_iterator(getRegUseDefListHead(RegNo)); 140 } 141 static use_iterator use_end() { return use_iterator(0); } 142 143 /// use_empty - Return true if there are no instructions using the specified 144 /// register. 145 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 146 147 /// hasOneUse - Return true if there is exactly one instruction using the 148 /// specified register. 149 bool hasOneUse(unsigned RegNo) const; 150 151 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 152 /// specified register, skipping those marked as Debug. 153 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 154 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 155 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 156 } 157 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 158 159 /// use_nodbg_empty - Return true if there are no non-Debug instructions 160 /// using the specified register. 161 bool use_nodbg_empty(unsigned RegNo) const { 162 return use_nodbg_begin(RegNo) == use_nodbg_end(); 163 } 164 165 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 166 /// instruction using the specified register. 167 bool hasOneNonDBGUse(unsigned RegNo) const; 168 169 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 170 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 171 /// except that it also changes any definitions of the register as well. 172 void replaceRegWith(unsigned FromReg, unsigned ToReg); 173 174 /// getRegUseDefListHead - Return the head pointer for the register use/def 175 /// list for the specified virtual or physical register. 176 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 177 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 178 return VRegInfo[RegNo].second; 179 return PhysRegUseDefLists[RegNo]; 180 } 181 182 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 183 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 184 return VRegInfo[RegNo].second; 185 return PhysRegUseDefLists[RegNo]; 186 } 187 188 /// getVRegDef - Return the machine instr that defines the specified virtual 189 /// register or null if none is found. This assumes that the code is in SSA 190 /// form, so there should only be one definition. 191 MachineInstr *getVRegDef(unsigned Reg) const; 192 193 /// clearKillFlags - Iterate over all the uses of the given register and 194 /// clear the kill flag from the MachineOperand. This function is used by 195 /// optimization passes which extend register lifetimes and need only 196 /// preserve conservative kill flag information. 197 void clearKillFlags(unsigned Reg) const; 198 199#ifndef NDEBUG 200 void dumpUses(unsigned RegNo) const; 201#endif 202 203 //===--------------------------------------------------------------------===// 204 // Virtual Register Info 205 //===--------------------------------------------------------------------===// 206 207 /// getRegClass - Return the register class of the specified virtual register. 208 /// 209 const TargetRegisterClass *getRegClass(unsigned Reg) const { 210 return VRegInfo[Reg].first; 211 } 212 213 /// setRegClass - Set the register class of the specified virtual register. 214 /// 215 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 216 217 /// constrainRegClass - Constrain the register class of the specified virtual 218 /// register to be a common subclass of RC and the current register class. 219 /// Return the new register class, or NULL if no such class exists. 220 /// This should only be used when the constraint is known to be trivial, like 221 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 222 /// 223 const TargetRegisterClass *constrainRegClass(unsigned Reg, 224 const TargetRegisterClass *RC); 225 226 /// recomputeRegClass - Try to find a legal super-class of Reg's register 227 /// class that still satisfies the constraints from the instructions using 228 /// Reg. Returns true if Reg was upgraded. 229 /// 230 /// This method can be used after constraints have been removed from a 231 /// virtual register, for example after removing instructions or splitting 232 /// the live range. 233 /// 234 bool recomputeRegClass(unsigned Reg, const TargetMachine&); 235 236 /// createVirtualRegister - Create and return a new virtual register in the 237 /// function with the specified register class. 238 /// 239 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 240 241 /// getNumVirtRegs - Return the number of virtual registers created. 242 /// 243 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 244 245 /// setRegAllocationHint - Specify a register allocation hint for the 246 /// specified virtual register. 247 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 248 RegAllocHints[Reg].first = Type; 249 RegAllocHints[Reg].second = PrefReg; 250 } 251 252 /// getRegAllocationHint - Return the register allocation hint for the 253 /// specified virtual register. 254 std::pair<unsigned, unsigned> 255 getRegAllocationHint(unsigned Reg) const { 256 return RegAllocHints[Reg]; 257 } 258 259 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 260 /// standard simple hint (Type == 0) is not set. 261 unsigned getSimpleHint(unsigned Reg) const { 262 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 263 return Hint.first ? 0 : Hint.second; 264 } 265 266 267 //===--------------------------------------------------------------------===// 268 // Physical Register Use Info 269 //===--------------------------------------------------------------------===// 270 271 /// isPhysRegUsed - Return true if the specified register is used in this 272 /// function. This only works after register allocation. 273 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 274 275 /// setPhysRegUsed - Mark the specified register used in this function. 276 /// This should only be called during and after register allocation. 277 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 278 279 /// addPhysRegsUsed - Mark the specified registers used in this function. 280 /// This should only be called during and after register allocation. 281 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 282 283 /// setPhysRegUnused - Mark the specified register unused in this function. 284 /// This should only be called during and after register allocation. 285 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 286 287 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 288 /// subregisters. That means that if R is used, so are all subregisters. 289 void closePhysRegsUsed(const TargetRegisterInfo&); 290 291 //===--------------------------------------------------------------------===// 292 // LiveIn/LiveOut Management 293 //===--------------------------------------------------------------------===// 294 295 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 296 /// is an error to add the same register to the same set more than once. 297 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 298 LiveIns.push_back(std::make_pair(Reg, vreg)); 299 } 300 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 301 302 // Iteration support for live in/out sets. These sets are kept in sorted 303 // order by their register number. 304 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 305 livein_iterator; 306 typedef std::vector<unsigned>::const_iterator liveout_iterator; 307 livein_iterator livein_begin() const { return LiveIns.begin(); } 308 livein_iterator livein_end() const { return LiveIns.end(); } 309 bool livein_empty() const { return LiveIns.empty(); } 310 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 311 liveout_iterator liveout_end() const { return LiveOuts.end(); } 312 bool liveout_empty() const { return LiveOuts.empty(); } 313 314 bool isLiveIn(unsigned Reg) const; 315 bool isLiveOut(unsigned Reg) const; 316 317 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 318 /// corresponding live-in physical register. 319 unsigned getLiveInPhysReg(unsigned VReg) const; 320 321 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 322 /// corresponding live-in physical register. 323 unsigned getLiveInVirtReg(unsigned PReg) const; 324 325 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 326 /// into the given entry block. 327 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 328 const TargetRegisterInfo &TRI, 329 const TargetInstrInfo &TII); 330 331private: 332 void HandleVRegListReallocation(); 333 334public: 335 /// defusechain_iterator - This class provides iterator support for machine 336 /// operands in the function that use or define a specific register. If 337 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 338 /// returns defs. If neither are true then you are silly and it always 339 /// returns end(). If SkipDebug is true it skips uses marked Debug 340 /// when incrementing. 341 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 342 class defusechain_iterator 343 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 344 MachineOperand *Op; 345 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 346 // If the first node isn't one we're interested in, advance to one that 347 // we are interested in. 348 if (op) { 349 if ((!ReturnUses && op->isUse()) || 350 (!ReturnDefs && op->isDef()) || 351 (SkipDebug && op->isDebug())) 352 ++*this; 353 } 354 } 355 friend class MachineRegisterInfo; 356 public: 357 typedef std::iterator<std::forward_iterator_tag, 358 MachineInstr, ptrdiff_t>::reference reference; 359 typedef std::iterator<std::forward_iterator_tag, 360 MachineInstr, ptrdiff_t>::pointer pointer; 361 362 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 363 defusechain_iterator() : Op(0) {} 364 365 bool operator==(const defusechain_iterator &x) const { 366 return Op == x.Op; 367 } 368 bool operator!=(const defusechain_iterator &x) const { 369 return !operator==(x); 370 } 371 372 /// atEnd - return true if this iterator is equal to reg_end() on the value. 373 bool atEnd() const { return Op == 0; } 374 375 // Iterator traversal: forward iteration only 376 defusechain_iterator &operator++() { // Preincrement 377 assert(Op && "Cannot increment end iterator!"); 378 Op = Op->getNextOperandForReg(); 379 380 // If this is an operand we don't care about, skip it. 381 while (Op && ((!ReturnUses && Op->isUse()) || 382 (!ReturnDefs && Op->isDef()) || 383 (SkipDebug && Op->isDebug()))) 384 Op = Op->getNextOperandForReg(); 385 386 return *this; 387 } 388 defusechain_iterator operator++(int) { // Postincrement 389 defusechain_iterator tmp = *this; ++*this; return tmp; 390 } 391 392 /// skipInstruction - move forward until reaching a different instruction. 393 /// Return the skipped instruction that is no longer pointed to, or NULL if 394 /// already pointing to end(). 395 MachineInstr *skipInstruction() { 396 if (!Op) return 0; 397 MachineInstr *MI = Op->getParent(); 398 do ++*this; 399 while (Op && Op->getParent() == MI); 400 return MI; 401 } 402 403 MachineOperand &getOperand() const { 404 assert(Op && "Cannot dereference end iterator!"); 405 return *Op; 406 } 407 408 /// getOperandNo - Return the operand # of this MachineOperand in its 409 /// MachineInstr. 410 unsigned getOperandNo() const { 411 assert(Op && "Cannot dereference end iterator!"); 412 return Op - &Op->getParent()->getOperand(0); 413 } 414 415 // Retrieve a reference to the current operand. 416 MachineInstr &operator*() const { 417 assert(Op && "Cannot dereference end iterator!"); 418 return *Op->getParent(); 419 } 420 421 MachineInstr *operator->() const { 422 assert(Op && "Cannot dereference end iterator!"); 423 return Op->getParent(); 424 } 425 }; 426 427}; 428 429} // End llvm namespace 430 431#endif 432