MachineRegisterInfo.h revision 9aa6e0a134358c681cc5918ec65b1ec9726b778e
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/CodeGen/MachineInstrBundle.h" 19#include "llvm/ADT/BitVector.h" 20#include "llvm/ADT/IndexedMap.h" 21#include <vector> 22 23namespace llvm { 24 25/// MachineRegisterInfo - Keep track of information for virtual and physical 26/// registers, including vreg register classes, use/def chains for registers, 27/// etc. 28class MachineRegisterInfo { 29 const TargetRegisterInfo *const TRI; 30 31 /// IsSSA - True when the machine function is in SSA form and virtual 32 /// registers have a single def. 33 bool IsSSA; 34 35 /// TracksLiveness - True while register liveness is being tracked accurately. 36 /// Basic block live-in lists, kill flags, and implicit defs may not be 37 /// accurate when after this flag is cleared. 38 bool TracksLiveness; 39 40 /// VRegInfo - Information we keep for each virtual register. 41 /// 42 /// Each element in this list contains the register class of the vreg and the 43 /// start of the use/def list for the register. 44 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 45 VirtReg2IndexFunctor> VRegInfo; 46 47 /// RegAllocHints - This vector records register allocation hints for virtual 48 /// registers. For each virtual register, it keeps a register and hint type 49 /// pair making up the allocation hint. Hint type is target specific except 50 /// for the value 0 which means the second value of the pair is the preferred 51 /// register for allocation. For example, if the hint is <0, 1024>, it means 52 /// the allocator should prefer the physical register allocated to the virtual 53 /// register of the hint. 54 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 55 56 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 57 /// physical registers. 58 MachineOperand **PhysRegUseDefLists; 59 60 /// getRegUseDefListHead - Return the head pointer for the register use/def 61 /// list for the specified virtual or physical register. 62 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 63 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 64 return VRegInfo[RegNo].second; 65 return PhysRegUseDefLists[RegNo]; 66 } 67 68 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 69 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 70 return VRegInfo[RegNo].second; 71 return PhysRegUseDefLists[RegNo]; 72 } 73 74 /// Get the next element in the use-def chain. 75 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { 76 assert(MO && MO->isReg() && "This is not a register operand!"); 77 return MO->Contents.Reg.Next; 78 } 79 80 /// UsedPhysRegs - This is a bit vector that is computed and set by the 81 /// register allocator, and must be kept up to date by passes that run after 82 /// register allocation (though most don't modify this). This is used 83 /// so that the code generator knows which callee save registers to save and 84 /// for other target specific uses. 85 /// This vector only has bits set for registers explicitly used, not their 86 /// aliases. 87 BitVector UsedPhysRegs; 88 89 /// UsedPhysRegMask - Additional used physregs, but including aliases. 90 BitVector UsedPhysRegMask; 91 92 /// ReservedRegs - This is a bit vector of reserved registers. The target 93 /// may change its mind about which registers should be reserved. This 94 /// vector is the frozen set of reserved registers when register allocation 95 /// started. 96 BitVector ReservedRegs; 97 98 /// LiveIns/LiveOuts - Keep track of the physical registers that are 99 /// livein/liveout of the function. Live in values are typically arguments in 100 /// registers, live out values are typically return values in registers. 101 /// LiveIn values are allowed to have virtual registers associated with them, 102 /// stored in the second element. 103 std::vector<std::pair<unsigned, unsigned> > LiveIns; 104 std::vector<unsigned> LiveOuts; 105 106 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 107 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION; 108public: 109 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 110 ~MachineRegisterInfo(); 111 112 //===--------------------------------------------------------------------===// 113 // Function State 114 //===--------------------------------------------------------------------===// 115 116 // isSSA - Returns true when the machine function is in SSA form. Early 117 // passes require the machine function to be in SSA form where every virtual 118 // register has a single defining instruction. 119 // 120 // The TwoAddressInstructionPass and PHIElimination passes take the machine 121 // function out of SSA form when they introduce multiple defs per virtual 122 // register. 123 bool isSSA() const { return IsSSA; } 124 125 // leaveSSA - Indicates that the machine function is no longer in SSA form. 126 void leaveSSA() { IsSSA = false; } 127 128 /// tracksLiveness - Returns true when tracking register liveness accurately. 129 /// 130 /// While this flag is true, register liveness information in basic block 131 /// live-in lists and machine instruction operands is accurate. This means it 132 /// can be used to change the code in ways that affect the values in 133 /// registers, for example by the register scavenger. 134 /// 135 /// When this flag is false, liveness is no longer reliable. 136 bool tracksLiveness() const { return TracksLiveness; } 137 138 /// invalidateLiveness - Indicates that register liveness is no longer being 139 /// tracked accurately. 140 /// 141 /// This should be called by late passes that invalidate the liveness 142 /// information. 143 void invalidateLiveness() { TracksLiveness = false; } 144 145 //===--------------------------------------------------------------------===// 146 // Register Info 147 //===--------------------------------------------------------------------===// 148 149 // Strictly for use by MachineInstr.cpp. 150 void addRegOperandToUseList(MachineOperand *MO); 151 152 // Strictly for use by MachineInstr.cpp. 153 void removeRegOperandFromUseList(MachineOperand *MO); 154 155 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 156 /// and uses of a register within the MachineFunction that corresponds to this 157 /// MachineRegisterInfo object. 158 template<bool Uses, bool Defs, bool SkipDebug> 159 class defusechain_iterator; 160 161 // Make it a friend so it can access getNextOperandForReg(). 162 template<bool, bool, bool> friend class defusechain_iterator; 163 164 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 165 /// register. 166 typedef defusechain_iterator<true,true,false> reg_iterator; 167 reg_iterator reg_begin(unsigned RegNo) const { 168 return reg_iterator(getRegUseDefListHead(RegNo)); 169 } 170 static reg_iterator reg_end() { return reg_iterator(0); } 171 172 /// reg_empty - Return true if there are no instructions using or defining the 173 /// specified register (it may be live-in). 174 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 175 176 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 177 /// of the specified register, skipping those marked as Debug. 178 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 179 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 180 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 181 } 182 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 183 184 /// reg_nodbg_empty - Return true if the only instructions using or defining 185 /// Reg are Debug instructions. 186 bool reg_nodbg_empty(unsigned RegNo) const { 187 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 188 } 189 190 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 191 typedef defusechain_iterator<false,true,false> def_iterator; 192 def_iterator def_begin(unsigned RegNo) const { 193 return def_iterator(getRegUseDefListHead(RegNo)); 194 } 195 static def_iterator def_end() { return def_iterator(0); } 196 197 /// def_empty - Return true if there are no instructions defining the 198 /// specified register (it may be live-in). 199 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 200 201 /// hasOneDef - Return true if there is exactly one instruction defining the 202 /// specified register. 203 bool hasOneDef(unsigned RegNo) const { 204 def_iterator DI = def_begin(RegNo); 205 if (DI == def_end()) 206 return false; 207 return ++DI == def_end(); 208 } 209 210 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 211 typedef defusechain_iterator<true,false,false> use_iterator; 212 use_iterator use_begin(unsigned RegNo) const { 213 return use_iterator(getRegUseDefListHead(RegNo)); 214 } 215 static use_iterator use_end() { return use_iterator(0); } 216 217 /// use_empty - Return true if there are no instructions using the specified 218 /// register. 219 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 220 221 /// hasOneUse - Return true if there is exactly one instruction using the 222 /// specified register. 223 bool hasOneUse(unsigned RegNo) const { 224 use_iterator UI = use_begin(RegNo); 225 if (UI == use_end()) 226 return false; 227 return ++UI == use_end(); 228 } 229 230 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 231 /// specified register, skipping those marked as Debug. 232 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 233 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 234 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 235 } 236 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 237 238 /// use_nodbg_empty - Return true if there are no non-Debug instructions 239 /// using the specified register. 240 bool use_nodbg_empty(unsigned RegNo) const { 241 return use_nodbg_begin(RegNo) == use_nodbg_end(); 242 } 243 244 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 245 /// instruction using the specified register. 246 bool hasOneNonDBGUse(unsigned RegNo) const; 247 248 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 249 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 250 /// except that it also changes any definitions of the register as well. 251 /// 252 /// Note that it is usually necessary to first constrain ToReg's register 253 /// class to match the FromReg constraints using: 254 /// 255 /// constrainRegClass(ToReg, getRegClass(FromReg)) 256 /// 257 /// That function will return NULL if the virtual registers have incompatible 258 /// constraints. 259 void replaceRegWith(unsigned FromReg, unsigned ToReg); 260 261 /// getVRegDef - Return the machine instr that defines the specified virtual 262 /// register or null if none is found. This assumes that the code is in SSA 263 /// form, so there should only be one definition. 264 MachineInstr *getVRegDef(unsigned Reg) const; 265 266 /// getUniqueVRegDef - Return the unique machine instr that defines the 267 /// specified virtual register or null if none is found. If there are 268 /// multiple definitions or no definition, return null. 269 MachineInstr *getUniqueVRegDef(unsigned Reg) const; 270 271 /// clearKillFlags - Iterate over all the uses of the given register and 272 /// clear the kill flag from the MachineOperand. This function is used by 273 /// optimization passes which extend register lifetimes and need only 274 /// preserve conservative kill flag information. 275 void clearKillFlags(unsigned Reg) const; 276 277#ifndef NDEBUG 278 void dumpUses(unsigned RegNo) const; 279#endif 280 281 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 282 /// throughout the function. It is safe to move instructions that read such 283 /// a physreg. 284 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 285 286 //===--------------------------------------------------------------------===// 287 // Virtual Register Info 288 //===--------------------------------------------------------------------===// 289 290 /// getRegClass - Return the register class of the specified virtual register. 291 /// 292 const TargetRegisterClass *getRegClass(unsigned Reg) const { 293 return VRegInfo[Reg].first; 294 } 295 296 /// setRegClass - Set the register class of the specified virtual register. 297 /// 298 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 299 300 /// constrainRegClass - Constrain the register class of the specified virtual 301 /// register to be a common subclass of RC and the current register class, 302 /// but only if the new class has at least MinNumRegs registers. Return the 303 /// new register class, or NULL if no such class exists. 304 /// This should only be used when the constraint is known to be trivial, like 305 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 306 /// 307 const TargetRegisterClass *constrainRegClass(unsigned Reg, 308 const TargetRegisterClass *RC, 309 unsigned MinNumRegs = 0); 310 311 /// recomputeRegClass - Try to find a legal super-class of Reg's register 312 /// class that still satisfies the constraints from the instructions using 313 /// Reg. Returns true if Reg was upgraded. 314 /// 315 /// This method can be used after constraints have been removed from a 316 /// virtual register, for example after removing instructions or splitting 317 /// the live range. 318 /// 319 bool recomputeRegClass(unsigned Reg, const TargetMachine&); 320 321 /// createVirtualRegister - Create and return a new virtual register in the 322 /// function with the specified register class. 323 /// 324 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 325 326 /// getNumVirtRegs - Return the number of virtual registers created. 327 /// 328 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 329 330 /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 331 void clearVirtRegs(); 332 333 /// setRegAllocationHint - Specify a register allocation hint for the 334 /// specified virtual register. 335 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 336 RegAllocHints[Reg].first = Type; 337 RegAllocHints[Reg].second = PrefReg; 338 } 339 340 /// getRegAllocationHint - Return the register allocation hint for the 341 /// specified virtual register. 342 std::pair<unsigned, unsigned> 343 getRegAllocationHint(unsigned Reg) const { 344 return RegAllocHints[Reg]; 345 } 346 347 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 348 /// standard simple hint (Type == 0) is not set. 349 unsigned getSimpleHint(unsigned Reg) const { 350 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 351 return Hint.first ? 0 : Hint.second; 352 } 353 354 355 //===--------------------------------------------------------------------===// 356 // Physical Register Use Info 357 //===--------------------------------------------------------------------===// 358 359 /// isPhysRegUsed - Return true if the specified register is used in this 360 /// function. Also check for clobbered aliases and registers clobbered by 361 /// function calls with register mask operands. 362 /// 363 /// This only works after register allocation. It is primarily used by 364 /// PrologEpilogInserter to determine which callee-saved registers need 365 /// spilling. 366 bool isPhysRegUsed(unsigned Reg) const { 367 if (UsedPhysRegMask.test(Reg)) 368 return true; 369 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 370 if (UsedPhysRegs.test(*AI)) 371 return true; 372 return false; 373 } 374 375 /// setPhysRegUsed - Mark the specified register used in this function. 376 /// This should only be called during and after register allocation. 377 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); } 378 379 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 380 /// This corresponds to the bit mask attached to register mask operands. 381 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 382 UsedPhysRegMask.setBitsNotInMask(RegMask); 383 } 384 385 /// setPhysRegUnused - Mark the specified register unused in this function. 386 /// This should only be called during and after register allocation. 387 void setPhysRegUnused(unsigned Reg) { 388 UsedPhysRegs.reset(Reg); 389 UsedPhysRegMask.reset(Reg); 390 } 391 392 393 //===--------------------------------------------------------------------===// 394 // Reserved Register Info 395 //===--------------------------------------------------------------------===// 396 // 397 // The set of reserved registers must be invariant during register 398 // allocation. For example, the target cannot suddenly decide it needs a 399 // frame pointer when the register allocator has already used the frame 400 // pointer register for something else. 401 // 402 // These methods can be used by target hooks like hasFP() to avoid changing 403 // the reserved register set during register allocation. 404 405 /// freezeReservedRegs - Called by the register allocator to freeze the set 406 /// of reserved registers before allocation begins. 407 void freezeReservedRegs(const MachineFunction&); 408 409 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 410 /// to ensure the set of reserved registers stays constant. 411 bool reservedRegsFrozen() const { 412 return !ReservedRegs.empty(); 413 } 414 415 /// canReserveReg - Returns true if PhysReg can be used as a reserved 416 /// register. Any register can be reserved before freezeReservedRegs() is 417 /// called. 418 bool canReserveReg(unsigned PhysReg) const { 419 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 420 } 421 422 /// getReservedRegs - Returns a reference to the frozen set of reserved 423 /// registers. This method should always be preferred to calling 424 /// TRI::getReservedRegs() when possible. 425 const BitVector &getReservedRegs() const { 426 assert(reservedRegsFrozen() && 427 "Reserved registers haven't been frozen yet. " 428 "Use TRI::getReservedRegs()."); 429 return ReservedRegs; 430 } 431 432 /// isReserved - Returns true when PhysReg is a reserved register. 433 /// 434 /// Reserved registers may belong to an allocatable register class, but the 435 /// target has explicitly requested that they are not used. 436 /// 437 bool isReserved(unsigned PhysReg) const { 438 return getReservedRegs().test(PhysReg); 439 } 440 441 /// isAllocatable - Returns true when PhysReg belongs to an allocatable 442 /// register class and it hasn't been reserved. 443 /// 444 /// Allocatable registers may show up in the allocation order of some virtual 445 /// register, so a register allocator needs to track its liveness and 446 /// availability. 447 bool isAllocatable(unsigned PhysReg) const { 448 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg); 449 } 450 451 //===--------------------------------------------------------------------===// 452 // LiveIn/LiveOut Management 453 //===--------------------------------------------------------------------===// 454 455 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 456 /// is an error to add the same register to the same set more than once. 457 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 458 LiveIns.push_back(std::make_pair(Reg, vreg)); 459 } 460 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 461 462 // Iteration support for live in/out sets. These sets are kept in sorted 463 // order by their register number. 464 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 465 livein_iterator; 466 typedef std::vector<unsigned>::const_iterator liveout_iterator; 467 livein_iterator livein_begin() const { return LiveIns.begin(); } 468 livein_iterator livein_end() const { return LiveIns.end(); } 469 bool livein_empty() const { return LiveIns.empty(); } 470 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 471 liveout_iterator liveout_end() const { return LiveOuts.end(); } 472 bool liveout_empty() const { return LiveOuts.empty(); } 473 474 bool isLiveIn(unsigned Reg) const; 475 bool isLiveOut(unsigned Reg) const; 476 477 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 478 /// corresponding live-in physical register. 479 unsigned getLiveInPhysReg(unsigned VReg) const; 480 481 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 482 /// corresponding live-in physical register. 483 unsigned getLiveInVirtReg(unsigned PReg) const; 484 485 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 486 /// into the given entry block. 487 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 488 const TargetRegisterInfo &TRI, 489 const TargetInstrInfo &TII); 490 491 /// defusechain_iterator - This class provides iterator support for machine 492 /// operands in the function that use or define a specific register. If 493 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 494 /// returns defs. If neither are true then you are silly and it always 495 /// returns end(). If SkipDebug is true it skips uses marked Debug 496 /// when incrementing. 497 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 498 class defusechain_iterator 499 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 500 MachineOperand *Op; 501 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 502 // If the first node isn't one we're interested in, advance to one that 503 // we are interested in. 504 if (op) { 505 if ((!ReturnUses && op->isUse()) || 506 (!ReturnDefs && op->isDef()) || 507 (SkipDebug && op->isDebug())) 508 ++*this; 509 } 510 } 511 friend class MachineRegisterInfo; 512 public: 513 typedef std::iterator<std::forward_iterator_tag, 514 MachineInstr, ptrdiff_t>::reference reference; 515 typedef std::iterator<std::forward_iterator_tag, 516 MachineInstr, ptrdiff_t>::pointer pointer; 517 518 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 519 defusechain_iterator() : Op(0) {} 520 521 bool operator==(const defusechain_iterator &x) const { 522 return Op == x.Op; 523 } 524 bool operator!=(const defusechain_iterator &x) const { 525 return !operator==(x); 526 } 527 528 /// atEnd - return true if this iterator is equal to reg_end() on the value. 529 bool atEnd() const { return Op == 0; } 530 531 // Iterator traversal: forward iteration only 532 defusechain_iterator &operator++() { // Preincrement 533 assert(Op && "Cannot increment end iterator!"); 534 Op = getNextOperandForReg(Op); 535 536 // All defs come before the uses, so stop def_iterator early. 537 if (!ReturnUses) { 538 if (Op) { 539 if (Op->isUse()) 540 Op = 0; 541 else 542 assert(!Op->isDebug() && "Can't have debug defs"); 543 } 544 } else { 545 // If this is an operand we don't care about, skip it. 546 while (Op && ((!ReturnDefs && Op->isDef()) || 547 (SkipDebug && Op->isDebug()))) 548 Op = getNextOperandForReg(Op); 549 } 550 551 return *this; 552 } 553 defusechain_iterator operator++(int) { // Postincrement 554 defusechain_iterator tmp = *this; ++*this; return tmp; 555 } 556 557 /// skipInstruction - move forward until reaching a different instruction. 558 /// Return the skipped instruction that is no longer pointed to, or NULL if 559 /// already pointing to end(). 560 MachineInstr *skipInstruction() { 561 if (!Op) return 0; 562 MachineInstr *MI = Op->getParent(); 563 do ++*this; 564 while (Op && Op->getParent() == MI); 565 return MI; 566 } 567 568 MachineInstr *skipBundle() { 569 if (!Op) return 0; 570 MachineInstr *MI = getBundleStart(Op->getParent()); 571 do ++*this; 572 while (Op && getBundleStart(Op->getParent()) == MI); 573 return MI; 574 } 575 576 MachineOperand &getOperand() const { 577 assert(Op && "Cannot dereference end iterator!"); 578 return *Op; 579 } 580 581 /// getOperandNo - Return the operand # of this MachineOperand in its 582 /// MachineInstr. 583 unsigned getOperandNo() const { 584 assert(Op && "Cannot dereference end iterator!"); 585 return Op - &Op->getParent()->getOperand(0); 586 } 587 588 // Retrieve a reference to the current operand. 589 MachineInstr &operator*() const { 590 assert(Op && "Cannot dereference end iterator!"); 591 return *Op->getParent(); 592 } 593 594 MachineInstr *operator->() const { 595 assert(Op && "Cannot dereference end iterator!"); 596 return Op->getParent(); 597 } 598 }; 599 600}; 601 602} // End llvm namespace 603 604#endif 605