MachineRegisterInfo.h revision a91a7d594ff1e1503731ca92f72e627bdfd18f3f 
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
16
17#include "llvm/Target/MRegisterInfo.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/iterator"
20#include <vector>
21
22namespace llvm {
23
24/// MachineRegisterInfo - Keep track of information for each virtual register,
25/// including its register class.
26class MachineRegisterInfo {
27  /// VRegInfo - Information we keep for each virtual register.  The entries in
28  /// this vector are actually converted to vreg numbers by adding the
29  /// MRegisterInfo::FirstVirtualRegister delta to their index.
30  ///
31  /// Each element in this list contains the register class of the vreg and the
32  /// start of the use/def list for the register.
33  std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
34
35  /// PhysRegUseDefLists - This is an array of the head of the use/def list for
36  /// physical registers.
37  MachineOperand **PhysRegUseDefLists;
38
39  /// UsedPhysRegs - This is a bit vector that is computed and set by the
40  /// register allocator, and must be kept up to date by passes that run after
41  /// register allocation (though most don't modify this).  This is used
42  /// so that the code generator knows which callee save registers to save and
43  /// for other target specific uses.
44  BitVector UsedPhysRegs;
45
46  /// LiveIns/LiveOuts - Keep track of the physical registers that are
47  /// livein/liveout of the function.  Live in values are typically arguments in
48  /// registers, live out values are typically return values in registers.
49  /// LiveIn values are allowed to have virtual registers associated with them,
50  /// stored in the second element.
51  std::vector<std::pair<unsigned, unsigned> > LiveIns;
52  std::vector<unsigned> LiveOuts;
53
54  MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
55  void operator=(const MachineRegisterInfo&);      // DO NOT IMPLEMENT
56public:
57  MachineRegisterInfo(const MRegisterInfo &MRI);
58  ~MachineRegisterInfo();
59
60  //===--------------------------------------------------------------------===//
61  // Register Info
62  //===--------------------------------------------------------------------===//
63
64  /// reg_begin/reg_end - Provide iteration support to walk over all definitions
65  /// and uses of a register within the MachineFunction that corresponds to this
66  /// MachineRegisterInfo object.
67  class reg_iterator;
68  reg_iterator reg_begin(unsigned RegNo) const {
69    return reg_iterator(getRegUseDefListHead(RegNo));
70  }
71  static reg_iterator reg_end() { return reg_iterator(0); }
72
73  /// getRegUseDefListHead - Return the head pointer for the register use/def
74  /// list for the specified virtual or physical register.
75  MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
76    if (RegNo < MRegisterInfo::FirstVirtualRegister)
77      return PhysRegUseDefLists[RegNo];
78    RegNo -= MRegisterInfo::FirstVirtualRegister;
79    return VRegInfo[RegNo].second;
80  }
81
82  MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
83    if (RegNo < MRegisterInfo::FirstVirtualRegister)
84      return PhysRegUseDefLists[RegNo];
85    RegNo -= MRegisterInfo::FirstVirtualRegister;
86    return VRegInfo[RegNo].second;
87  }
88
89  //===--------------------------------------------------------------------===//
90  // Virtual Register Info
91  //===--------------------------------------------------------------------===//
92
93  /// getRegClass - Return the register class of the specified virtual register.
94  const TargetRegisterClass *getRegClass(unsigned Reg) {
95    Reg -= MRegisterInfo::FirstVirtualRegister;
96    assert(Reg < VRegInfo.size() && "Invalid vreg!");
97    return VRegInfo[Reg].first;
98  }
99
100  /// createVirtualRegister - Create and return a new virtual register in the
101  /// function with the specified register class.
102  ///
103  unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
104    assert(RegClass && "Cannot create register without RegClass!");
105    // Add a reg, but keep track of whether the vector reallocated or not.
106    void *ArrayBase = &VRegInfo[0];
107    VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
108
109    if (&VRegInfo[0] == ArrayBase)
110      return getLastVirtReg();
111
112    // Otherwise, the vector reallocated, handle this now.
113    HandleVRegListReallocation();
114    return getLastVirtReg();
115  }
116
117  /// getLastVirtReg - Return the highest currently assigned virtual register.
118  ///
119  unsigned getLastVirtReg() const {
120    return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
121  }
122
123  /// getVRegDef - Return the machine instr that defines the specified virtual
124  /// register or null if none is found.  This assumes that the code is in SSA
125  /// form, so there should only be one definition.
126  MachineInstr *getVRegDef(unsigned Reg) const;
127
128
129  //===--------------------------------------------------------------------===//
130  // Physical Register Use Info
131  //===--------------------------------------------------------------------===//
132
133  /// isPhysRegUsed - Return true if the specified register is used in this
134  /// function.  This only works after register allocation.
135  bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
136
137  /// setPhysRegUsed - Mark the specified register used in this function.
138  /// This should only be called during and after register allocation.
139  void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
140
141  /// setPhysRegUnused - Mark the specified register unused in this function.
142  /// This should only be called during and after register allocation.
143  void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
144
145
146  //===--------------------------------------------------------------------===//
147  // LiveIn/LiveOut Management
148  //===--------------------------------------------------------------------===//
149
150  /// addLiveIn/Out - Add the specified register as a live in/out.  Note that it
151  /// is an error to add the same register to the same set more than once.
152  void addLiveIn(unsigned Reg, unsigned vreg = 0) {
153    LiveIns.push_back(std::make_pair(Reg, vreg));
154  }
155  void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
156
157  // Iteration support for live in/out sets.  These sets are kept in sorted
158  // order by their register number.
159  typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
160  livein_iterator;
161  typedef std::vector<unsigned>::const_iterator liveout_iterator;
162  livein_iterator livein_begin() const { return LiveIns.begin(); }
163  livein_iterator livein_end()   const { return LiveIns.end(); }
164  bool            livein_empty() const { return LiveIns.empty(); }
165  liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
166  liveout_iterator liveout_end()   const { return LiveOuts.end(); }
167  bool             liveout_empty() const { return LiveOuts.empty(); }
168private:
169  void HandleVRegListReallocation();
170
171public:
172  /// reg_iterator - This class provides iterator support for machine
173  /// operands in the function that use or define a specific register.
174  class reg_iterator : public forward_iterator<MachineOperand, ptrdiff_t> {
175    typedef forward_iterator<MachineOperand, ptrdiff_t> super;
176
177    MachineOperand *Op;
178    reg_iterator(MachineOperand *op) : Op(op) {}
179    friend class MachineRegisterInfo;
180  public:
181    typedef super::reference reference;
182    typedef super::pointer pointer;
183
184    reg_iterator(const reg_iterator &I) : Op(I.Op) {}
185    reg_iterator() : Op(0) {}
186
187    bool operator==(const reg_iterator &x) const {
188      return Op == x.Op;
189    }
190    bool operator!=(const reg_iterator &x) const {
191      return !operator==(x);
192    }
193
194    /// atEnd - return true if this iterator is equal to reg_end() on the value.
195    bool atEnd() const { return Op == 0; }
196
197    // Iterator traversal: forward iteration only
198    reg_iterator &operator++() {          // Preincrement
199      assert(Op && "Cannot increment end iterator!");
200      Op = Op->getNextOperandForReg();
201      return *this;
202    }
203    reg_iterator operator++(int) {        // Postincrement
204      reg_iterator tmp = *this; ++*this; return tmp;
205    }
206
207    // Retrieve a reference to the current operand.
208    MachineOperand &operator*() const {
209      assert(Op && "Cannot dereference end iterator!");
210      return *Op;
211    }
212
213    MachineOperand *operator->() const { return Op; }
214  };
215
216};
217
218} // End llvm namespace
219
220#endif
221