MachineRegisterInfo.h revision d9e5c764bfea339fc5082bf17e558db959fd6d28
12a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 72a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 82a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 92a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// 102a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// This file defines the MachineRegisterInfo class. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===----------------------------------------------------------------------===// 132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 14c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Target/TargetRegisterInfo.h" 1890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles)#include "llvm/ADT/BitVector.h" 192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#include "llvm/ADT/IndexedMap.h" 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include <vector> 212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)namespace llvm { 232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// MachineRegisterInfo - Keep track of information for virtual and physical 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// registers, including vreg register classes, use/def chains for registers, 262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// etc. 272a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)class MachineRegisterInfo { 2890dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) const TargetRegisterInfo *const TRI; 292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// IsSSA - True when the machine function is in SSA form and virtual 312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// registers have a single def. 322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool IsSSA; 332a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// VRegInfo - Information we keep for each virtual register. 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Each element in this list contains the register class of the vreg and the 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// start of the use/def list for the register. 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) VirtReg2IndexFunctor> VRegInfo; 402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// RegAllocHints - This vector records register allocation hints for virtual 422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// registers. For each virtual register, it keeps a register and hint type 432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// pair making up the allocation hint. Hint type is target specific except 442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// for the value 0 which means the second value of the pair is the preferred 452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register for allocation. For example, if the hint is <0, 1024>, it means 462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// the allocator should prefer the physical register allocated to the virtual 472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register of the hint. 482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// PhysRegUseDefLists - This is an array of the head of the use/def list for 512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// physical registers. 522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineOperand **PhysRegUseDefLists; 532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// UsedPhysRegs - This is a bit vector that is computed and set by the 552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register allocator, and must be kept up to date by passes that run after 562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register allocation (though most don't modify this). This is used 572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// so that the code generator knows which callee save registers to save and 582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// for other target specific uses. 592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) BitVector UsedPhysRegs; 602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// ReservedRegs - This is a bit vector of reserved registers. The target 622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// may change its mind about which registers should be reserved. This 632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// vector is the frozen set of reserved registers when register allocation 642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// started. 652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) BitVector ReservedRegs; 662a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 672a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// LiveIns/LiveOuts - Keep track of the physical registers that are 682a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// livein/liveout of the function. Live in values are typically arguments in 692a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// registers, live out values are typically return values in registers. 702a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// LiveIn values are allowed to have virtual registers associated with them, 71b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// stored in the second element. 72b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) std::vector<std::pair<unsigned, unsigned> > LiveIns; 73b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) std::vector<unsigned> LiveOuts; 74b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 75b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)public: 782a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 792a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) ~MachineRegisterInfo(); 802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 822a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Function State 832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // isSSA - Returns true when the machine function is in SSA form. Early 862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // passes require the machine function to be in SSA form where every virtual 872a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // register has a single defining instruction. 882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // 892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // The TwoAddressInstructionPass and PHIElimination passes take the machine 902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // function out of SSA form when they introduce multiple defs per virtual 912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // register. 922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool isSSA() const { return IsSSA; } 932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 942a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // leaveSSA - Indicates that the machine function is no longer in SSA form. 952a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void leaveSSA() { IsSSA = false; } 962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 982a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Register Info 992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 1002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reg_begin/reg_end - Provide iteration support to walk over all definitions 1022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// and uses of a register within the MachineFunction that corresponds to this 1032a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MachineRegisterInfo object. 1042a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) template<bool Uses, bool Defs, bool SkipDebug> 1052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) class defusechain_iterator; 1062a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1072a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 1082a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register. 1092a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) typedef defusechain_iterator<true,true,false> reg_iterator; 1102a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) reg_iterator reg_begin(unsigned RegNo) const { 1112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return reg_iterator(getRegUseDefListHead(RegNo)); 1122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 1132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) static reg_iterator reg_end() { return reg_iterator(0); } 1142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reg_empty - Return true if there are no instructions using or defining the 1162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// specified register (it may be live-in). 1172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 1182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 1202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// of the specified register, skipping those marked as Debug. 1215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 12290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 1235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 1245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 1265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 12790dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// reg_nodbg_empty - Return true if the only instructions using or defining 1285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Reg are Debug instructions. 1295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool reg_nodbg_empty(unsigned RegNo) const { 1305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 1312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 1322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 1345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef defusechain_iterator<false,true,false> def_iterator; 1352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) def_iterator def_begin(unsigned RegNo) const { 1362a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return def_iterator(getRegUseDefListHead(RegNo)); 1372a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 1382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) static def_iterator def_end() { return def_iterator(0); } 1392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// def_empty - Return true if there are no instructions defining the 1412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// specified register (it may be live-in). 1422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 143b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 144b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 1452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) typedef defusechain_iterator<true,false,false> use_iterator; 1462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) use_iterator use_begin(unsigned RegNo) const { 1475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return use_iterator(getRegUseDefListHead(RegNo)); 1485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static use_iterator use_end() { return use_iterator(0); } 1505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// use_empty - Return true if there are no instructions using the specified 1525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register. 1535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 1545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasOneUse - Return true if there is exactly one instruction using the 1565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified register. 1572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool hasOneUse(unsigned RegNo) const; 1582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 1602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// specified register, skipping those marked as Debug. 1612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 1622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 1632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 1642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 1655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// use_nodbg_empty - Return true if there are no non-Debug instructions 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// using the specified register. 1695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool use_nodbg_empty(unsigned RegNo) const { 1705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return use_nodbg_begin(RegNo) == use_nodbg_end(); 1715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 1745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction using the specified register. 1755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool hasOneNonDBGUse(unsigned RegNo) const; 1765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// replaceRegWith - Replace all instances of FromReg with ToReg in the 1785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// except that it also changes any definitions of the register as well. 1805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Note that it is usually necessary to first constrain ToReg's register 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// class to match the FromReg constraints using: 1832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// constrainRegClass(ToReg, getRegClass(FromReg)) 1852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 1862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// That function will return NULL if the virtual registers have incompatible 1872a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// constraints. 1882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void replaceRegWith(unsigned FromReg, unsigned ToReg); 1892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 1902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// getRegUseDefListHead - Return the head pointer for the register use/def 1912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// list for the specified virtual or physical register. 1922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (TargetRegisterInfo::isVirtualRegister(RegNo)) 1942a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return VRegInfo[RegNo].second; 1955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return PhysRegUseDefLists[RegNo]; 1965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if (TargetRegisterInfo::isVirtualRegister(RegNo)) 2002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return VRegInfo[RegNo].second; 2012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return PhysRegUseDefLists[RegNo]; 2025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2042a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// getVRegDef - Return the machine instr that defines the specified virtual 2052a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register or null if none is found. This assumes that the code is in SSA 2062a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// form, so there should only be one definition. 2072a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineInstr *getVRegDef(unsigned Reg) const; 2082a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2092a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// clearKillFlags - Iterate over all the uses of the given register and 2105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// clear the kill flag from the MachineOperand. This function is used by 2112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// optimization passes which extend register lifetimes and need only 2122a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// preserve conservative kill flag information. 2132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void clearKillFlags(unsigned Reg) const; 2142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#ifndef NDEBUG 2162a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void dumpUses(unsigned RegNo) const; 2172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)#endif 2182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 2202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Virtual Register Info 2212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 2222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 223b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// getRegClass - Return the register class of the specified virtual register. 224b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// 225b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) const TargetRegisterClass *getRegClass(unsigned Reg) const { 2262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return VRegInfo[Reg].first; 2272a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 2282a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2292a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// setRegClass - Set the register class of the specified virtual register. 2302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2312a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 2325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// constrainRegClass - Constrain the register class of the specified virtual 2345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register to be a common subclass of RC and the current register class, 2355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// but only if the new class has at least MinNumRegs registers. Return the 2365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// new register class, or NULL if no such class exists. 2375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This should only be used when the constraint is known to be trivial, like 2385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 2395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *constrainRegClass(unsigned Reg, 2412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const TargetRegisterClass *RC, 2422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) unsigned MinNumRegs = 0); 2432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// recomputeRegClass - Try to find a legal super-class of Reg's register 2452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// class that still satisfies the constraints from the instructions using 2462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// Reg. Returns true if Reg was upgraded. 2472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// This method can be used after constraints have been removed from a 2492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// virtual register, for example after removing instructions or splitting 2502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// the live range. 2512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool recomputeRegClass(unsigned Reg, const TargetMachine&); 2532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 2542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// createVirtualRegister - Create and return a new virtual register in the 2552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// function with the specified register class. 2562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// 2575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 2585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getNumVirtRegs - Return the number of virtual registers created. 2605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getNumVirtRegs() const { return VRegInfo.size(); } 2625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// setRegAllocationHint - Specify a register allocation hint for the 2645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified virtual register. 2655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 2665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegAllocHints[Reg].first = Type; 2675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegAllocHints[Reg].second = PrefReg; 2685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegAllocationHint - Return the register allocation hint for the 2715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified virtual register. 2725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::pair<unsigned, unsigned> 2735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) getRegAllocationHint(unsigned Reg) const { 2745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return RegAllocHints[Reg]; 2755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 2785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// standard simple hint (Type == 0) is not set. 2795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getSimpleHint(unsigned Reg) const { 2805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 2815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Hint.first ? 0 : Hint.second; 2825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 2865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Physical Register Use Info 2875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 2885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isPhysRegUsed - Return true if the specified register is used in this 2905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// function. This only works after register allocation. 2915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 2925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register 2945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// is used in this function. 2955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isPhysRegOrOverlapUsed(unsigned Reg) const { 2965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) for (const unsigned *AI = TRI->getOverlaps(Reg); *AI; ++AI) 2975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (isPhysRegUsed(*AI)) 2985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return true; 2995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return false; 3005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// setPhysRegUsed - Mark the specified register used in this function. 3035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This should only be called during and after register allocation. 3045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 3055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// addPhysRegsUsed - Mark the specified registers used in this function. 3075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This should only be called during and after register allocation. 3085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 3095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// setPhysRegUnused - Mark the specified register unused in this function. 3115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This should only be called during and after register allocation. 3125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 3135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 3152a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// subregisters. That means that if R is used, so are all subregisters. 316b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) void closePhysRegsUsed(const TargetRegisterInfo&); 3172a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3182a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3192a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 3202a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Reserved Register Info 3212a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 3222a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // 3232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // The set of reserved registers must be invariant during register 3242a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // allocation. For example, the target cannot suddenly decide it needs a 3252a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // frame pointer when the register allocator has already used the frame 3262a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // pointer register for something else. 3272a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // 328b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) // These methods can be used by target hooks like hasFP() to avoid changing 329b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) // the reserved register set during register allocation. 33090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 331b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// freezeReservedRegs - Called by the register allocator to freeze the set 33290dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// of reserved registers before allocation begins. 33390dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) void freezeReservedRegs(const MachineFunction&); 33490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 335b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 336b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) /// to ensure the set of reserved registers stays constant. 337b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) bool reservedRegsFrozen() const { 3382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return !ReservedRegs.empty(); 3392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 3402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// canReserveReg - Returns true if PhysReg can be used as a reserved 3422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// register. Any register can be reserved before freezeReservedRegs() is 3432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// called. 3442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) bool canReserveReg(unsigned PhysReg) const { 3452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 3462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 3472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 3502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // LiveIn/LiveOut Management 3512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) //===--------------------------------------------------------------------===// 3522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 3542a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// is an error to add the same register to the same set more than once. 3552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void addLiveIn(unsigned Reg, unsigned vreg = 0) { 3562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) LiveIns.push_back(std::make_pair(Reg, vreg)); 3572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 3582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 3592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Iteration support for live in/out sets. These sets are kept in sorted 3612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // order by their register number. 3622a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 3635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) livein_iterator; 3645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef std::vector<unsigned>::const_iterator liveout_iterator; 3655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) livein_iterator livein_begin() const { return LiveIns.begin(); } 3665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) livein_iterator livein_end() const { return LiveIns.end(); } 3675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool livein_empty() const { return LiveIns.empty(); } 3685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 3695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) liveout_iterator liveout_end() const { return LiveOuts.end(); } 3705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool liveout_empty() const { return LiveOuts.empty(); } 3715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isLiveIn(unsigned Reg) const; 3735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isLiveOut(unsigned Reg) const; 37490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) 37590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 37690dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// corresponding live-in physical register. 3775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getLiveInPhysReg(unsigned VReg) const; 3785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getLiveInVirtReg - If PReg is a live-in physical register, return the 38090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) /// corresponding live-in physical register. 38190dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) unsigned getLiveInVirtReg(unsigned PReg) const; 382c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 383c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 3845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// into the given entry block. 3855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 3862a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const TargetRegisterInfo &TRI, 387c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) const TargetInstrInfo &TII); 3882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)private: 3902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void HandleVRegListReallocation(); 3912a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 3922a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)public: 3932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// defusechain_iterator - This class provides iterator support for machine 394c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// operands in the function that use or define a specific register. If 3952a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 3962a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// returns defs. If neither are true then you are silly and it always 3972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// returns end(). If SkipDebug is true it skips uses marked Debug 3982a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// when incrementing. 399c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 4002a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) class defusechain_iterator 4012a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 4022a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineOperand *Op; 403c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) explicit defusechain_iterator(MachineOperand *op) : Op(op) { 404c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // If the first node isn't one we're interested in, advance to one that 405c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) // we are interested in. 406c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (op) { 4072a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) if ((!ReturnUses && op->isUse()) || 4082a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) (!ReturnDefs && op->isDef()) || 409c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) (SkipDebug && op->isDebug())) 410c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) ++*this; 411c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 412c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 4132a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) friend class MachineRegisterInfo; 4142a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) public: 415b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) typedef std::iterator<std::forward_iterator_tag, 416b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) MachineInstr, ptrdiff_t>::reference reference; 417b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) typedef std::iterator<std::forward_iterator_tag, 418b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) MachineInstr, ptrdiff_t>::pointer pointer; 419b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 42090dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 421b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) defusechain_iterator() : Op(0) {} 422b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 423b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) bool operator==(const defusechain_iterator &x) const { 42490dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) return Op == x.Op; 42590dce4d38c5ff5333bea97d859d4e484e27edf0cTorne (Richard Coles) } 426b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) bool operator!=(const defusechain_iterator &x) const { 427b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) return !operator==(x); 428b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) } 429b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles) 4302a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// atEnd - return true if this iterator is equal to reg_end() on the value. 431c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) bool atEnd() const { return Op == 0; } 4322a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4332a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Iterator traversal: forward iteration only 4342a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) defusechain_iterator &operator++() { // Preincrement 4352a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) assert(Op && "Cannot increment end iterator!"); 4362a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Op = Op->getNextOperandForReg(); 4372a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4382a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // If this is an operand we don't care about, skip it. 4392a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) while (Op && ((!ReturnUses && Op->isUse()) || 4402a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) (!ReturnDefs && Op->isDef()) || 4412a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) (SkipDebug && Op->isDebug()))) 442c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) Op = Op->getNextOperandForReg(); 4432a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4442a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return *this; 4452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 4462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) defusechain_iterator operator++(int) { // Postincrement 447c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) defusechain_iterator tmp = *this; ++*this; return tmp; 4482a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 4492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4502a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// skipInstruction - move forward until reaching a different instruction. 4512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// Return the skipped instruction that is no longer pointed to, or NULL if 4522a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// already pointing to end(). 4532a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineInstr *skipInstruction() { 454c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (!Op) return 0; 4552a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineInstr *MI = Op->getParent(); 4562a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) do ++*this; 4572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) while (Op && Op->getParent() == MI); 458c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return MI; 4592a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 4602a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4612a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineOperand &getOperand() const { 462c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 4632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return *Op; 4642a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 4652a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 466c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /// getOperandNo - Return the operand # of this MachineOperand in its 4672a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// MachineInstr. 4682a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) unsigned getOperandNo() const { 4692a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 470c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return Op - &Op->getParent()->getOperand(0); 4712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 4722a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4732a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Retrieve a reference to the current operand. 474c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) MachineInstr &operator*() const { 4752a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 4762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return *Op->getParent(); 4772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 478c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 4792a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineInstr *operator->() const { 4802a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 4812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return Op->getParent(); 482c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 4832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) }; 4842a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 4852a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)}; 486c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 4872a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)} // End llvm namespace 4885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 4895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 490c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)