MachineRegisterInfo.h revision f0891be8bdbeeadb39da5575273b6645755fa383
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include <vector> 20 21namespace llvm { 22 23/// MachineRegisterInfo - Keep track of information for virtual and physical 24/// registers, including vreg register classes, use/def chains for registers, 25/// etc. 26class MachineRegisterInfo { 27 /// VRegInfo - Information we keep for each virtual register. The entries in 28 /// this vector are actually converted to vreg numbers by adding the 29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 30 /// 31 /// Each element in this list contains the register class of the vreg and the 32 /// start of the use/def list for the register. 33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 34 35 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 36 /// virtual registers. For each target register class, it keeps a list of 37 /// virtual registers belonging to the class. 38 std::vector<std::vector<unsigned> > RegClass2VRegMap; 39 40 /// RegAllocHints - This vector records register allocation hints for virtual 41 /// registers. For each virtual register, it keeps a register and hint type 42 /// pair making up the allocation hint. Hint type is target specific except 43 /// for the value 0 which means the second value of the pair is the preferred 44 /// register for allocation. For example, if the hint is <0, 1024>, it means 45 /// the allocator should prefer the physical register allocated to the virtual 46 /// register of the hint. 47 std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 48 49 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 50 /// physical registers. 51 MachineOperand **PhysRegUseDefLists; 52 53 /// UsedPhysRegs - This is a bit vector that is computed and set by the 54 /// register allocator, and must be kept up to date by passes that run after 55 /// register allocation (though most don't modify this). This is used 56 /// so that the code generator knows which callee save registers to save and 57 /// for other target specific uses. 58 BitVector UsedPhysRegs; 59 60 /// LiveIns/LiveOuts - Keep track of the physical registers that are 61 /// livein/liveout of the function. Live in values are typically arguments in 62 /// registers, live out values are typically return values in registers. 63 /// LiveIn values are allowed to have virtual registers associated with them, 64 /// stored in the second element. 65 std::vector<std::pair<unsigned, unsigned> > LiveIns; 66 std::vector<unsigned> LiveOuts; 67 68 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 70public: 71 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 72 ~MachineRegisterInfo(); 73 74 //===--------------------------------------------------------------------===// 75 // Register Info 76 //===--------------------------------------------------------------------===// 77 78 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 79 /// and uses of a register within the MachineFunction that corresponds to this 80 /// MachineRegisterInfo object. 81 template<bool Uses, bool Defs> 82 class defusechain_iterator; 83 84 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85 /// register. 86 typedef defusechain_iterator<true,true> reg_iterator; 87 reg_iterator reg_begin(unsigned RegNo) const { 88 return reg_iterator(getRegUseDefListHead(RegNo)); 89 } 90 static reg_iterator reg_end() { return reg_iterator(0); } 91 92 /// reg_empty - Return true if there are no instructions using or defining the 93 /// specified register (it may be live-in). 94 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 95 96 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 97 typedef defusechain_iterator<false,true> def_iterator; 98 def_iterator def_begin(unsigned RegNo) const { 99 return def_iterator(getRegUseDefListHead(RegNo)); 100 } 101 static def_iterator def_end() { return def_iterator(0); } 102 103 /// def_empty - Return true if there are no instructions defining the 104 /// specified register (it may be live-in). 105 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 106 107 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 108 typedef defusechain_iterator<true,false> use_iterator; 109 use_iterator use_begin(unsigned RegNo) const { 110 return use_iterator(getRegUseDefListHead(RegNo)); 111 } 112 static use_iterator use_end() { return use_iterator(0); } 113 114 /// use_empty - Return true if there are no instructions using the specified 115 /// register. 116 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 117 118 119 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 120 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 121 /// except that it also changes any definitions of the register as well. 122 void replaceRegWith(unsigned FromReg, unsigned ToReg); 123 124 /// getRegUseDefListHead - Return the head pointer for the register use/def 125 /// list for the specified virtual or physical register. 126 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 127 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 128 return PhysRegUseDefLists[RegNo]; 129 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 130 return VRegInfo[RegNo].second; 131 } 132 133 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 134 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 135 return PhysRegUseDefLists[RegNo]; 136 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 137 return VRegInfo[RegNo].second; 138 } 139 140 /// getVRegDef - Return the machine instr that defines the specified virtual 141 /// register or null if none is found. This assumes that the code is in SSA 142 /// form, so there should only be one definition. 143 MachineInstr *getVRegDef(unsigned Reg) const; 144 145#ifndef NDEBUG 146 void dumpUses(unsigned RegNo) const; 147#endif 148 149 //===--------------------------------------------------------------------===// 150 // Virtual Register Info 151 //===--------------------------------------------------------------------===// 152 153 /// getRegClass - Return the register class of the specified virtual register. 154 /// 155 const TargetRegisterClass *getRegClass(unsigned Reg) const { 156 Reg -= TargetRegisterInfo::FirstVirtualRegister; 157 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 158 return VRegInfo[Reg].first; 159 } 160 161 /// setRegClass - Set the register class of the specified virtual register. 162 /// 163 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 164 165 /// createVirtualRegister - Create and return a new virtual register in the 166 /// function with the specified register class. 167 /// 168 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 169 170 /// getLastVirtReg - Return the highest currently assigned virtual register. 171 /// 172 unsigned getLastVirtReg() const { 173 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 174 } 175 176 /// getRegClassVirtRegs - Return the list of virtual registers of the given 177 /// target register class. 178 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 179 return RegClass2VRegMap[RC->getID()]; 180 } 181 182 /// setRegAllocationHint - Specify a register allocation hint for the 183 /// specified virtual register. 184 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 185 Reg -= TargetRegisterInfo::FirstVirtualRegister; 186 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 187 RegAllocHints[Reg].first = Type; 188 RegAllocHints[Reg].second = PrefReg; 189 } 190 191 /// getRegAllocationHint - Return the register allocation hint for the 192 /// specified virtual register. 193 std::pair<unsigned, unsigned> 194 getRegAllocationHint(unsigned Reg) const { 195 Reg -= TargetRegisterInfo::FirstVirtualRegister; 196 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 197 return RegAllocHints[Reg]; 198 } 199 200 //===--------------------------------------------------------------------===// 201 // Physical Register Use Info 202 //===--------------------------------------------------------------------===// 203 204 /// isPhysRegUsed - Return true if the specified register is used in this 205 /// function. This only works after register allocation. 206 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 207 208 /// setPhysRegUsed - Mark the specified register used in this function. 209 /// This should only be called during and after register allocation. 210 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 211 212 /// setPhysRegUnused - Mark the specified register unused in this function. 213 /// This should only be called during and after register allocation. 214 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 215 216 217 //===--------------------------------------------------------------------===// 218 // LiveIn/LiveOut Management 219 //===--------------------------------------------------------------------===// 220 221 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 222 /// is an error to add the same register to the same set more than once. 223 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 224 LiveIns.push_back(std::make_pair(Reg, vreg)); 225 } 226 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 227 228 // Iteration support for live in/out sets. These sets are kept in sorted 229 // order by their register number. 230 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 231 livein_iterator; 232 typedef std::vector<unsigned>::const_iterator liveout_iterator; 233 livein_iterator livein_begin() const { return LiveIns.begin(); } 234 livein_iterator livein_end() const { return LiveIns.end(); } 235 bool livein_empty() const { return LiveIns.empty(); } 236 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 237 liveout_iterator liveout_end() const { return LiveOuts.end(); } 238 bool liveout_empty() const { return LiveOuts.empty(); } 239 240 bool isLiveIn(unsigned Reg) const { 241 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 242 if (I->first == Reg || I->second == Reg) 243 return true; 244 return false; 245 } 246 247private: 248 void HandleVRegListReallocation(); 249 250public: 251 /// defusechain_iterator - This class provides iterator support for machine 252 /// operands in the function that use or define a specific register. If 253 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 254 /// returns defs. If neither are true then you are silly and it always 255 /// returns end(). 256 template<bool ReturnUses, bool ReturnDefs> 257 class defusechain_iterator 258 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 259 MachineOperand *Op; 260 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 261 // If the first node isn't one we're interested in, advance to one that 262 // we are interested in. 263 if (op) { 264 if ((!ReturnUses && op->isUse()) || 265 (!ReturnDefs && op->isDef())) 266 ++*this; 267 } 268 } 269 friend class MachineRegisterInfo; 270 public: 271 typedef std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t>::reference reference; 272 typedef std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t>::pointer pointer; 273 274 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 275 defusechain_iterator() : Op(0) {} 276 277 bool operator==(const defusechain_iterator &x) const { 278 return Op == x.Op; 279 } 280 bool operator!=(const defusechain_iterator &x) const { 281 return !operator==(x); 282 } 283 284 /// atEnd - return true if this iterator is equal to reg_end() on the value. 285 bool atEnd() const { return Op == 0; } 286 287 // Iterator traversal: forward iteration only 288 defusechain_iterator &operator++() { // Preincrement 289 assert(Op && "Cannot increment end iterator!"); 290 Op = Op->getNextOperandForReg(); 291 292 // If this is an operand we don't care about, skip it. 293 while (Op && ((!ReturnUses && Op->isUse()) || 294 (!ReturnDefs && Op->isDef()))) 295 Op = Op->getNextOperandForReg(); 296 297 return *this; 298 } 299 defusechain_iterator operator++(int) { // Postincrement 300 defusechain_iterator tmp = *this; ++*this; return tmp; 301 } 302 303 MachineOperand &getOperand() const { 304 assert(Op && "Cannot dereference end iterator!"); 305 return *Op; 306 } 307 308 /// getOperandNo - Return the operand # of this MachineOperand in its 309 /// MachineInstr. 310 unsigned getOperandNo() const { 311 assert(Op && "Cannot dereference end iterator!"); 312 return Op - &Op->getParent()->getOperand(0); 313 } 314 315 // Retrieve a reference to the current operand. 316 MachineInstr &operator*() const { 317 assert(Op && "Cannot dereference end iterator!"); 318 return *Op->getParent(); 319 } 320 321 MachineInstr *operator->() const { 322 assert(Op && "Cannot dereference end iterator!"); 323 return Op->getParent(); 324 } 325 }; 326 327}; 328 329} // End llvm namespace 330 331#endif 332