199ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick//===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===// 299ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// 399ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// The LLVM Compiler Infrastructure 499ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// 599ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// This file is distributed under the University of Illinois Open Source 699ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// License. See LICENSE.TXT for details. 799ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// 899ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick//===----------------------------------------------------------------------===// 999ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// 1099ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// This file defines a wrapper around MCSchedModel that allows the interface to 1199ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// benefit from information currently only available in TargetInstrInfo. 121ef65d61d11a9ac038de13e8accdebb7e731d876Andrew Trick// Ideally, the scheduling interface would be fully defined in the MC layer. 1399ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick// 1499ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick//===----------------------------------------------------------------------===// 1599ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 16674be02d525d4e24bc6943ed9274958c580bcfbcJakub Staszak#ifndef LLVM_CODEGEN_TARGETSCHEDULE_H 17674be02d525d4e24bc6943ed9274958c580bcfbcJakub Staszak#define LLVM_CODEGEN_TARGETSCHEDULE_H 1899ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 198d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick#include "llvm/ADT/SmallVector.h" 20255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/MC/MCInstrItineraries.h" 21255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/MC/MCSchedule.h" 22255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/Target/TargetSubtargetInfo.h" 2399ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 2499ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Tricknamespace llvm { 2599ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 2699ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trickclass TargetRegisterInfo; 2799ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trickclass TargetSubtargetInfo; 2899ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trickclass TargetInstrInfo; 2999ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trickclass MachineInstr; 3099ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 3199ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick/// Provide an instruction scheduling machine model to CodeGen passes. 3299ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trickclass TargetSchedModel { 3399ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick // For efficiency, hold a copy of the statically defined MCSchedModel for this 3499ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick // processor. 3599ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick MCSchedModel SchedModel; 3699ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick InstrItineraryData InstrItins; 3799ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick const TargetSubtargetInfo *STI; 3899ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick const TargetInstrInfo *TII; 398d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 408d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick SmallVector<unsigned, 16> ResourceFactors; 418d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned MicroOpFactor; // Multiply to normalize microops to resource units. 428d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned ResourceLCM; // Resource units per cycle. Latency normalization factor. 4399ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trickpublic: 44dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines TargetSchedModel(): STI(nullptr), TII(nullptr) {} 4599ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 46c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// \brief Initialize the machine model for instruction scheduling. 47c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// 48c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// The machine model API keeps a copy of the top-level MCSchedModel table 49c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve 50c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// dynamic properties. 5199ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti, 5299ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick const TargetInstrInfo *tii); 5399ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 548d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// Return the MCSchedClassDesc for this instruction. 558d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const; 568d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 57c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// \brief TargetInstrInfo getter. 5899ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick const TargetInstrInfo *getInstrInfo() const { return TII; } 5999ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 60c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// \brief Return true if this machine model includes an instruction-level 61c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// scheduling model. 62c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// 63c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// This is more detailed than the course grain IssueWidth and default 6499ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick /// latency properties, but separate from the per-cycle itinerary data. 6542bb106118db51393c2524c8b0c7f7ba6674cfd7Andrew Trick bool hasInstrSchedModel() const; 6699ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 67412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick const MCSchedModel *getMCSchedModel() const { return &SchedModel; } 68412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick 69c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// \brief Return true if this machine model includes cycle-to-cycle itinerary 70c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// data. 71c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// 72c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// This models scheduling at each stage in the processor pipeline. 7342bb106118db51393c2524c8b0c7f7ba6674cfd7Andrew Trick bool hasInstrItineraries() const; 7434301ceca8913f3126339f332d3dc6f2d7ac0d78Andrew Trick 75412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick const InstrItineraryData *getInstrItineraries() const { 76412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick if (hasInstrItineraries()) 77412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick return &InstrItins; 78dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 79412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick } 80412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick 81412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick /// \brief Identify the processor corresponding to the current subtarget. 82412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick unsigned getProcessorID() const { return SchedModel.getProcessorID(); } 83412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick 84412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick /// \brief Maximum number of micro-ops that may be scheduled per cycle. 85412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick unsigned getIssueWidth() const { return SchedModel.IssueWidth; } 86412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick 87412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick /// \brief Return the number of issue slots required for this MI. 888d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned getNumMicroOps(const MachineInstr *MI, 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCSchedClassDesc *SC = nullptr) const; 908d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 918d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// \brief Get the number of kinds of resources for this target. 928d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned getNumProcResourceKinds() const { 938d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return SchedModel.getNumProcResourceKinds(); 948d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 958d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 968d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// \brief Get a processor resource by ID for convenience. 978d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick const MCProcResourceDesc *getProcResource(unsigned PIdx) const { 988d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return SchedModel.getProcResource(PIdx); 998d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 1008d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 10136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#ifndef NDEBUG 10236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const char *getResourceName(unsigned PIdx) const { 10336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (!PIdx) 10436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return "MOps"; 10536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return SchedModel.getProcResource(PIdx)->Name; 10636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 10736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#endif 10836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 1098d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick typedef const MCWriteProcResEntry *ProcResIter; 1108d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 1118d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick // \brief Get an iterator into the processor resources consumed by this 1128d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick // scheduling class. 1138d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { 1148d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick // The subtarget holds a single resource table for all processors. 1158d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return STI->getWriteProcResBegin(SC); 1168d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 1178d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { 1188d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return STI->getWriteProcResEnd(SC); 1198d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 1208d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 1218d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// \brief Multiply the number of units consumed for a resource by this factor 1228d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// to normalize it relative to other resources. 1238d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned getResourceFactor(unsigned ResIdx) const { 1248d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return ResourceFactors[ResIdx]; 1258d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 1268d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 1278d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// \brief Multiply number of micro-ops by this factor to normalize it 1288d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// relative to other resources. 1298d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned getMicroOpFactor() const { 1308d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return MicroOpFactor; 1318d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 1328d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick 1338d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// \brief Multiply cycle count by this factor to normalize it relative to 1348d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick /// other resources. This is the number of resource units per cycle. 1358d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick unsigned getLatencyFactor() const { 1368d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick return ResourceLCM; 1378d4abb2446f80986ad5136bbec30c5da18cd6f4bAndrew Trick } 138412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick 139b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick /// \brief Number of micro-ops that may be buffered for OOO execution. 140b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } 141b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick 142b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick /// \brief Number of resource units that may be buffered for OOO execution. 143b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick /// \return The buffer size in resource units or -1 for unlimited. 144b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick int getResourceBufferSize(unsigned PIdx) const { 145b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick return SchedModel.getProcResource(PIdx)->BufferSize; 146b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick } 147b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick 148c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// \brief Compute operand latency based on the available machine model. 149c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// 150b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick /// Compute and return the latency of the given data dependent def and use 151c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// when the operand indices are already known. UseMI may be NULL for an 152c92d72abd03b0c29099b3f87f4cb67a299610f03Andrew Trick /// unknown user. 15334301ceca8913f3126339f332d3dc6f2d7ac0d78Andrew Trick unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, 154b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick const MachineInstr *UseMI, unsigned UseOperIdx) 155b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick const; 15699ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 157c0dfffa448ad7ab647779bc3e7f2aee5c76cb31bAndrew Trick /// \brief Compute the instruction latency based on the available machine 158c0dfffa448ad7ab647779bc3e7f2aee5c76cb31bAndrew Trick /// model. 159c0dfffa448ad7ab647779bc3e7f2aee5c76cb31bAndrew Trick /// 160c0dfffa448ad7ab647779bc3e7f2aee5c76cb31bAndrew Trick /// Compute and return the expected latency of this instruction independent of 16136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines /// a particular use. computeOperandLatency is the preferred API, but this is 162c0dfffa448ad7ab647779bc3e7f2aee5c76cb31bAndrew Trick /// occasionally useful to help estimate instruction cost. 163d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer /// 164d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer /// If UseDefaultDefLatency is false and no new machine sched model is 165d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer /// present this method falls back to TII->getInstrLatency with an empty 166d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer /// instruction itinerary (this is so we preserve the previous behavior of the 167d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer /// if converter after moving it to TargetSchedModel). 168d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer unsigned computeInstrLatency(const MachineInstr *MI, 169d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer bool UseDefaultDefLatency = true) const; 170c0dfffa448ad7ab647779bc3e7f2aee5c76cb31bAndrew Trick 171412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick /// \brief Output dependency latency of a pair of defs of the same register. 172412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick /// 173412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick /// This is typically one cycle. 174412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx, 175412cd2f81374865dfa708bef6d5b896ca10dece0Andrew Trick const MachineInstr *DepMI) const; 17699ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick}; 17799ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 17899ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick} // namespace llvm 17999ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick 18099ab6c6035aec3c0e9b0cc5b76a4666fc5fd7b7bAndrew Trick#endif 181