1dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines//===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===// 287773c318fcee853fb34a80a10c4347d523bdafbTim Northover// 387773c318fcee853fb34a80a10c4347d523bdafbTim Northover// The LLVM Compiler Infrastructure 487773c318fcee853fb34a80a10c4347d523bdafbTim Northover// 587773c318fcee853fb34a80a10c4347d523bdafbTim Northover// This file is distributed under the University of Illinois Open Source 687773c318fcee853fb34a80a10c4347d523bdafbTim Northover// License. See LICENSE.TXT for details. 787773c318fcee853fb34a80a10c4347d523bdafbTim Northover// 887773c318fcee853fb34a80a10c4347d523bdafbTim Northover//===----------------------------------------------------------------------===// 987773c318fcee853fb34a80a10c4347d523bdafbTim Northover// 10dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// This file defines all of the AARCH64-specific intrinsics. 1187773c318fcee853fb34a80a10c4347d523bdafbTim Northover// 1287773c318fcee853fb34a80a10c4347d523bdafbTim Northover//===----------------------------------------------------------------------===// 1387773c318fcee853fb34a80a10c4347d523bdafbTim Northover 14dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet TargetPrefix = "aarch64" in { 15dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 16dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; 17dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; 18dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; 19dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; 20dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 21dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; 22dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; 23dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_stxp : Intrinsic<[llvm_i32_ty], 24dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>; 25dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_stlxp : Intrinsic<[llvm_i32_ty], 26dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>; 27dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 28dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_clrex : Intrinsic<[]>; 29dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 30dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, 31dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>], [IntrNoMem]>; 32dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, 33dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>], [IntrNoMem]>; 34cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 35cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines//===----------------------------------------------------------------------===// 36cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines// RBIT 37cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 38cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesdef int_aarch64_rbit : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], 39cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines [IntrNoMem]>; 40cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 42dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 4387773c318fcee853fb34a80a10c4347d523bdafbTim Northover//===----------------------------------------------------------------------===// 4487773c318fcee853fb34a80a10c4347d523bdafbTim Northover// Advanced SIMD (NEON) 4587773c318fcee853fb34a80a10c4347d523bdafbTim Northover 4687773c318fcee853fb34a80a10c4347d523bdafbTim Northoverlet TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 47dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Scalar_Float_Intrinsic 48dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 49dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 50dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 51dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_FPToIntRounding_Intrinsic 52dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; 53dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 54dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1IntArg_Intrinsic 55dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; 56dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1FloatArg_Intrinsic 57dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; 58dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1VectorArg_Intrinsic 59dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; 60dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1VectorArg_Expand_Intrinsic 61dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 62dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1VectorArg_Long_Intrinsic 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>; 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1IntArg_Narrow_Intrinsic 65dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>; 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1VectorArg_Narrow_Intrinsic 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>; 68dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1VectorArg_Int_Across_Intrinsic 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>; 70dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1VectorArg_Float_Across_Intrinsic 71dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>; 72dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 73dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2IntArg_Intrinsic 74dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 75dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 76dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2FloatArg_Intrinsic 77dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 78dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 79dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Intrinsic 80dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 81dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 82dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Compare_Intrinsic 83dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], 84dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 85dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Arg_FloatCompare_Intrinsic 86dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>], 87dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 88dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Long_Intrinsic 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 90dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMTruncatedType<0>, LLVMTruncatedType<0>], 91dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Wide_Intrinsic 93dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 94dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, LLVMTruncatedType<0>], 95dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 96dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Narrow_Intrinsic 97dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 98dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMExtendedType<0>, LLVMExtendedType<0>], 99dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 100dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic 101dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], 102dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMExtendedType<0>, llvm_i32_ty], 103dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 104dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic 105dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 106dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_anyvector_ty], 107dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 108dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic 109dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 110dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMTruncatedType<0>], 111dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 112dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic 113dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 114dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMTruncatedType<0>, llvm_i32_ty], 115dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 116dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic 117dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 118dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty], 119dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 120dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 121dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3VectorArg_Intrinsic 122dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 123dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 124dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 125dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3VectorArg_Scalar_Intrinsic 126dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 127dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], 128dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 129dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic 130dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 131dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, 132dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<1>], [IntrNoMem]>; 133dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic 134dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 135dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty], 136dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 137dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_CvtFxToFP_Intrinsic 138dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], 139dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 140dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_CvtFPToFx_Intrinsic 141dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], 142dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 143dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 14487773c318fcee853fb34a80a10c4347d523bdafbTim Northover 145dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// Arithmetic ops 14636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 147dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet Properties = [IntrNoMem] in { 148dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Add Across Lanes 149dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_saddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 150dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uaddv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 151dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_faddv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 152dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 153dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Long Add Across Lanes 154dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_saddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 155dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uaddlv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 156dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 157dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Halving Add 158dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_shadd : AdvSIMD_2VectorArg_Intrinsic; 159dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uhadd : AdvSIMD_2VectorArg_Intrinsic; 160dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 161dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Rounding Halving Add 162dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_srhadd : AdvSIMD_2VectorArg_Intrinsic; 163dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_urhadd : AdvSIMD_2VectorArg_Intrinsic; 164dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 165dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Add 166dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqadd : AdvSIMD_2IntArg_Intrinsic; 167dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_suqadd : AdvSIMD_2IntArg_Intrinsic; 168dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_usqadd : AdvSIMD_2IntArg_Intrinsic; 169dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqadd : AdvSIMD_2IntArg_Intrinsic; 170dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 171dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Add High-Half 172dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that 173dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // header is no longer supported. 174dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_addhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 175dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 176dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Rounding Add High-Half 177dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_raddhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 178dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 179dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Doubling Multiply High 180dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqdmulh : AdvSIMD_2IntArg_Intrinsic; 181dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 182dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Rounding Doubling Multiply High 183dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqrdmulh : AdvSIMD_2IntArg_Intrinsic; 184dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 185dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Polynominal Multiply 186dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_pmul : AdvSIMD_2VectorArg_Intrinsic; 187dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 188dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Long Multiply 189dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_smull : AdvSIMD_2VectorArg_Long_Intrinsic; 190dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_umull : AdvSIMD_2VectorArg_Long_Intrinsic; 191dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_pmull : AdvSIMD_2VectorArg_Long_Intrinsic; 192dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 193dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // 64-bit polynomial multiply really returns an i128, which is not legal. Fake 194dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // it with a v16i8. 195dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_pmull64 : 196dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; 197dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 198dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Extending Multiply 199dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic { 200dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines let Properties = [IntrNoMem, Commutative]; 201dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 202dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 203dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Doubling Long Multiply 204dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic; 205dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqdmulls_scalar 206dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 207dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 208dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Halving Subtract 209dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic; 210dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uhsub : AdvSIMD_2VectorArg_Intrinsic; 211dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 212dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Subtract 213dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqsub : AdvSIMD_2IntArg_Intrinsic; 214dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqsub : AdvSIMD_2IntArg_Intrinsic; 215dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 216dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Subtract High-Half 217dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // FIXME: this is a legacy intrinsic for aarch64_simd.h. Remove it when that 218dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // header is no longer supported. 219dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_subhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 220dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 221dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Rounding Subtract High-Half 222dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_rsubhn : AdvSIMD_2VectorArg_Narrow_Intrinsic; 223dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 224dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Compare Absolute Greater-than-or-equal 225dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_facge : AdvSIMD_2Arg_FloatCompare_Intrinsic; 226dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 227dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Compare Absolute Greater-than 228dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_facgt : AdvSIMD_2Arg_FloatCompare_Intrinsic; 229dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 230dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Absolute Difference 231dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sabd : AdvSIMD_2VectorArg_Intrinsic; 232dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uabd : AdvSIMD_2VectorArg_Intrinsic; 233dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fabd : AdvSIMD_2VectorArg_Intrinsic; 234dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 235dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Scalar Absolute Difference 236dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_sisd_fabd : AdvSIMD_2Scalar_Float_Intrinsic; 237dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 238dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Max 239dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_smax : AdvSIMD_2VectorArg_Intrinsic; 240dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_umax : AdvSIMD_2VectorArg_Intrinsic; 241dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmax : AdvSIMD_2VectorArg_Intrinsic; 242dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmaxnmp : AdvSIMD_2VectorArg_Intrinsic; 243dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 244dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Max Across Lanes 245dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_smaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 246dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_umaxv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 247dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmaxv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 248dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmaxnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 249dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 250dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Min 251dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_smin : AdvSIMD_2VectorArg_Intrinsic; 252dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_umin : AdvSIMD_2VectorArg_Intrinsic; 253dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmin : AdvSIMD_2VectorArg_Intrinsic; 254dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fminnmp : AdvSIMD_2VectorArg_Intrinsic; 255dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 256dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Min/Max Number 257dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fminnm : AdvSIMD_2FloatArg_Intrinsic; 258dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmaxnm : AdvSIMD_2FloatArg_Intrinsic; 259dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 260dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Min Across Lanes 261dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 262dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uminv : AdvSIMD_1VectorArg_Int_Across_Intrinsic; 263dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fminv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 264dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fminnmv : AdvSIMD_1VectorArg_Float_Across_Intrinsic; 265dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 266dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Pairwise Add 267dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_addp : AdvSIMD_2VectorArg_Intrinsic; 268dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 269dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Long Pairwise Add 270dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // FIXME: In theory, we shouldn't need intrinsics for saddlp or 271dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // uaddlp, but tblgen's type inference currently can't handle the 272dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // pattern fragments this ends up generating. 273dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_saddlp : AdvSIMD_1VectorArg_Expand_Intrinsic; 274dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uaddlp : AdvSIMD_1VectorArg_Expand_Intrinsic; 2751d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 276dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Folding Maximum 277dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_smaxp : AdvSIMD_2VectorArg_Intrinsic; 278dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_umaxp : AdvSIMD_2VectorArg_Intrinsic; 279dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fmaxp : AdvSIMD_2VectorArg_Intrinsic; 280dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 281dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Folding Minimum 282dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sminp : AdvSIMD_2VectorArg_Intrinsic; 283dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uminp : AdvSIMD_2VectorArg_Intrinsic; 284dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fminp : AdvSIMD_2VectorArg_Intrinsic; 285dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 286dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Reciprocal Estimate/Step 287dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_frecps : AdvSIMD_2FloatArg_Intrinsic; 288dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_frsqrts : AdvSIMD_2FloatArg_Intrinsic; 289dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 290dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Reciprocal Exponent 291dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_frecpx : AdvSIMD_1FloatArg_Intrinsic; 292dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 293dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Shift Left 294dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqshl : AdvSIMD_2IntArg_Intrinsic; 295dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqshl : AdvSIMD_2IntArg_Intrinsic; 296dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 297dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Rounding Shift Left 298dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_srshl : AdvSIMD_2IntArg_Intrinsic; 299dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_urshl : AdvSIMD_2IntArg_Intrinsic; 300dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 301dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Rounding Shift Left 302dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqrshl : AdvSIMD_2IntArg_Intrinsic; 303dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqrshl : AdvSIMD_2IntArg_Intrinsic; 304dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 305dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Signed->Unsigned Shift Left by Constant 306dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqshlu : AdvSIMD_2IntArg_Intrinsic; 307dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 308dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant 309dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 310dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 311dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const 312dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqrshrun : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 313dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 314dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Narrowing Shift Right by Constant 315dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 316dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 317dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 318dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Rounding Narrowing Shift Right by Constant 319dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_rshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 320dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 321dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Rounding Narrowing Saturating Shift Right by Constant 322dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 323dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqrshrn : AdvSIMD_2Arg_Scalar_Narrow_Intrinsic; 324dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 325dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Shift Left 326dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sshl : AdvSIMD_2IntArg_Intrinsic; 327dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_ushl : AdvSIMD_2IntArg_Intrinsic; 328dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 329dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Widening Shift Left by Constant 330dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_shll : AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic; 331dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sshll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic; 332dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_ushll : AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic; 333dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 334dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Shift Right by Constant and Insert 335dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vsri : AdvSIMD_3VectorArg_Scalar_Intrinsic; 336dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 337dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Shift Left by Constant and Insert 338dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vsli : AdvSIMD_3VectorArg_Scalar_Intrinsic; 339dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 340dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Narrow 341dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_scalar_sqxtn: AdvSIMD_1IntArg_Narrow_Intrinsic; 342dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_scalar_uqxtn : AdvSIMD_1IntArg_Narrow_Intrinsic; 343dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic; 344dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_uqxtn : AdvSIMD_1VectorArg_Narrow_Intrinsic; 345dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 346dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Extract and Unsigned Narrow 347dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_scalar_sqxtun : AdvSIMD_1IntArg_Narrow_Intrinsic; 348dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqxtun : AdvSIMD_1VectorArg_Narrow_Intrinsic; 349dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 350dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Absolute Value 351dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_abs : AdvSIMD_1IntArg_Intrinsic; 352dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 353dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Absolute Value 354dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqabs : AdvSIMD_1IntArg_Intrinsic; 355dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 356dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Saturating Negation 357dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_sqneg : AdvSIMD_1IntArg_Intrinsic; 358dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 359dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Count Leading Sign Bits 360dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_cls : AdvSIMD_1VectorArg_Intrinsic; 361dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 362dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Reciprocal Estimate 363dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_urecpe : AdvSIMD_1VectorArg_Intrinsic; 364dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_frecpe : AdvSIMD_1FloatArg_Intrinsic; 365dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 366dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Square Root Estimate 367dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_ursqrte : AdvSIMD_1VectorArg_Intrinsic; 368dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_frsqrte : AdvSIMD_1FloatArg_Intrinsic; 369dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 370dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Bitwise Reverse 371dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_rbit : AdvSIMD_1VectorArg_Intrinsic; 372dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 373dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Conversions Between Half-Precision and Single-Precision. 374dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vcvtfp2hf 375dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; 376dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vcvthf2fp 377dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; 3781d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 379dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector Conversions Between Floating-point and Fixed-point. 380dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic; 381dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vcvtfp2fxu : AdvSIMD_CvtFPToFx_Intrinsic; 382dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vcvtfxs2fp : AdvSIMD_CvtFxToFP_Intrinsic; 383dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_vcvtfxu2fp : AdvSIMD_CvtFxToFP_Intrinsic; 3841d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 385dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector FP->Int Conversions 386dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtas : AdvSIMD_FPToIntRounding_Intrinsic; 387dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtau : AdvSIMD_FPToIntRounding_Intrinsic; 388dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtms : AdvSIMD_FPToIntRounding_Intrinsic; 389dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtmu : AdvSIMD_FPToIntRounding_Intrinsic; 390dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtns : AdvSIMD_FPToIntRounding_Intrinsic; 391dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtnu : AdvSIMD_FPToIntRounding_Intrinsic; 392dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtps : AdvSIMD_FPToIntRounding_Intrinsic; 393dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtpu : AdvSIMD_FPToIntRounding_Intrinsic; 394dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtzs : AdvSIMD_FPToIntRounding_Intrinsic; 395dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtzu : AdvSIMD_FPToIntRounding_Intrinsic; 3961d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 397dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector FP Rounding: only ties to even is unrepresented by a normal 398dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // intrinsic. 399dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_frintn : AdvSIMD_1FloatArg_Intrinsic; 4001d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 401dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Scalar FP->Int conversions 4021d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 403dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Vector FP Inexact Narrowing 404dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic; 405dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 406dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Scalar FP Inexact Narrowing 407dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty], 408dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 409dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 410dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 411dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 412dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Vector2Index_Intrinsic 413dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 414dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty], 415dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 416dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 4171d28917dc39f38847f5c69c0a60cd1491430bdadChad Rosier 418dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// Vector element to element moves 419dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_vcopy_lane: AdvSIMD_2Vector2Index_Intrinsic; 420dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 421dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 422dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1Vec_Load_Intrinsic 423dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType<LLVMMatchType<0>>], 424dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 425dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_1Vec_Store_Lane_Intrinsic 426dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], 427dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<2>]>; 428dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 429dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Vec_Load_Intrinsic 430dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 431dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMAnyPointerType<LLVMMatchType<0>>], 432dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 433dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Vec_Load_Lane_Intrinsic 434dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 435dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, LLVMMatchType<0>, 436dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_i64_ty, llvm_anyptr_ty], 437dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 438dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Vec_Store_Intrinsic 439dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 440dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMAnyPointerType<LLVMMatchType<0>>], 441dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<2>]>; 442dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_2Vec_Store_Lane_Intrinsic 443dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 444dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_i64_ty, llvm_anyptr_ty], 445dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<3>]>; 446dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 447dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3Vec_Load_Intrinsic 448dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>], 449dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMAnyPointerType<LLVMMatchType<0>>], 450dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 451dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3Vec_Load_Lane_Intrinsic 452dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>], 453dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, 454dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_i64_ty, llvm_anyptr_ty], 455dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 456dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3Vec_Store_Intrinsic 457dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 458dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMAnyPointerType<LLVMMatchType<0>>], 459dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<3>]>; 460dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_3Vec_Store_Lane_Intrinsic 461dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, 462dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMMatchType<0>, 463dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_i64_ty, llvm_anyptr_ty], 464dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<4>]>; 465dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 466dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_4Vec_Load_Intrinsic 467dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 468dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMMatchType<0>], 469dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMAnyPointerType<LLVMMatchType<0>>], 470dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 471dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_4Vec_Load_Lane_Intrinsic 472dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 473dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMMatchType<0>], 474dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, LLVMMatchType<0>, 475dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMMatchType<0>, 476dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_i64_ty, llvm_anyptr_ty], 477dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadArgMem]>; 478dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_4Vec_Store_Intrinsic 479dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 480dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMMatchType<0>, 481dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMAnyPointerType<LLVMMatchType<0>>], 482dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<4>]>; 483dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_4Vec_Store_Lane_Intrinsic 484dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, 485dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>, LLVMMatchType<0>, 486dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_i64_ty, llvm_anyptr_ty], 487dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrReadWriteArgMem, NoCapture<5>]>; 488dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 4890710afb9af81cff9846ceda7b56d03cf177dd6efKevin Qin 490dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// Memory ops 4911a035dd6df1d953af57656491eda28ceef9ad4a3Chad Rosier 492dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld1x2 : AdvSIMD_2Vec_Load_Intrinsic; 493dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld1x3 : AdvSIMD_3Vec_Load_Intrinsic; 494dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld1x4 : AdvSIMD_4Vec_Load_Intrinsic; 4953ff3a8aa7511bede13e836303a083af37fec4f4eJiangning Liu 496dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st1x2 : AdvSIMD_2Vec_Store_Intrinsic; 497dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st1x3 : AdvSIMD_3Vec_Store_Intrinsic; 498dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st1x4 : AdvSIMD_4Vec_Store_Intrinsic; 49930b2a19f3be840da1bc4aefcaabcbddd2e0130fcChad Rosier 500dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld2 : AdvSIMD_2Vec_Load_Intrinsic; 501dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld3 : AdvSIMD_3Vec_Load_Intrinsic; 502dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld4 : AdvSIMD_4Vec_Load_Intrinsic; 5033ff3a8aa7511bede13e836303a083af37fec4f4eJiangning Liu 504dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld2lane : AdvSIMD_2Vec_Load_Lane_Intrinsic; 505dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld3lane : AdvSIMD_3Vec_Load_Lane_Intrinsic; 506dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld4lane : AdvSIMD_4Vec_Load_Lane_Intrinsic; 507dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 508dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld2r : AdvSIMD_2Vec_Load_Intrinsic; 509dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld3r : AdvSIMD_3Vec_Load_Intrinsic; 510dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_ld4r : AdvSIMD_4Vec_Load_Intrinsic; 511dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 512dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st2 : AdvSIMD_2Vec_Store_Intrinsic; 513dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st3 : AdvSIMD_3Vec_Store_Intrinsic; 514dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st4 : AdvSIMD_4Vec_Store_Intrinsic; 515dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 516dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st2lane : AdvSIMD_2Vec_Store_Lane_Intrinsic; 517dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st3lane : AdvSIMD_3Vec_Store_Lane_Intrinsic; 518dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_st4lane : AdvSIMD_4Vec_Store_Lane_Intrinsic; 519dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 520dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". 521dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbl1_Intrinsic 522dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>], 523dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 524dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbl2_Intrinsic 525dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 526dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; 527dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbl3_Intrinsic 528dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 529dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, 530dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>], 531dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 532dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbl4_Intrinsic 533dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 534dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, 535dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>], 536dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 537dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 538dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbx1_Intrinsic 539dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 540dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>], 541dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 542dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbx2_Intrinsic 543dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 544dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, 545dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LLVMMatchType<0>], 546dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 547dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbx3_Intrinsic 548dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 549dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, 550dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_v16i8_ty, LLVMMatchType<0>], 551dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 552dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class AdvSIMD_Tbx4_Intrinsic 553dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_anyvector_ty], 554dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, 555dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], 556dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 557dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 558dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbl1 : AdvSIMD_Tbl1_Intrinsic; 559dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbl2 : AdvSIMD_Tbl2_Intrinsic; 560dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbl3 : AdvSIMD_Tbl3_Intrinsic; 561dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbl4 : AdvSIMD_Tbl4_Intrinsic; 562dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 563dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbx1 : AdvSIMD_Tbx1_Intrinsic; 564dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbx2 : AdvSIMD_Tbx2_Intrinsic; 565dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic; 566dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic; 567dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 568dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet TargetPrefix = "aarch64" in { 569dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_AES_DataKey_Intrinsic 570dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; 571dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 572dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_AES_Data_Intrinsic 573dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; 574dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 575dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule 576dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // (v4i32). 577dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_SHA_5Hash4Schedule_Intrinsic 578dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], 579dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 580dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 581dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule 582dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // (v4i32). 583dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_SHA_1Hash_Intrinsic 584dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; 585dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 586dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // SHA intrinsic taking 8 words of the schedule 587dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_SHA_8Schedule_Intrinsic 588dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; 589dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 590dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // SHA intrinsic taking 12 words of the schedule 591dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_SHA_12Schedule_Intrinsic 592dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 593dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 594dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 595dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // SHA intrinsic taking 8 words of the hash and 4 of the schedule. 596dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines class Crypto_SHA_8Hash4Schedule_Intrinsic 597dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], 598dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 599dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 600dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 601dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// AES 602dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_aese : Crypto_AES_DataKey_Intrinsic; 603dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_aesd : Crypto_AES_DataKey_Intrinsic; 604dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_aesmc : Crypto_AES_Data_Intrinsic; 605dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_aesimc : Crypto_AES_Data_Intrinsic; 606dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 607dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// SHA1 608dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha1c : Crypto_SHA_5Hash4Schedule_Intrinsic; 609dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha1p : Crypto_SHA_5Hash4Schedule_Intrinsic; 610dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha1m : Crypto_SHA_5Hash4Schedule_Intrinsic; 611dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha1h : Crypto_SHA_1Hash_Intrinsic; 612dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 613dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha1su0 : Crypto_SHA_12Schedule_Intrinsic; 614dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha1su1 : Crypto_SHA_8Schedule_Intrinsic; 615dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 616dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// SHA256 617dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha256h : Crypto_SHA_8Hash4Schedule_Intrinsic; 618dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha256h2 : Crypto_SHA_8Hash4Schedule_Intrinsic; 619dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha256su0 : Crypto_SHA_8Schedule_Intrinsic; 620dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crypto_sha256su1 : Crypto_SHA_12Schedule_Intrinsic; 621dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 622dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines//===----------------------------------------------------------------------===// 623dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// CRC32 624dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 625dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineslet TargetPrefix = "aarch64" in { 626dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 627dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 628dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 629dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 630dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 631dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 632dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 633dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 634dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 635dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 636dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 637dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 638dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 639dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32x : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], 640dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 641dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesdef int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], 642dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines [IntrNoMem]>; 64387773c318fcee853fb34a80a10c4347d523bdafbTim Northover} 644