MCInstrDesc.h revision 16884415db751c75f2133bd04921393c792b1158
15821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 55821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file defines the MCOperandInfo and MCInstrDesc classes, which 112a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)// are used to describe target instructions and their operands. 12868fa2fe829687343ffae624259930155e16dbd8Torne (Richard Coles)// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 147dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch 15c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#ifndef LLVM_MC_MCINSTRDESC_H 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define LLVM_MC_MCINSTRDESC_H 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Support/DataTypes.h" 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace llvm { 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Machine Operand Flags and Description 245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace MCOI { 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Operand constraints 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) enum OperandConstraint { 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) TIED_TO = 0, // Must be allocated the same register as. 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) EARLY_CLOBBER // Operand is an early clobber register operand 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// OperandFlags - These are flags set on operands, but should be considered 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// private, all access should go through the MCOperandInfo accessors. 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// See the accessors for a description of what these are. 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) enum OperandFlags { 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) LookupPtrRegClass = 0, 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Predicate, 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) OptionalDef 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// MCOperandInfo - This holds information about one operand of a machine 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// instruction, indicating the register class for register operands, etc. 455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MCOperandInfo { 475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// RegClass - This specifies the register class enumeration of the operand 495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// if the operand is a register. If isLookupPtrRegClass is set, then this is 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// get a dynamic register class. 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) short RegClass; 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Flags - These are flags from the MCOI::OperandFlags enum. 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned short Flags; 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Lower 16 bits are used to specify which constraints are set. The higher 16 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// bits are used to specify the value of constraints (4 bits each). 595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned Constraints; 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Currently no other information. 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isLookupPtrRegClass - Set if this operand is a pointer value and it 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// requires a callback to look up its register class. 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isLookupPtrRegClass() const { return Flags&(1 <<MCOI::LookupPtrRegClass);} 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isPredicate - Set if this is one of the operands that made up of 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// the predicate operand that controls an isPredicable() instruction. 685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isOptionalDef - Set if this operand is a optional def. 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)}; 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// Machine Instruction Flags and Description 78c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)//===----------------------------------------------------------------------===// 79c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// MCInstrDesc flags - These should be considered private to the 815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// implementation of the MCInstrDesc class. Clients should use the predicate 825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// methods on MCInstrDesc, not use these directly. These all correspond to 835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// bitfields in the MCInstrDesc::Flags field. 845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace MCID { 855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) enum { 865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Variadic = 0, 875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) HasOptionalDef, 882a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Return, 892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Call, 902a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) Barrier, 915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Terminator, 925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Branch, 935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) IndirectBranch, 945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Compare, 955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MoveImm, 965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Bitcast, 975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) DelaySlot, 985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) FoldableAsLoad, 995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MayLoad, 1005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MayStore, 1015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Predicable, 1025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) NotDuplicable, 1035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) UnmodeledSideEffects, 1045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Commutable, 1055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ConvertibleTo3Addr, 1065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) UsesCustomInserter, 1075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Rematerializable, 1085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) CheapAsAMove, 1095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ExtraSrcRegAllocReq, 1105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ExtraDefRegAllocReq 1115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 1125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)} 1135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// MCInstrDesc - Describe properties that are true of each instruction in the 1155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// target description file. This captures information about side effects, 1165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// register use and many other things. There is one instance of this struct 1175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// for each target instruction class, and the MachineInstr class points to 1185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// this struct directly to describe itself. 1195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MCInstrDesc { 1205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 1215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned short Opcode; // The opcode number 1225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned short NumOperands; // Num of args (may be more if variable_ops) 1235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned short NumDefs; // Num of args that are definitions 1245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned short SchedClass; // enum identifying instr sched class 1255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned short Size; // Number of bytes in encoding. 1265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const char * Name; // Name of the instruction record in td file 1275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned Flags; // Flags identifying machine instr class 1285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) uint64_t TSFlags; // Target Specific Flag values 1295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const unsigned *ImplicitUses; // Registers implicitly read by this instr 1305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 1315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 1325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getOperandConstraint - Returns the value of the specific constraint if 1345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// it is set. Returns -1 if it is not set. 1355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) int getOperandConstraint(unsigned OpNum, 1365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MCOI::OperandConstraint Constraint) const { 1375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (OpNum < NumOperands && 1385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (OpInfo[OpNum].Constraints & (1 << Constraint))) { 1395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned Pos = 16 + Constraint * 4; 1405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 1415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return -1; 1435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getOpcode - Return the opcode number for this descriptor. 1465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getOpcode() const { 1475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Opcode; 1485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getName - Return the name of the record in the .td file for this 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction, for example "ADD8ri". 1525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const char *getName() const { 1535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Name; 1545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getNumOperands - Return the number of declared MachineOperands for this 1575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// MachineInstruction. Note that variadic (isVariadic() returns true) 1585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instructions may have additional operands at the end of the list, and note 1595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// that the machine instruction may include implicit register def/uses as 1605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// well. 1615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getNumOperands() const { 1625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return NumOperands; 1635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getNumDefs - Return the number of MachineOperands that are register 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// definitions. Register definitions always occur at the start of the 1675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// machine operand list. This is the number of "outs" in the .td file, 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// and does not include implicit defs. 1695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getNumDefs() const { 1705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return NumDefs; 1715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isVariadic - Return true if this instruction can have a variable number of 1745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// operands. In this case, the variable operands will be after the normal 1755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// operands but before the implicit definitions and uses (if any are 1765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// present). 1775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isVariadic() const { 1785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Flags & (1 << MCID::Variadic); 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// ARM instructions which can set condition code if 's' bit is set. 1835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool hasOptionalDef() const { 1845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Flags & (1 << MCID::HasOptionalDef); 1855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getImplicitUses - Return a list of registers that are potentially 188a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// read by any instance of this machine instruction. For example, on X86, 189a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// the "adc" instruction adds two register operands and adds the carry bit in 190a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) /// from the flags register. In this case, the instruction is marked as 1915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// implicitly reading the flags. Likewise, the variable shift instruction on 1925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// X86 is marked as implicitly reading the 'CL' register, which it always 1935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// does. 1945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This method returns null if the instruction has no implicit uses. 1965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const unsigned *getImplicitUses() const { 1975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return ImplicitUses; 1985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getNumImplicitUses - Return the number of implicit uses this instruction 2015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// has. 2025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getNumImplicitUses() const { 2035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (ImplicitUses == 0) return 0; 2045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned i = 0; 2055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) for (; ImplicitUses[i]; ++i) /*empty*/; 2065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return i; 2075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getImplicitDefs - Return a list of registers that are potentially 2105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// written by any instance of this machine instruction. For example, on X86, 211 /// many instructions implicitly set the flags register. In this case, they 212 /// are marked as setting the FLAGS. Likewise, many instructions always 213 /// deposit their result in a physical register. For example, the X86 divide 214 /// instruction always deposits the quotient and remainder in the EAX/EDX 215 /// registers. For that instruction, this will return a list containing the 216 /// EAX/EDX/EFLAGS registers. 217 /// 218 /// This method returns null if the instruction has no implicit defs. 219 const unsigned *getImplicitDefs() const { 220 return ImplicitDefs; 221 } 222 223 /// getNumImplicitDefs - Return the number of implicit defs this instruction 224 /// has. 225 unsigned getNumImplicitDefs() const { 226 if (ImplicitDefs == 0) return 0; 227 unsigned i = 0; 228 for (; ImplicitDefs[i]; ++i) /*empty*/; 229 return i; 230 } 231 232 /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly 233 /// uses the specified physical register. 234 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 235 if (const unsigned *ImpUses = ImplicitUses) 236 for (; *ImpUses; ++ImpUses) 237 if (*ImpUses == Reg) return true; 238 return false; 239 } 240 241 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly 242 /// defines the specified physical register. 243 bool hasImplicitDefOfPhysReg(unsigned Reg) const { 244 if (const unsigned *ImpDefs = ImplicitDefs) 245 for (; *ImpDefs; ++ImpDefs) 246 if (*ImpDefs == Reg) return true; 247 return false; 248 } 249 250 /// getSchedClass - Return the scheduling class for this instruction. The 251 /// scheduling class is an index into the InstrItineraryData table. This 252 /// returns zero if there is no known scheduling information for the 253 /// instruction. 254 /// 255 unsigned getSchedClass() const { 256 return SchedClass; 257 } 258 259 /// getSize - Return the number of bytes in the encoding of this instruction, 260 /// or zero if the encoding size cannot be known from the opcode. 261 unsigned getSize() const { 262 return Size; 263 } 264 265 bool isReturn() const { 266 return Flags & (1 << MCID::Return); 267 } 268 269 bool isCall() const { 270 return Flags & (1 << MCID::Call); 271 } 272 273 /// isBarrier - Returns true if the specified instruction stops control flow 274 /// from executing the instruction immediately following it. Examples include 275 /// unconditional branches and return instructions. 276 bool isBarrier() const { 277 return Flags & (1 << MCID::Barrier); 278 } 279 280 /// isTerminator - Returns true if this instruction part of the terminator for 281 /// a basic block. Typically this is things like return and branch 282 /// instructions. 283 /// 284 /// Various passes use this to insert code into the bottom of a basic block, 285 /// but before control flow occurs. 286 bool isTerminator() const { 287 return Flags & (1 << MCID::Terminator); 288 } 289 290 /// isBranch - Returns true if this is a conditional, unconditional, or 291 /// indirect branch. Predicates below can be used to discriminate between 292 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 293 /// get more information. 294 bool isBranch() const { 295 return Flags & (1 << MCID::Branch); 296 } 297 298 /// isIndirectBranch - Return true if this is an indirect branch, such as a 299 /// branch through a register. 300 bool isIndirectBranch() const { 301 return Flags & (1 << MCID::IndirectBranch); 302 } 303 304 /// isConditionalBranch - Return true if this is a branch which may fall 305 /// through to the next instruction or may transfer control flow to some other 306 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 307 /// information about this branch. 308 bool isConditionalBranch() const { 309 return isBranch() & !isBarrier() & !isIndirectBranch(); 310 } 311 312 /// isUnconditionalBranch - Return true if this is a branch which always 313 /// transfers control flow to some other block. The 314 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 315 /// about this branch. 316 bool isUnconditionalBranch() const { 317 return isBranch() & isBarrier() & !isIndirectBranch(); 318 } 319 320 // isPredicable - Return true if this instruction has a predicate operand that 321 // controls execution. It may be set to 'always', or may be set to other 322 /// values. There are various methods in TargetInstrInfo that can be used to 323 /// control and modify the predicate in this instruction. 324 bool isPredicable() const { 325 return Flags & (1 << MCID::Predicable); 326 } 327 328 /// isCompare - Return true if this instruction is a comparison. 329 bool isCompare() const { 330 return Flags & (1 << MCID::Compare); 331 } 332 333 /// isMoveImmediate - Return true if this instruction is a move immediate 334 /// (including conditional moves) instruction. 335 bool isMoveImmediate() const { 336 return Flags & (1 << MCID::MoveImm); 337 } 338 339 /// isBitcast - Return true if this instruction is a bitcast instruction. 340 /// 341 bool isBitcast() const { 342 return Flags & (1 << MCID::Bitcast); 343 } 344 345 /// isNotDuplicable - Return true if this instruction cannot be safely 346 /// duplicated. For example, if the instruction has a unique labels attached 347 /// to it, duplicating it would cause multiple definition errors. 348 bool isNotDuplicable() const { 349 return Flags & (1 << MCID::NotDuplicable); 350 } 351 352 /// hasDelaySlot - Returns true if the specified instruction has a delay slot 353 /// which must be filled by the code generator. 354 bool hasDelaySlot() const { 355 return Flags & (1 << MCID::DelaySlot); 356 } 357 358 /// canFoldAsLoad - Return true for instructions that can be folded as 359 /// memory operands in other instructions. The most common use for this 360 /// is instructions that are simple loads from memory that don't modify 361 /// the loaded value in any way, but it can also be used for instructions 362 /// that can be expressed as constant-pool loads, such as V_SETALLONES 363 /// on x86, to allow them to be folded when it is beneficial. 364 /// This should only be set on instructions that return a value in their 365 /// only virtual register definition. 366 bool canFoldAsLoad() const { 367 return Flags & (1 << MCID::FoldableAsLoad); 368 } 369 370 //===--------------------------------------------------------------------===// 371 // Side Effect Analysis 372 //===--------------------------------------------------------------------===// 373 374 /// mayLoad - Return true if this instruction could possibly read memory. 375 /// Instructions with this flag set are not necessarily simple load 376 /// instructions, they may load a value and modify it, for example. 377 bool mayLoad() const { 378 return Flags & (1 << MCID::MayLoad); 379 } 380 381 382 /// mayStore - Return true if this instruction could possibly modify memory. 383 /// Instructions with this flag set are not necessarily simple store 384 /// instructions, they may store a modified value based on their operands, or 385 /// may not actually modify anything, for example. 386 bool mayStore() const { 387 return Flags & (1 << MCID::MayStore); 388 } 389 390 /// hasUnmodeledSideEffects - Return true if this instruction has side 391 /// effects that are not modeled by other flags. This does not return true 392 /// for instructions whose effects are captured by: 393 /// 394 /// 1. Their operand list and implicit definition/use list. Register use/def 395 /// info is explicit for instructions. 396 /// 2. Memory accesses. Use mayLoad/mayStore. 397 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 398 /// 399 /// Examples of side effects would be modifying 'invisible' machine state like 400 /// a control register, flushing a cache, modifying a register invisible to 401 /// LLVM, etc. 402 /// 403 bool hasUnmodeledSideEffects() const { 404 return Flags & (1 << MCID::UnmodeledSideEffects); 405 } 406 407 //===--------------------------------------------------------------------===// 408 // Flags that indicate whether an instruction can be modified by a method. 409 //===--------------------------------------------------------------------===// 410 411 /// isCommutable - Return true if this may be a 2- or 3-address 412 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 413 /// result if Y and Z are exchanged. If this flag is set, then the 414 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 415 /// instruction. 416 /// 417 /// Note that this flag may be set on instructions that are only commutable 418 /// sometimes. In these cases, the call to commuteInstruction will fail. 419 /// Also note that some instructions require non-trivial modification to 420 /// commute them. 421 bool isCommutable() const { 422 return Flags & (1 << MCID::Commutable); 423 } 424 425 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 426 /// which can be changed into a 3-address instruction if needed. Doing this 427 /// transformation can be profitable in the register allocator, because it 428 /// means that the instruction can use a 2-address form if possible, but 429 /// degrade into a less efficient form if the source and dest register cannot 430 /// be assigned to the same register. For example, this allows the x86 431 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 432 /// is the same speed as the shift but has bigger code size. 433 /// 434 /// If this returns true, then the target must implement the 435 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 436 /// is allowed to fail if the transformation isn't valid for this specific 437 /// instruction (e.g. shl reg, 4 on x86). 438 /// 439 bool isConvertibleTo3Addr() const { 440 return Flags & (1 << MCID::ConvertibleTo3Addr); 441 } 442 443 /// usesCustomInsertionHook - Return true if this instruction requires 444 /// custom insertion support when the DAG scheduler is inserting it into a 445 /// machine basic block. If this is true for the instruction, it basically 446 /// means that it is a pseudo instruction used at SelectionDAG time that is 447 /// expanded out into magic code by the target when MachineInstrs are formed. 448 /// 449 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 450 /// is used to insert this into the MachineBasicBlock. 451 bool usesCustomInsertionHook() const { 452 return Flags & (1 << MCID::UsesCustomInserter); 453 } 454 455 /// isRematerializable - Returns true if this instruction is a candidate for 456 /// remat. This flag is deprecated, please don't use it anymore. If this 457 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 458 /// verify the instruction is really rematable. 459 bool isRematerializable() const { 460 return Flags & (1 << MCID::Rematerializable); 461 } 462 463 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 464 /// less) than a move instruction. This is useful during certain types of 465 /// optimizations (e.g., remat during two-address conversion or machine licm) 466 /// where we would like to remat or hoist the instruction, but not if it costs 467 /// more than moving the instruction into the appropriate register. Note, we 468 /// are not marking copies from and to the same register class with this flag. 469 bool isAsCheapAsAMove() const { 470 return Flags & (1 << MCID::CheapAsAMove); 471 } 472 473 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 474 /// have special register allocation requirements that are not captured by the 475 /// operand register classes. e.g. ARM::STRD's two source registers must be an 476 /// even / odd pair, ARM::STM registers have to be in ascending order. 477 /// Post-register allocation passes should not attempt to change allocations 478 /// for sources of instructions with this flag. 479 bool hasExtraSrcRegAllocReq() const { 480 return Flags & (1 << MCID::ExtraSrcRegAllocReq); 481 } 482 483 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 484 /// have special register allocation requirements that are not captured by the 485 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 486 /// even / odd pair, ARM::LDM registers have to be in ascending order. 487 /// Post-register allocation passes should not attempt to change allocations 488 /// for definitions of instructions with this flag. 489 bool hasExtraDefRegAllocReq() const { 490 return Flags & (1 << MCID::ExtraDefRegAllocReq); 491 } 492}; 493 494} // end namespace llvm 495 496#endif 497