MCInstrDesc.h revision 22fee2dff4c43b551aefa44a96ca74fcade6bfac
1e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 3d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// The LLVM Compiler Infrastructure 4d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 5d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// This file is distributed under the University of Illinois Open Source 6d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// License. See LICENSE.TXT for details. 7d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 8d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 9d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 1022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng// This file defines the MCOperandInfo and MCInstrDesc classes, which 11d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// are used to describe target instructions and their operands. 12d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 13d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 14d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#ifndef LLVM_MC_MCINSTRDESC_H 16e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#define LLVM_MC_MCINSTRDESC_H 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 181f6efa3996dd1929fbc129203ce5009b620e6969Michael J. Spencer#include "llvm/Support/DataTypes.h" 1999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 20d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnernamespace llvm { 21d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 22d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 23d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Operand Flags and Description 24d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 25d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 26e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCOI { 2706801722a43c697eff0acee905de6b50257ce19bJim Grosbach // Operand constraints 28d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandConstraint { 2906801722a43c697eff0acee905de6b50257ce19bJim Grosbach TIED_TO = 0, // Must be allocated the same register as. 3006801722a43c697eff0acee905de6b50257ce19bJim Grosbach EARLY_CLOBBER // Operand is an early clobber register operand 31d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 32d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 33d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// OperandFlags - These are flags set on operands, but should be considered 34e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// private, all access should go through the MCOperandInfo accessors. 35d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// See the accessors for a description of what these are. 36d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandFlags { 37d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner LookupPtrRegClass = 0, 38d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Predicate, 39d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner OptionalDef 40d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 41d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 42d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 43e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCOperandInfo - This holds information about one operand of a machine 44d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// instruction, indicating the register class for register operands, etc. 45d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// 46e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCOperandInfo { 47d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 48d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// RegClass - This specifies the register class enumeration of the operand 49cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// if the operand is a register. If isLookupPtrRegClass is set, then this is 50cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 51cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// get a dynamic register class. 52a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman short RegClass; 53cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner 54e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// Flags - These are flags from the MCOI::OperandFlags enum. 55d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short Flags; 56cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner 57d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Lower 16 bits are used to specify which constraints are set. The higher 16 58d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// bits are used to specify the value of constraints (4 bits each). 59cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner unsigned Constraints; 60d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Currently no other information. 61d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 62d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isLookupPtrRegClass - Set if this operand is a pointer value and it 63d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// requires a callback to look up its register class. 64e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isLookupPtrRegClass() const { return Flags&(1 <<MCOI::LookupPtrRegClass);} 65d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 66d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isPredicate - Set if this is one of the operands that made up of 67d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the predicate operand that controls an isPredicable() instruction. 68e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 69d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 70d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isOptionalDef - Set if this operand is a optional def. 71d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 72e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 73d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 74d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 75d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 76d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 77d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Instruction Flags and Description 78d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 79d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 80e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc flags - These should be considered private to the 81e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// implementation of the MCInstrDesc class. Clients should use the predicate 82e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// methods on MCInstrDesc, not use these directly. These all correspond to 83e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// bitfields in the MCInstrDesc::Flags field. 84e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCID { 85d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum { 86d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Variadic = 0, 87d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner HasOptionalDef, 88d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Return, 89d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Call, 90d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Barrier, 91d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Terminator, 92d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Branch, 93d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner IndirectBranch, 9473739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling Compare, 95c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MoveImm, 960f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng Bitcast, 97d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner DelaySlot, 9815511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman FoldableAsLoad, 99dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner MayLoad, 100d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner MayStore, 101c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Predicable, 102c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NotDuplicable, 103a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner UnmodeledSideEffects, 104d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Commutable, 105d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner ConvertibleTo3Addr, 106533297b58da8c74bec65551e1aface9801fc2259Dan Gohman UsesCustomInserter, 1078370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling Rematerializable, 108799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng CheapAsAMove, 109799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraSrcRegAllocReq, 110799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraDefRegAllocReq 111d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 112d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 113d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 114e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc - Describe properties that are true of each instruction in the 115e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// target description file. This captures information about side effects, 116e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// register use and many other things. There is one instance of this struct 117e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// for each target instruction class, and the MachineInstr class points to 118e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// this struct directly to describe itself. 119e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCInstrDesc { 120d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 121b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short Opcode; // The opcode number 122d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short NumOperands; // Num of args (may be more if variable_ops) 123b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short NumDefs; // Num of args that are definitions 124d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short SchedClass; // enum identifying instr sched class 125b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng const char * Name; // Name of the instruction record in td file 126b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned Flags; // Flags identifying machine instr class 12799405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags; // Target Specific Flag values 128d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 129d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 130e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 131d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 132d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getOperandConstraint - Returns the value of the specific constraint if 133d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// it is set. Returns -1 if it is not set. 134d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner int getOperandConstraint(unsigned OpNum, 135e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCOI::OperandConstraint Constraint) const { 136d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner if (OpNum < NumOperands && 137d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner (OpInfo[OpNum].Constraints & (1 << Constraint))) { 138d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned Pos = 16 + Constraint * 4; 139d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 140d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 141d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return -1; 142d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 143d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 144d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getOpcode - Return the opcode number for this descriptor. 145d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getOpcode() const { 146d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Opcode; 147d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 148d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 149d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getName - Return the name of the record in the .td file for this 150d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction, for example "ADD8ri". 151d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const char *getName() const { 152d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Name; 153d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 154d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 155d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getNumOperands - Return the number of declared MachineOperands for this 156d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// MachineInstruction. Note that variadic (isVariadic() returns true) 157d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions may have additional operands at the end of the list, and note 158d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// that the machine instruction may include implicit register def/uses as 159d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// well. 160d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumOperands() const { 161d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumOperands; 162d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 163d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 164d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getNumDefs - Return the number of MachineOperands that are register 165d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// definitions. Register definitions always occur at the start of the 166b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// machine operand list. This is the number of "outs" in the .td file, 167b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// and does not include implicit defs. 168d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumDefs() const { 169d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumDefs; 170d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 171d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 172d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isVariadic - Return true if this instruction can have a variable number of 173d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands. In this case, the variable operands will be after the normal 174d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands but before the implicit definitions and uses (if any are 175d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// present). 176d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isVariadic() const { 177e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Variadic); 178d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 179d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 180d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 181d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// ARM instructions which can set condition code if 's' bit is set. 182d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasOptionalDef() const { 183e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::HasOptionalDef); 184d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 185d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 186920c6828ee2a31b324e2b0a9d16e01574955485dDan Gohman /// getImplicitUses - Return a list of registers that are potentially 187d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// read by any instance of this machine instruction. For example, on X86, 188d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the "adc" instruction adds two register operands and adds the carry bit in 189d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from the flags register. In this case, the instruction is marked as 190d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// implicitly reading the flags. Likewise, the variable shift instruction on 191d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// X86 is marked as implicitly reading the 'CL' register, which it always 192d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// does. 193d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 194d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// This method returns null if the instruction has no implicit uses. 195d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *getImplicitUses() const { 196d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return ImplicitUses; 197d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 198e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng 199375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// getNumImplicitUses - Return the number of implicit uses this instruction 200375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// has. 201375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned getNumImplicitUses() const { 202375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner if (ImplicitUses == 0) return 0; 203375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned i = 0; 204375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner for (; ImplicitUses[i]; ++i) /*empty*/; 205375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner return i; 206375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner } 207e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng 208920c6828ee2a31b324e2b0a9d16e01574955485dDan Gohman /// getImplicitDefs - Return a list of registers that are potentially 209d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// written by any instance of this machine instruction. For example, on X86, 210d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// many instructions implicitly set the flags register. In this case, they 211d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// are marked as setting the FLAGS. Likewise, many instructions always 212d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// deposit their result in a physical register. For example, the X86 divide 213d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction always deposits the quotient and remainder in the EAX/EDX 214d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// registers. For that instruction, this will return a list containing the 215d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// EAX/EDX/EFLAGS registers. 216d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 217920c6828ee2a31b324e2b0a9d16e01574955485dDan Gohman /// This method returns null if the instruction has no implicit defs. 218d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *getImplicitDefs() const { 219d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return ImplicitDefs; 220d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2210461c0a8f5b476794a061e995210906670a4542dChris Lattner 222375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// getNumImplicitDefs - Return the number of implicit defs this instruction 223375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// has. 224375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned getNumImplicitDefs() const { 225375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner if (ImplicitDefs == 0) return 0; 226375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned i = 0; 227375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner for (; ImplicitDefs[i]; ++i) /*empty*/; 228375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner return i; 229375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner } 230375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner 2310461c0a8f5b476794a061e995210906670a4542dChris Lattner /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly 2320461c0a8f5b476794a061e995210906670a4542dChris Lattner /// uses the specified physical register. 2330461c0a8f5b476794a061e995210906670a4542dChris Lattner bool hasImplicitUseOfPhysReg(unsigned Reg) const { 2340461c0a8f5b476794a061e995210906670a4542dChris Lattner if (const unsigned *ImpUses = ImplicitUses) 2350461c0a8f5b476794a061e995210906670a4542dChris Lattner for (; *ImpUses; ++ImpUses) 2360461c0a8f5b476794a061e995210906670a4542dChris Lattner if (*ImpUses == Reg) return true; 2370461c0a8f5b476794a061e995210906670a4542dChris Lattner return false; 2380461c0a8f5b476794a061e995210906670a4542dChris Lattner } 2390461c0a8f5b476794a061e995210906670a4542dChris Lattner 2400461c0a8f5b476794a061e995210906670a4542dChris Lattner /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly 2410461c0a8f5b476794a061e995210906670a4542dChris Lattner /// defines the specified physical register. 2420461c0a8f5b476794a061e995210906670a4542dChris Lattner bool hasImplicitDefOfPhysReg(unsigned Reg) const { 2430461c0a8f5b476794a061e995210906670a4542dChris Lattner if (const unsigned *ImpDefs = ImplicitDefs) 2440461c0a8f5b476794a061e995210906670a4542dChris Lattner for (; *ImpDefs; ++ImpDefs) 2450461c0a8f5b476794a061e995210906670a4542dChris Lattner if (*ImpDefs == Reg) return true; 2460461c0a8f5b476794a061e995210906670a4542dChris Lattner return false; 2470461c0a8f5b476794a061e995210906670a4542dChris Lattner } 248d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 249d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getSchedClass - Return the scheduling class for this instruction. The 250d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// scheduling class is an index into the InstrItineraryData table. This 251d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// returns zero if there is no known scheduling information for the 252d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 253d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 254d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getSchedClass() const { 255d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return SchedClass; 256d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 257d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 258d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isReturn() const { 259e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Return); 260d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 261d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 262d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCall() const { 263e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Call); 264d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 265d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 266d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 267d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from executing the instruction immediately following it. Examples include 268d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// unconditional branches and return instructions. 269d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBarrier() const { 270e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Barrier); 271d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 272d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 273d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isTerminator - Returns true if this instruction part of the terminator for 274d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// a basic block. Typically this is things like return and branch 275d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions. 276d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 277d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Various passes use this to insert code into the bottom of a basic block, 278d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// but before control flow occurs. 279d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isTerminator() const { 280e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Terminator); 281d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 282d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 283d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isBranch - Returns true if this is a conditional, unconditional, or 284d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// indirect branch. Predicates below can be used to discriminate between 285d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 286d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// get more information. 287d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBranch() const { 288e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Branch); 289d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 290d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 291d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isIndirectBranch - Return true if this is an indirect branch, such as a 292d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// branch through a register. 293d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isIndirectBranch() const { 294e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::IndirectBranch); 295d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 29673739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 297d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConditionalBranch - Return true if this is a branch which may fall 298d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// through to the next instruction or may transfer control flow to some other 299d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 300d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// information about this branch. 301d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConditionalBranch() const { 302d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & !isBarrier() & !isIndirectBranch(); 303d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 304d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 305d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isUnconditionalBranch - Return true if this is a branch which always 306d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transfers control flow to some other block. The 307d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 308d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// about this branch. 309d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isUnconditionalBranch() const { 310d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & isBarrier() & !isIndirectBranch(); 311d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 312d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 313d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // isPredicable - Return true if this instruction has a predicate operand that 314d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // controls execution. It may be set to 'always', or may be set to other 315d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// values. There are various methods in TargetInstrInfo that can be used to 316d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// control and modify the predicate in this instruction. 317d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isPredicable() const { 318e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Predicable); 319d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 320d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 32173739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling /// isCompare - Return true if this instruction is a comparison. 32273739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling bool isCompare() const { 323e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Compare); 32473739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling } 32573739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 326c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// isMoveImmediate - Return true if this instruction is a move immediate 327c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// (including conditional moves) instruction. 328c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isMoveImmediate() const { 329e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MoveImm); 330c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 3310f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng 3320f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng /// isBitcast - Return true if this instruction is a bitcast instruction. 3330f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng /// 3340f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng bool isBitcast() const { 335e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Bitcast); 3360f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng } 337c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng 338d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isNotDuplicable - Return true if this instruction cannot be safely 339d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// duplicated. For example, if the instruction has a unique labels attached 340d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// to it, duplicating it would cause multiple definition errors. 341d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isNotDuplicable() const { 342e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::NotDuplicable); 343d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 344d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 345d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 346d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which must be filled by the code generator. 347d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasDelaySlot() const { 348e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::DelaySlot); 349d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 350d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 35115511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman /// canFoldAsLoad - Return true for instructions that can be folded as 35262c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// memory operands in other instructions. The most common use for this 35362c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// is instructions that are simple loads from memory that don't modify 35462c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// the loaded value in any way, but it can also be used for instructions 35562c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// that can be expressed as constant-pool loads, such as V_SETALLONES 35662c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// on x86, to allow them to be folded when it is beneficial. 35762c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// This should only be set on instructions that return a value in their 35862c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// only virtual register definition. 35915511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman bool canFoldAsLoad() const { 360e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::FoldableAsLoad); 361d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 362d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 363d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 364d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Side Effect Analysis 365d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 366dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 367dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// mayLoad - Return true if this instruction could possibly read memory. 368dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// Instructions with this flag set are not necessarily simple load 369dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// instructions, they may load a value and modify it, for example. 370dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner bool mayLoad() const { 371e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayLoad); 372dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner } 373dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 374d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 375d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// mayStore - Return true if this instruction could possibly modify memory. 376d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Instructions with this flag set are not necessarily simple store 377d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions, they may store a modified value based on their operands, or 378d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// may not actually modify anything, for example. 379d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool mayStore() const { 380e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayStore); 381d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 382d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 383a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// hasUnmodeledSideEffects - Return true if this instruction has side 384a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// effects that are not modeled by other flags. This does not return true 385a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// for instructions whose effects are captured by: 386d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 387a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 1. Their operand list and implicit definition/use list. Register use/def 388a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// info is explicit for instructions. 389a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 2. Memory accesses. Use mayLoad/mayStore. 390a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 391d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 392a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// Examples of side effects would be modifying 'invisible' machine state like 393a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// a control register, flushing a cache, modifying a register invisible to 394a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// LLVM, etc. 395d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 396a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner bool hasUnmodeledSideEffects() const { 397e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UnmodeledSideEffects); 398d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 399d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 400d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 401d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Flags that indicate whether an instruction can be modified by a method. 402d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 403d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 404d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isCommutable - Return true if this may be a 2- or 3-address 405d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (of the form "X = op Y, Z, ..."), which produces the same 406d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// result if Y and Z are exchanged. If this flag is set, then the 407d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::commuteInstruction method may be used to hack on the 408d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 409d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 410d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Note that this flag may be set on instructions that are only commutable 411d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// sometimes. In these cases, the call to commuteInstruction will fail. 412d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Also note that some instructions require non-trivial modification to 413d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// commute them. 414d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCommutable() const { 415e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Commutable); 416d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 417d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 418d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 419d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which can be changed into a 3-address instruction if needed. Doing this 420d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transformation can be profitable in the register allocator, because it 421d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// means that the instruction can use a 2-address form if possible, but 422d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// degrade into a less efficient form if the source and dest register cannot 423d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// be assigned to the same register. For example, this allows the x86 424d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 425d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is the same speed as the shift but has bigger code size. 426d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 427d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this returns true, then the target must implement the 428d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 429d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is allowed to fail if the transformation isn't valid for this specific 430d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (e.g. shl reg, 4 on x86). 431d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 432d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConvertibleTo3Addr() const { 433e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ConvertibleTo3Addr); 434d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 435d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 436533297b58da8c74bec65551e1aface9801fc2259Dan Gohman /// usesCustomInsertionHook - Return true if this instruction requires 437d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 438d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// machine basic block. If this is true for the instruction, it basically 439d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// means that it is a pseudo instruction used at SelectionDAG time that is 440d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// expanded out into magic code by the target when MachineInstrs are formed. 441d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 442d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 443d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is used to insert this into the MachineBasicBlock. 444533297b58da8c74bec65551e1aface9801fc2259Dan Gohman bool usesCustomInsertionHook() const { 445e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UsesCustomInserter); 446d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 447d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 448d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isRematerializable - Returns true if this instruction is a candidate for 449d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// remat. This flag is deprecated, please don't use it anymore. If this 450d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// flag is set, the isReallyTriviallyReMaterializable() method is called to 451d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// verify the instruction is really rematable. 452d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isRematerializable() const { 453e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Rematerializable); 454d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4558370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling 4568370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 4578370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// less) than a move instruction. This is useful during certain types of 458758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// optimizations (e.g., remat during two-address conversion or machine licm) 459758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// where we would like to remat or hoist the instruction, but not if it costs 460758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// more than moving the instruction into the appropriate register. Note, we 461758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// are not marking copies from and to the same register class with this flag. 4628370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling bool isAsCheapAsAMove() const { 463e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::CheapAsAMove); 4648370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling } 465799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 466799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 467799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 468799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::STRD's two source registers must be an 469799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::STM registers have to be in ascending order. 470799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 471799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for sources of instructions with this flag. 472799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraSrcRegAllocReq() const { 473e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraSrcRegAllocReq); 474799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 475799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 476799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 477799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 478799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::LDRD's two def registers must be an 479799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::LDM registers have to be in ascending order. 480799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 481799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for definitions of instructions with this flag. 482799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraDefRegAllocReq() const { 483e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraDefRegAllocReq); 484799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 485d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 486d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 487d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} // end namespace llvm 488d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 489d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#endif 490