MCInstrDesc.h revision 715d98d657491b3fb8ea0e14643e9801b2f9628c
17f8f3f7f6400291d30531c88a98511f9fc626b4cChad Rosier//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 3d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// The LLVM Compiler Infrastructure 4d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 5d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// This file is distributed under the University of Illinois Open Source 6d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// License. See LICENSE.TXT for details. 7d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 8d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 9d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 1022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng// This file defines the MCOperandInfo and MCInstrDesc classes, which 110ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach// are used to describe target instructions and their operands. 12d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 13d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 14d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#ifndef LLVM_MC_MCINSTRDESC_H 16e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#define LLVM_MC_MCINSTRDESC_H 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 18fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach#include "llvm/MC/MCInst.h" 1958a2cbef4aac9ee7d530dfb690c78d6fc11a2371Chandler Carruth#include "llvm/MC/MCRegisterInfo.h" 20715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly#include "llvm/MC/MCSubtargetInfo.h" 2158a2cbef4aac9ee7d530dfb690c78d6fc11a2371Chandler Carruth#include "llvm/Support/DataTypes.h" 2299405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 23d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnernamespace llvm { 24d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 25d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 26d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Operand Flags and Description 27d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 280ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 29e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCOI { 3006801722a43c697eff0acee905de6b50257ce19bJim Grosbach // Operand constraints 31d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandConstraint { 3206801722a43c697eff0acee905de6b50257ce19bJim Grosbach TIED_TO = 0, // Must be allocated the same register as. 3306801722a43c697eff0acee905de6b50257ce19bJim Grosbach EARLY_CLOBBER // Operand is an early clobber register operand 34d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 350ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 36d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// OperandFlags - These are flags set on operands, but should be considered 37e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// private, all access should go through the MCOperandInfo accessors. 38d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// See the accessors for a description of what these are. 39d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandFlags { 40d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner LookupPtrRegClass = 0, 41d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Predicate, 42d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner OptionalDef 43d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 445196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer 455196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer /// Operand Type - Operands are tagged with one of the values of this enum. 465196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer enum OperandType { 475196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_UNKNOWN, 485196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_IMMEDIATE, 495196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_REGISTER, 505196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_MEMORY, 515196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_PCREL 525196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer }; 53d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 54d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 55e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCOperandInfo - This holds information about one operand of a machine 56d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// instruction, indicating the register class for register operands, etc. 57d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// 58e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCOperandInfo { 59d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 600ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// RegClass - This specifies the register class enumeration of the operand 61cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// if the operand is a register. If isLookupPtrRegClass is set, then this is 62cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 63cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// get a dynamic register class. 6439bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper int16_t RegClass; 650ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 66e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// Flags - These are flags from the MCOI::OperandFlags enum. 6739bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t Flags; 6839bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper 6939bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper /// OperandType - Information about the type of the operand. 7039bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t OperandType; 710ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 72d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Lower 16 bits are used to specify which constraints are set. The higher 16 73d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// bits are used to specify the value of constraints (4 bits each). 7439bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint32_t Constraints; 75d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Currently no other information. 760ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 77d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isLookupPtrRegClass - Set if this operand is a pointer value and it 78d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// requires a callback to look up its register class. 797e0d22cbf7b41e93279f574c9b3c557cdf517dcbJim Grosbach bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);} 800ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 81d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isPredicate - Set if this is one of the operands that made up of 82d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the predicate operand that controls an isPredicable() instruction. 83e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 840ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 85d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isOptionalDef - Set if this operand is a optional def. 86d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 87e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 88d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 89d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 900ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 91d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 92d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Instruction Flags and Description 93d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 94d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 95e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc flags - These should be considered private to the 96e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// implementation of the MCInstrDesc class. Clients should use the predicate 97e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// methods on MCInstrDesc, not use these directly. These all correspond to 98e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// bitfields in the MCInstrDesc::Flags field. 99e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCID { 100d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum { 101d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Variadic = 0, 102d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner HasOptionalDef, 103c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen Pseudo, 104d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Return, 105d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Call, 106d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Barrier, 107d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Terminator, 108d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Branch, 109d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner IndirectBranch, 11073739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling Compare, 111c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MoveImm, 1120f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng Bitcast, 113f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen Select, 114d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner DelaySlot, 11515511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman FoldableAsLoad, 116dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner MayLoad, 117d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner MayStore, 118c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Predicable, 119c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NotDuplicable, 120a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner UnmodeledSideEffects, 121d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Commutable, 122d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner ConvertibleTo3Addr, 123533297b58da8c74bec65551e1aface9801fc2259Dan Gohman UsesCustomInserter, 12437fefc20d3a1e3934a377567d54a141f67752227Evan Cheng HasPostISelHook, 1258370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling Rematerializable, 126799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng CheapAsAMove, 127799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraSrcRegAllocReq, 128799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraDefRegAllocReq 129d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 130d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 131d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 132e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc - Describe properties that are true of each instruction in the 133e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// target description file. This captures information about side effects, 134e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// register use and many other things. There is one instance of this struct 135e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// for each target instruction class, and the MachineInstr class points to 136e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// this struct directly to describe itself. 137e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCInstrDesc { 138d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 139b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short Opcode; // The opcode number 140d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short NumOperands; // Num of args (may be more if variable_ops) 141b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short NumDefs; // Num of args that are definitions 142d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short SchedClass; // enum identifying instr sched class 14316884415db751c75f2133bd04921393c792b1158Owen Anderson unsigned short Size; // Number of bytes in encoding. 144b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned Flags; // Flags identifying machine instr class 14599405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags; // Target Specific Flag values 146fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *ImplicitUses; // Registers implicitly read by this instr 147fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr 148e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 149715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any 150715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly // A complex method to determine is a certain is deprecated or not, and return 151715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly // the reason for deprecation. 152715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &); 153d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns the value of the specific constraint if 155d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// it is set. Returns -1 if it is not set. 156d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner int getOperandConstraint(unsigned OpNum, 157e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCOI::OperandConstraint Constraint) const { 158d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner if (OpNum < NumOperands && 159d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner (OpInfo[OpNum].Constraints & (1 << Constraint))) { 160d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned Pos = 16 + Constraint * 4; 161d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 162d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 163d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return -1; 164d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 165d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 166715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly /// \brief Returns true if a certain instruction is deprecated and if so 167715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly /// returns the reason in \p Info. 168715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI, 169715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly std::string &Info) const { 170715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly if (ComplexDeprecationInfo) 171715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly return ComplexDeprecationInfo(MI, STI, Info); 172715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly if (DeprecatedFeatureMask != 0) { 173715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly // FIXME: it would be nice to include the subtarget feature here. 174715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly Info = "deprecated"; 175715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly return true; 176715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly } 177715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly return false; 178715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly } 179715d98d657491b3fb8ea0e14643e9801b2f9628cJoey Gouly 18046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the opcode number for this descriptor. 181d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getOpcode() const { 182d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Opcode; 183d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1840ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 18546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of declared MachineOperands for this 186d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// MachineInstruction. Note that variadic (isVariadic() returns true) 187d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions may have additional operands at the end of the list, and note 188d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// that the machine instruction may include implicit register def/uses as 189d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// well. 190d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumOperands() const { 191d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumOperands; 192d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1930ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 19446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of MachineOperands that are register 1950ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// definitions. Register definitions always occur at the start of the 196b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// machine operand list. This is the number of "outs" in the .td file, 197b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// and does not include implicit defs. 198d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumDefs() const { 199d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumDefs; 200d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2010ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 20246367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return flags of this instruction. 2035a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getFlags() const { return Flags; } 2047c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng 20546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction can have a variable number of 206d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands. In this case, the variable operands will be after the normal 207d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands but before the implicit definitions and uses (if any are 208d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// present). 209d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isVariadic() const { 210e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Variadic); 211d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2120ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 21346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Set if this instruction has an optional definition, e.g. 214d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// ARM instructions which can set condition code if 's' bit is set. 215d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasOptionalDef() const { 216e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::HasOptionalDef); 217d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2180ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 21946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a pseudo instruction that doesn't 220c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// correspond to a real machine instruction. 221c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// 222c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen bool isPseudo() const { 223c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen return Flags & (1 << MCID::Pseudo); 224c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen } 225c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen 22646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if the instruction is a return. 227d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isReturn() const { 228e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Return); 229d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2300ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 23146367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if the instruction is a call. 232d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCall() const { 233e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Call); 234d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2350ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 23646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if the specified instruction stops control flow 237d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from executing the instruction immediately following it. Examples include 238d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// unconditional branches and return instructions. 239d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBarrier() const { 240e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Barrier); 241d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2420ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 24346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if this instruction part of the terminator for 244d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// a basic block. Typically this is things like return and branch 245d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions. 246d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 247d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Various passes use this to insert code into the bottom of a basic block, 248d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// but before control flow occurs. 249d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isTerminator() const { 250e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Terminator); 251d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2520ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 25346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if this is a conditional, unconditional, or 254d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// indirect branch. Predicates below can be used to discriminate between 255d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 256d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// get more information. 257d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBranch() const { 258e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Branch); 259d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 260d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 26146367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is an indirect branch, such as a 262d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// branch through a register. 263d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isIndirectBranch() const { 264e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::IndirectBranch); 265d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 26673739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 26746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch which may fall 268d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// through to the next instruction or may transfer control flow to some other 269d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 270d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// information about this branch. 271d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConditionalBranch() const { 272d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & !isBarrier() & !isIndirectBranch(); 273d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2740ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 27546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch which always 276d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transfers control flow to some other block. The 277d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 278d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// about this branch. 279d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isUnconditionalBranch() const { 280d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & isBarrier() & !isIndirectBranch(); 281d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2820ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 28346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch or an instruction which directly 284fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// writes to the program counter. Considered 'may' affect rather than 285fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// 'does' affect as things like predication are not taken into account. 286fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const { 287fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (isBranch() || isCall() || isReturn() || isIndirectBranch()) 288fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return true; 289fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach unsigned PC = RI.getProgramCounter(); 290741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach if (PC == 0) 291741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach return false; 292741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach if (hasDefOfPhysReg(MI, PC, RI)) 293741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach return true; 294741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach // A variadic instruction may define PC in the variable operand list. 295741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach // There's currently no indication of which entries in a variable 296741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach // list are defs and which are uses. While that's the case, this function 297741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach // needs to assume they're defs in order to be conservatively correct. 298741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) { 299741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach if (MI.getOperand(i).isReg() && 300741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach RI.isSubRegisterEq(PC, MI.getOperand(i).getReg())) 301741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach return true; 302741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach } 303741e37ed0de4a65eab69e0967a5da3eb1adc01efJim Grosbach return false; 304fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach } 305fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 30646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction has a predicate operand 307dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// that controls execution. It may be set to 'always', or may be set to other 308dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// values. There are various methods in TargetInstrInfo that can be used to 309d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// control and modify the predicate in this instruction. 310d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isPredicable() const { 311e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Predicable); 312d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3130ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 31446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a comparison. 31573739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling bool isCompare() const { 316e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Compare); 31773739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling } 3180ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 31946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a move immediate 3200ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// (including conditional moves) instruction. 321c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isMoveImmediate() const { 322e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MoveImm); 323c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 3240f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng 32546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a bitcast instruction. 3260f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng bool isBitcast() const { 327e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Bitcast); 3280f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng } 3290ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 33046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a select instruction. 331f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen bool isSelect() const { 332f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen return Flags & (1 << MCID::Select); 333f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen } 334f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen 33546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction cannot be safely 336d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// duplicated. For example, if the instruction has a unique labels attached 337d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// to it, duplicating it would cause multiple definition errors. 338d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isNotDuplicable() const { 339e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::NotDuplicable); 340d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3410ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 342d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 343d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which must be filled by the code generator. 344d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasDelaySlot() const { 345e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::DelaySlot); 346d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3470ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 34815511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman /// canFoldAsLoad - Return true for instructions that can be folded as 34962c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// memory operands in other instructions. The most common use for this 35062c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// is instructions that are simple loads from memory that don't modify 35162c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// the loaded value in any way, but it can also be used for instructions 35262c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// that can be expressed as constant-pool loads, such as V_SETALLONES 35362c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// on x86, to allow them to be folded when it is beneficial. 35462c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// This should only be set on instructions that return a value in their 35562c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// only virtual register definition. 35615511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman bool canFoldAsLoad() const { 357e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::FoldableAsLoad); 358d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3590ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 360d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 361d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Side Effect Analysis 362d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 363dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 36446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction could possibly read memory. 365dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// Instructions with this flag set are not necessarily simple load 366dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// instructions, they may load a value and modify it, for example. 367dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner bool mayLoad() const { 368e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayLoad); 369dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner } 3700ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 3710ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 37246367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction could possibly modify memory. 373d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Instructions with this flag set are not necessarily simple store 374d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions, they may store a modified value based on their operands, or 375d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// may not actually modify anything, for example. 376d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool mayStore() const { 377e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayStore); 378d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3790ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 380a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// hasUnmodeledSideEffects - Return true if this instruction has side 381a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// effects that are not modeled by other flags. This does not return true 382a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// for instructions whose effects are captured by: 383d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 384a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 1. Their operand list and implicit definition/use list. Register use/def 385a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// info is explicit for instructions. 386a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 2. Memory accesses. Use mayLoad/mayStore. 387a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 388d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 389a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// Examples of side effects would be modifying 'invisible' machine state like 390a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// a control register, flushing a cache, modifying a register invisible to 391a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// LLVM, etc. 392d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 393a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner bool hasUnmodeledSideEffects() const { 394e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UnmodeledSideEffects); 395d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3960ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 397d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 398d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Flags that indicate whether an instruction can be modified by a method. 399d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 4000ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 401d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isCommutable - Return true if this may be a 2- or 3-address 402d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (of the form "X = op Y, Z, ..."), which produces the same 4030ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// result if Y and Z are exchanged. If this flag is set, then the 404d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::commuteInstruction method may be used to hack on the 405d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 406d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 407d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Note that this flag may be set on instructions that are only commutable 408d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// sometimes. In these cases, the call to commuteInstruction will fail. 409d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Also note that some instructions require non-trivial modification to 410d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// commute them. 411d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCommutable() const { 412e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Commutable); 413d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4140ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 415d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 416d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which can be changed into a 3-address instruction if needed. Doing this 417d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transformation can be profitable in the register allocator, because it 418d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// means that the instruction can use a 2-address form if possible, but 419d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// degrade into a less efficient form if the source and dest register cannot 420d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// be assigned to the same register. For example, this allows the x86 421d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 422d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is the same speed as the shift but has bigger code size. 423d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 424d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this returns true, then the target must implement the 425d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 426d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is allowed to fail if the transformation isn't valid for this specific 427d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (e.g. shl reg, 4 on x86). 428d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 429d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConvertibleTo3Addr() const { 430e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ConvertibleTo3Addr); 431d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4320ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 433533297b58da8c74bec65551e1aface9801fc2259Dan Gohman /// usesCustomInsertionHook - Return true if this instruction requires 434d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 435d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// machine basic block. If this is true for the instruction, it basically 4360ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// means that it is a pseudo instruction used at SelectionDAG time that is 437d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// expanded out into magic code by the target when MachineInstrs are formed. 438d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 439d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 440d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is used to insert this into the MachineBasicBlock. 441533297b58da8c74bec65551e1aface9801fc2259Dan Gohman bool usesCustomInsertionHook() const { 442e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UsesCustomInserter); 443d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4440ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 44583a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// hasPostISelHook - Return true if this instruction requires *adjustment* 44683a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// after instruction selection by calling a target hook. For example, this 44783a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// can be used to fill in ARM 's' optional operand depending on whether 44883a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// the conditional flag register is used. 44983a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick bool hasPostISelHook() const { 45083a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick return Flags & (1 << MCID::HasPostISelHook); 45183a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick } 45283a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick 453d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isRematerializable - Returns true if this instruction is a candidate for 454d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// remat. This flag is deprecated, please don't use it anymore. If this 455d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// flag is set, the isReallyTriviallyReMaterializable() method is called to 456d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// verify the instruction is really rematable. 457d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isRematerializable() const { 458e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Rematerializable); 459d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4608370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling 4618370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 4628370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// less) than a move instruction. This is useful during certain types of 463758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// optimizations (e.g., remat during two-address conversion or machine licm) 464758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// where we would like to remat or hoist the instruction, but not if it costs 465758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// more than moving the instruction into the appropriate register. Note, we 466758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// are not marking copies from and to the same register class with this flag. 4678370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling bool isAsCheapAsAMove() const { 468e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::CheapAsAMove); 4698370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling } 470799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 471799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 472799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 473799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::STRD's two source registers must be an 474799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::STM registers have to be in ascending order. 475799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 476799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for sources of instructions with this flag. 477799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraSrcRegAllocReq() const { 478e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraSrcRegAllocReq); 479799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 480799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 481799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 482799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 483799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::LDRD's two def registers must be an 484799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::LDM registers have to be in ascending order. 485799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 486799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for definitions of instructions with this flag. 487799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraDefRegAllocReq() const { 488e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraDefRegAllocReq); 489799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 4905a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4915a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4925a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getImplicitUses - Return a list of registers that are potentially 4935a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// read by any instance of this machine instruction. For example, on X86, 4945a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// the "adc" instruction adds two register operands and adds the carry bit in 4955a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// from the flags register. In this case, the instruction is marked as 4965a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// implicitly reading the flags. Likewise, the variable shift instruction on 4975a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// X86 is marked as implicitly reading the 'CL' register, which it always 4985a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// does. 4995a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 5005a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit uses. 501fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *getImplicitUses() const { 5025a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return ImplicitUses; 5035a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5045a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 5050eaf5a503e291cfd6d3ad27b6cc3956be2d4b914Jim Grosbach /// \brief Return the number of implicit uses this instruction has. 5065a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitUses() const { 5075a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (ImplicitUses == 0) return 0; 5085a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 5095a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; ImplicitUses[i]; ++i) /*empty*/; 5105a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5115a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5125a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 5135a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getImplicitDefs - Return a list of registers that are potentially 5145a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// written by any instance of this machine instruction. For example, on X86, 5155a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// many instructions implicitly set the flags register. In this case, they 5165a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// are marked as setting the FLAGS. Likewise, many instructions always 5175a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// deposit their result in a physical register. For example, the X86 divide 5185a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction always deposits the quotient and remainder in the EAX/EDX 5195a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// registers. For that instruction, this will return a list containing the 5205a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// EAX/EDX/EFLAGS registers. 5215a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 5225a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit defs. 523fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *getImplicitDefs() const { 5245a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return ImplicitDefs; 5255a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 52746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of implicit defs this instruct has. 5285a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitDefs() const { 5295a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (ImplicitDefs == 0) return 0; 5305a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 5315a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; ImplicitDefs[i]; ++i) /*empty*/; 5325a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5335a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5345a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 53546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction implicitly 5365a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// uses the specified physical register. 5375a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool hasImplicitUseOfPhysReg(unsigned Reg) const { 538fac259814923d091942b230e7bd002a8d1130bc3Craig Topper if (const uint16_t *ImpUses = ImplicitUses) 5395a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpUses; ++ImpUses) 5405a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (*ImpUses == Reg) return true; 5415a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5425a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5435a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 54446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction implicitly 5455a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// defines the specified physical register. 546fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool hasImplicitDefOfPhysReg(unsigned Reg, 547fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach const MCRegisterInfo *MRI = 0) const { 548fac259814923d091942b230e7bd002a8d1130bc3Craig Topper if (const uint16_t *ImpDefs = ImplicitDefs) 5495a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpDefs; ++ImpDefs) 550fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) 551fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return true; 5525a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5535a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5545a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 55546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction defines the specified physical 556fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// register, either explicitly or implicitly. 557fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 558fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach const MCRegisterInfo &RI) const { 559fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach for (int i = 0, e = NumDefs; i != e; ++i) 560fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (MI.getOperand(i).isReg() && 561fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 562fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return true; 563fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return hasImplicitDefOfPhysReg(Reg, &RI); 564fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach } 565fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 56646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the scheduling class for this instruction. The 5675a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// scheduling class is an index into the InstrItineraryData table. This 5685a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// returns zero if there is no known scheduling information for the 5695a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction. 5705a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getSchedClass() const { 5715a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return SchedClass; 5725a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5735a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 57446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of bytes in the encoding of this instruction, 5755a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// or zero if the encoding size cannot be known from the opcode. 5765a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getSize() const { 5775a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return Size; 5785a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5795a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 58046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Find the index of the first operand in the 5815a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// operand list that is used to represent the predicate. It returns -1 if 5825a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// none is found. 5835a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng int findFirstPredOperandIdx() const { 5845a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (isPredicable()) { 5855a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5865a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (OpInfo[i].isPredicate()) 5875a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5885a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5895a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return -1; 5905a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 591d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 592d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 593d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} // end namespace llvm 594d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 595d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#endif 596