MCInstrDesc.h revision 7c2a4a30e0e16762c75adacebd05ec9fcbccf16b
1e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 3d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// The LLVM Compiler Infrastructure 4d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 5d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// This file is distributed under the University of Illinois Open Source 6d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// License. See LICENSE.TXT for details. 7d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 8d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 9d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 1022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng// This file defines the MCOperandInfo and MCInstrDesc classes, which 110ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach// are used to describe target instructions and their operands. 12d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 13d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 14d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#ifndef LLVM_MC_MCINSTRDESC_H 16e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#define LLVM_MC_MCINSTRDESC_H 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 181f6efa3996dd1929fbc129203ce5009b620e6969Michael J. Spencer#include "llvm/Support/DataTypes.h" 1999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 20d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnernamespace llvm { 21d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 22d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 23d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Operand Flags and Description 24d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 250ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 26e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCOI { 2706801722a43c697eff0acee905de6b50257ce19bJim Grosbach // Operand constraints 28d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandConstraint { 2906801722a43c697eff0acee905de6b50257ce19bJim Grosbach TIED_TO = 0, // Must be allocated the same register as. 3006801722a43c697eff0acee905de6b50257ce19bJim Grosbach EARLY_CLOBBER // Operand is an early clobber register operand 31d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 320ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 33d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// OperandFlags - These are flags set on operands, but should be considered 34e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// private, all access should go through the MCOperandInfo accessors. 35d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// See the accessors for a description of what these are. 36d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandFlags { 37d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner LookupPtrRegClass = 0, 38d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Predicate, 39d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner OptionalDef 40d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 415196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer 425196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer /// Operand Type - Operands are tagged with one of the values of this enum. 435196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer enum OperandType { 445196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_UNKNOWN, 455196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_IMMEDIATE, 465196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_REGISTER, 475196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_MEMORY, 485196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_PCREL 495196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer }; 50d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 51d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 52e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCOperandInfo - This holds information about one operand of a machine 53d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// instruction, indicating the register class for register operands, etc. 54d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// 55e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCOperandInfo { 56d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 570ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// RegClass - This specifies the register class enumeration of the operand 58cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// if the operand is a register. If isLookupPtrRegClass is set, then this is 59cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 60cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// get a dynamic register class. 61a606d955de3b0f777131d74162eb6f11b5f95d75Dan Gohman short RegClass; 620ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 63e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// Flags - These are flags from the MCOI::OperandFlags enum. 64d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short Flags; 650ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 66d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Lower 16 bits are used to specify which constraints are set. The higher 16 67d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// bits are used to specify the value of constraints (4 bits each). 68cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner unsigned Constraints; 695196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer 705196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer /// OperandType - Information about the type of the operand. 715196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer MCOI::OperandType OperandType; 72d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Currently no other information. 730ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 74d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isLookupPtrRegClass - Set if this operand is a pointer value and it 75d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// requires a callback to look up its register class. 767e0d22cbf7b41e93279f574c9b3c557cdf517dcbJim Grosbach bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);} 770ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 78d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isPredicate - Set if this is one of the operands that made up of 79d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the predicate operand that controls an isPredicable() instruction. 80e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 810ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 82d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isOptionalDef - Set if this operand is a optional def. 83d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 84e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 85d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 86d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 870ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 88d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 89d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Instruction Flags and Description 90d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 91d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 92e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc flags - These should be considered private to the 93e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// implementation of the MCInstrDesc class. Clients should use the predicate 94e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// methods on MCInstrDesc, not use these directly. These all correspond to 95e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// bitfields in the MCInstrDesc::Flags field. 96e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCID { 97d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum { 98d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Variadic = 0, 99d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner HasOptionalDef, 100c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen Pseudo, 101d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Return, 102d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Call, 103d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Barrier, 104d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Terminator, 105d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Branch, 106d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner IndirectBranch, 10773739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling Compare, 108c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MoveImm, 1090f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng Bitcast, 110d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner DelaySlot, 11115511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman FoldableAsLoad, 112dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner MayLoad, 113d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner MayStore, 114c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Predicable, 115c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NotDuplicable, 116a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner UnmodeledSideEffects, 117d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Commutable, 118d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner ConvertibleTo3Addr, 119533297b58da8c74bec65551e1aface9801fc2259Dan Gohman UsesCustomInserter, 12037fefc20d3a1e3934a377567d54a141f67752227Evan Cheng HasPostISelHook, 1218370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling Rematerializable, 122799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng CheapAsAMove, 123799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraSrcRegAllocReq, 124799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraDefRegAllocReq 125d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 126d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 127d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 128e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc - Describe properties that are true of each instruction in the 129e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// target description file. This captures information about side effects, 130e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// register use and many other things. There is one instance of this struct 131e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// for each target instruction class, and the MachineInstr class points to 132e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// this struct directly to describe itself. 133e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCInstrDesc { 134d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 135b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short Opcode; // The opcode number 136d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short NumOperands; // Num of args (may be more if variable_ops) 137b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short NumDefs; // Num of args that are definitions 138d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short SchedClass; // enum identifying instr sched class 13916884415db751c75f2133bd04921393c792b1158Owen Anderson unsigned short Size; // Number of bytes in encoding. 140b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng const char * Name; // Name of the instruction record in td file 141b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned Flags; // Flags identifying machine instr class 14299405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags; // Target Specific Flag values 143d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 144d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 145e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 146d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 147d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getOperandConstraint - Returns the value of the specific constraint if 148d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// it is set. Returns -1 if it is not set. 149d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner int getOperandConstraint(unsigned OpNum, 150e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCOI::OperandConstraint Constraint) const { 151d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner if (OpNum < NumOperands && 152d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner (OpInfo[OpNum].Constraints & (1 << Constraint))) { 153d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned Pos = 16 + Constraint * 4; 154d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 155d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 156d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return -1; 157d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 158d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 159d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getOpcode - Return the opcode number for this descriptor. 160d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getOpcode() const { 161d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Opcode; 162d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1630ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 164d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getName - Return the name of the record in the .td file for this 165d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction, for example "ADD8ri". 166d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const char *getName() const { 167d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Name; 168d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1690ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 170d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getNumOperands - Return the number of declared MachineOperands for this 171d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// MachineInstruction. Note that variadic (isVariadic() returns true) 172d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions may have additional operands at the end of the list, and note 173d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// that the machine instruction may include implicit register def/uses as 174d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// well. 175d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumOperands() const { 176d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumOperands; 177d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1780ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 179d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getNumDefs - Return the number of MachineOperands that are register 1800ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// definitions. Register definitions always occur at the start of the 181b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// machine operand list. This is the number of "outs" in the .td file, 182b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// and does not include implicit defs. 183d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumDefs() const { 184d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumDefs; 185d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1860ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 1877c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// getFlags - Return flags of this instruction. 1887c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// 1897c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng unsigned short getFlags() const { return Flags; } 1907c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng 191d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isVariadic - Return true if this instruction can have a variable number of 192d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands. In this case, the variable operands will be after the normal 193d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands but before the implicit definitions and uses (if any are 194d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// present). 195d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isVariadic() const { 196e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Variadic); 197d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1980ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 199d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 200d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// ARM instructions which can set condition code if 's' bit is set. 201d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasOptionalDef() const { 202e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::HasOptionalDef); 203d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2040ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 205920c6828ee2a31b324e2b0a9d16e01574955485dDan Gohman /// getImplicitUses - Return a list of registers that are potentially 206d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// read by any instance of this machine instruction. For example, on X86, 207d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the "adc" instruction adds two register operands and adds the carry bit in 208d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from the flags register. In this case, the instruction is marked as 209d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// implicitly reading the flags. Likewise, the variable shift instruction on 210d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// X86 is marked as implicitly reading the 'CL' register, which it always 211d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// does. 212d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 213d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// This method returns null if the instruction has no implicit uses. 214d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *getImplicitUses() const { 215d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return ImplicitUses; 216d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2170ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 218375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// getNumImplicitUses - Return the number of implicit uses this instruction 219375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// has. 220375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned getNumImplicitUses() const { 221375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner if (ImplicitUses == 0) return 0; 222375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned i = 0; 223375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner for (; ImplicitUses[i]; ++i) /*empty*/; 224375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner return i; 225375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner } 226e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng 227920c6828ee2a31b324e2b0a9d16e01574955485dDan Gohman /// getImplicitDefs - Return a list of registers that are potentially 228d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// written by any instance of this machine instruction. For example, on X86, 229d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// many instructions implicitly set the flags register. In this case, they 230d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// are marked as setting the FLAGS. Likewise, many instructions always 231d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// deposit their result in a physical register. For example, the X86 divide 232d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction always deposits the quotient and remainder in the EAX/EDX 233d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// registers. For that instruction, this will return a list containing the 234d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// EAX/EDX/EFLAGS registers. 235d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 236920c6828ee2a31b324e2b0a9d16e01574955485dDan Gohman /// This method returns null if the instruction has no implicit defs. 237d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner const unsigned *getImplicitDefs() const { 238d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return ImplicitDefs; 239d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2400ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 241375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// getNumImplicitDefs - Return the number of implicit defs this instruction 242375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner /// has. 243375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned getNumImplicitDefs() const { 244375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner if (ImplicitDefs == 0) return 0; 245375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner unsigned i = 0; 246375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner for (; ImplicitDefs[i]; ++i) /*empty*/; 247375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner return i; 248375cf52638cc5330abf0fe95dfa63a013a97a5f5Chris Lattner } 2490ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 2500461c0a8f5b476794a061e995210906670a4542dChris Lattner /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly 2510461c0a8f5b476794a061e995210906670a4542dChris Lattner /// uses the specified physical register. 2520461c0a8f5b476794a061e995210906670a4542dChris Lattner bool hasImplicitUseOfPhysReg(unsigned Reg) const { 2530461c0a8f5b476794a061e995210906670a4542dChris Lattner if (const unsigned *ImpUses = ImplicitUses) 2540461c0a8f5b476794a061e995210906670a4542dChris Lattner for (; *ImpUses; ++ImpUses) 2550461c0a8f5b476794a061e995210906670a4542dChris Lattner if (*ImpUses == Reg) return true; 2560461c0a8f5b476794a061e995210906670a4542dChris Lattner return false; 2570461c0a8f5b476794a061e995210906670a4542dChris Lattner } 2580ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 2590461c0a8f5b476794a061e995210906670a4542dChris Lattner /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly 2600461c0a8f5b476794a061e995210906670a4542dChris Lattner /// defines the specified physical register. 2610461c0a8f5b476794a061e995210906670a4542dChris Lattner bool hasImplicitDefOfPhysReg(unsigned Reg) const { 2620461c0a8f5b476794a061e995210906670a4542dChris Lattner if (const unsigned *ImpDefs = ImplicitDefs) 2630461c0a8f5b476794a061e995210906670a4542dChris Lattner for (; *ImpDefs; ++ImpDefs) 2640461c0a8f5b476794a061e995210906670a4542dChris Lattner if (*ImpDefs == Reg) return true; 2650461c0a8f5b476794a061e995210906670a4542dChris Lattner return false; 2660461c0a8f5b476794a061e995210906670a4542dChris Lattner } 267d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 268d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getSchedClass - Return the scheduling class for this instruction. The 269d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// scheduling class is an index into the InstrItineraryData table. This 270d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// returns zero if there is no known scheduling information for the 271d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 272d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 273d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getSchedClass() const { 274d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return SchedClass; 275d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2760ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 27716884415db751c75f2133bd04921393c792b1158Owen Anderson /// getSize - Return the number of bytes in the encoding of this instruction, 27816884415db751c75f2133bd04921393c792b1158Owen Anderson /// or zero if the encoding size cannot be known from the opcode. 27916884415db751c75f2133bd04921393c792b1158Owen Anderson unsigned getSize() const { 28016884415db751c75f2133bd04921393c792b1158Owen Anderson return Size; 28116884415db751c75f2133bd04921393c792b1158Owen Anderson } 28216884415db751c75f2133bd04921393c792b1158Owen Anderson 283c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// isPseudo - Return true if this is a pseudo instruction that doesn't 284c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// correspond to a real machine instruction. 285c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// 286c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen bool isPseudo() const { 287c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen return Flags & (1 << MCID::Pseudo); 288c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen } 289c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen 290d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isReturn() const { 291e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Return); 292d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2930ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 294d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCall() const { 295e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Call); 296d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2970ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 298d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 299d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from executing the instruction immediately following it. Examples include 300d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// unconditional branches and return instructions. 301d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBarrier() const { 302e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Barrier); 303d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3040ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 305f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach /// findFirstPredOperandIdx() - Find the index of the first operand in the 306f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach /// operand list that is used to represent the predicate. It returns -1 if 307f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach /// none is found. 308f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach int findFirstPredOperandIdx() const { 309f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (isPredicable()) { 310f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 311f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach if (OpInfo[i].isPredicate()) 312f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return i; 313f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 314f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach return -1; 315f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach } 316f8e1e3e729473b8b2b7ee6134b6417976af84d05Jim Grosbach 317d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isTerminator - Returns true if this instruction part of the terminator for 318d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// a basic block. Typically this is things like return and branch 319d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions. 320d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 321d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Various passes use this to insert code into the bottom of a basic block, 322d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// but before control flow occurs. 323d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isTerminator() const { 324e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Terminator); 325d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3260ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 327d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isBranch - Returns true if this is a conditional, unconditional, or 328d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// indirect branch. Predicates below can be used to discriminate between 329d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 330d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// get more information. 331d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBranch() const { 332e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Branch); 333d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 334d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 335d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isIndirectBranch - Return true if this is an indirect branch, such as a 336d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// branch through a register. 337d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isIndirectBranch() const { 338e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::IndirectBranch); 339d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 34073739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 341d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConditionalBranch - Return true if this is a branch which may fall 342d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// through to the next instruction or may transfer control flow to some other 343d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 344d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// information about this branch. 345d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConditionalBranch() const { 346d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & !isBarrier() & !isIndirectBranch(); 347d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3480ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 349d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isUnconditionalBranch - Return true if this is a branch which always 350d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transfers control flow to some other block. The 351d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 352d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// about this branch. 353d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isUnconditionalBranch() const { 354d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & isBarrier() & !isIndirectBranch(); 355d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3560ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 357d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // isPredicable - Return true if this instruction has a predicate operand that 358d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // controls execution. It may be set to 'always', or may be set to other 359d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// values. There are various methods in TargetInstrInfo that can be used to 360d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// control and modify the predicate in this instruction. 361d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isPredicable() const { 362e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Predicable); 363d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3640ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 36573739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling /// isCompare - Return true if this instruction is a comparison. 36673739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling bool isCompare() const { 367e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Compare); 36873739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling } 3690ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 370c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// isMoveImmediate - Return true if this instruction is a move immediate 3710ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// (including conditional moves) instruction. 372c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isMoveImmediate() const { 373e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MoveImm); 374c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 3750f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng 3760f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng /// isBitcast - Return true if this instruction is a bitcast instruction. 3770f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng /// 3780f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng bool isBitcast() const { 379e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Bitcast); 3800f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng } 3810ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 382d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isNotDuplicable - Return true if this instruction cannot be safely 383d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// duplicated. For example, if the instruction has a unique labels attached 384d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// to it, duplicating it would cause multiple definition errors. 385d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isNotDuplicable() const { 386e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::NotDuplicable); 387d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3880ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 389d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 390d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which must be filled by the code generator. 391d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasDelaySlot() const { 392e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::DelaySlot); 393d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3940ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 39515511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman /// canFoldAsLoad - Return true for instructions that can be folded as 39662c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// memory operands in other instructions. The most common use for this 39762c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// is instructions that are simple loads from memory that don't modify 39862c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// the loaded value in any way, but it can also be used for instructions 39962c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// that can be expressed as constant-pool loads, such as V_SETALLONES 40062c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// on x86, to allow them to be folded when it is beneficial. 40162c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// This should only be set on instructions that return a value in their 40262c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// only virtual register definition. 40315511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman bool canFoldAsLoad() const { 404e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::FoldableAsLoad); 405d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4060ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 407d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 408d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Side Effect Analysis 409d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 410dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 411dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// mayLoad - Return true if this instruction could possibly read memory. 412dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// Instructions with this flag set are not necessarily simple load 413dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// instructions, they may load a value and modify it, for example. 414dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner bool mayLoad() const { 415e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayLoad); 416dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner } 4170ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 4180ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 419d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// mayStore - Return true if this instruction could possibly modify memory. 420d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Instructions with this flag set are not necessarily simple store 421d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions, they may store a modified value based on their operands, or 422d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// may not actually modify anything, for example. 423d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool mayStore() const { 424e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayStore); 425d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4260ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 427a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// hasUnmodeledSideEffects - Return true if this instruction has side 428a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// effects that are not modeled by other flags. This does not return true 429a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// for instructions whose effects are captured by: 430d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 431a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 1. Their operand list and implicit definition/use list. Register use/def 432a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// info is explicit for instructions. 433a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 2. Memory accesses. Use mayLoad/mayStore. 434a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 435d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 436a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// Examples of side effects would be modifying 'invisible' machine state like 437a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// a control register, flushing a cache, modifying a register invisible to 438a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// LLVM, etc. 439d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 440a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner bool hasUnmodeledSideEffects() const { 441e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UnmodeledSideEffects); 442d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4430ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 444d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 445d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Flags that indicate whether an instruction can be modified by a method. 446d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 4470ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 448d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isCommutable - Return true if this may be a 2- or 3-address 449d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (of the form "X = op Y, Z, ..."), which produces the same 4500ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// result if Y and Z are exchanged. If this flag is set, then the 451d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::commuteInstruction method may be used to hack on the 452d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 453d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 454d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Note that this flag may be set on instructions that are only commutable 455d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// sometimes. In these cases, the call to commuteInstruction will fail. 456d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Also note that some instructions require non-trivial modification to 457d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// commute them. 458d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCommutable() const { 459e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Commutable); 460d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4610ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 462d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 463d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which can be changed into a 3-address instruction if needed. Doing this 464d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transformation can be profitable in the register allocator, because it 465d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// means that the instruction can use a 2-address form if possible, but 466d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// degrade into a less efficient form if the source and dest register cannot 467d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// be assigned to the same register. For example, this allows the x86 468d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 469d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is the same speed as the shift but has bigger code size. 470d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 471d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this returns true, then the target must implement the 472d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 473d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is allowed to fail if the transformation isn't valid for this specific 474d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (e.g. shl reg, 4 on x86). 475d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 476d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConvertibleTo3Addr() const { 477e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ConvertibleTo3Addr); 478d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4790ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 480533297b58da8c74bec65551e1aface9801fc2259Dan Gohman /// usesCustomInsertionHook - Return true if this instruction requires 481d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 482d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// machine basic block. If this is true for the instruction, it basically 4830ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// means that it is a pseudo instruction used at SelectionDAG time that is 484d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// expanded out into magic code by the target when MachineInstrs are formed. 485d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 486d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 487d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is used to insert this into the MachineBasicBlock. 488533297b58da8c74bec65551e1aface9801fc2259Dan Gohman bool usesCustomInsertionHook() const { 489e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UsesCustomInserter); 490d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4910ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 49283a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// hasPostISelHook - Return true if this instruction requires *adjustment* 49383a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// after instruction selection by calling a target hook. For example, this 49483a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// can be used to fill in ARM 's' optional operand depending on whether 49583a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// the conditional flag register is used. 49683a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick bool hasPostISelHook() const { 49783a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick return Flags & (1 << MCID::HasPostISelHook); 49883a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick } 49983a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick 500d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isRematerializable - Returns true if this instruction is a candidate for 501d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// remat. This flag is deprecated, please don't use it anymore. If this 502d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// flag is set, the isReallyTriviallyReMaterializable() method is called to 503d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// verify the instruction is really rematable. 504d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isRematerializable() const { 505e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Rematerializable); 506d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 5078370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling 5088370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 5098370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// less) than a move instruction. This is useful during certain types of 510758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// optimizations (e.g., remat during two-address conversion or machine licm) 511758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// where we would like to remat or hoist the instruction, but not if it costs 512758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// more than moving the instruction into the appropriate register. Note, we 513758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// are not marking copies from and to the same register class with this flag. 5148370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling bool isAsCheapAsAMove() const { 515e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::CheapAsAMove); 5168370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling } 517799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 518799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 519799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 520799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::STRD's two source registers must be an 521799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::STM registers have to be in ascending order. 522799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 523799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for sources of instructions with this flag. 524799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraSrcRegAllocReq() const { 525e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraSrcRegAllocReq); 526799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 527799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 528799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 529799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 530799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::LDRD's two def registers must be an 531799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::LDM registers have to be in ascending order. 532799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 533799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for definitions of instructions with this flag. 534799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraDefRegAllocReq() const { 535e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraDefRegAllocReq); 536799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 537d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 538d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 539d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} // end namespace llvm 540d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 541d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#endif 542