MCInstrDesc.h revision dd2fa5195ea2d98b2b4ee18f9894ad674f132a40
17f8f3f7f6400291d30531c88a98511f9fc626b4cChad Rosier//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 3d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// The LLVM Compiler Infrastructure 4d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 5d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// This file is distributed under the University of Illinois Open Source 6d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// License. See LICENSE.TXT for details. 7d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 8d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 9d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 1022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng// This file defines the MCOperandInfo and MCInstrDesc classes, which 110ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach// are used to describe target instructions and their operands. 12d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 13d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 14d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#ifndef LLVM_MC_MCINSTRDESC_H 16e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#define LLVM_MC_MCINSTRDESC_H 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 181f6efa3996dd1929fbc129203ce5009b620e6969Michael J. Spencer#include "llvm/Support/DataTypes.h" 1999405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 20d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnernamespace llvm { 21d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 22d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 23d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Operand Flags and Description 24d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 250ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 26e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCOI { 2706801722a43c697eff0acee905de6b50257ce19bJim Grosbach // Operand constraints 28d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandConstraint { 2906801722a43c697eff0acee905de6b50257ce19bJim Grosbach TIED_TO = 0, // Must be allocated the same register as. 3006801722a43c697eff0acee905de6b50257ce19bJim Grosbach EARLY_CLOBBER // Operand is an early clobber register operand 31d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 320ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 33d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// OperandFlags - These are flags set on operands, but should be considered 34e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// private, all access should go through the MCOperandInfo accessors. 35d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// See the accessors for a description of what these are. 36d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandFlags { 37d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner LookupPtrRegClass = 0, 38d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Predicate, 39d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner OptionalDef 40d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 415196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer 425196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer /// Operand Type - Operands are tagged with one of the values of this enum. 435196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer enum OperandType { 445196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_UNKNOWN, 455196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_IMMEDIATE, 465196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_REGISTER, 475196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_MEMORY, 485196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_PCREL 495196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer }; 50d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 51d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 52e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCOperandInfo - This holds information about one operand of a machine 53d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// instruction, indicating the register class for register operands, etc. 54d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// 55e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCOperandInfo { 56d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 570ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// RegClass - This specifies the register class enumeration of the operand 58cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// if the operand is a register. If isLookupPtrRegClass is set, then this is 59cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 60cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// get a dynamic register class. 6139bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper int16_t RegClass; 620ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 63e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// Flags - These are flags from the MCOI::OperandFlags enum. 6439bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t Flags; 6539bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper 6639bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper /// OperandType - Information about the type of the operand. 6739bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t OperandType; 680ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 69d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Lower 16 bits are used to specify which constraints are set. The higher 16 70d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// bits are used to specify the value of constraints (4 bits each). 7139bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint32_t Constraints; 72d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Currently no other information. 730ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 74d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isLookupPtrRegClass - Set if this operand is a pointer value and it 75d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// requires a callback to look up its register class. 767e0d22cbf7b41e93279f574c9b3c557cdf517dcbJim Grosbach bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);} 770ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 78d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isPredicate - Set if this is one of the operands that made up of 79d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the predicate operand that controls an isPredicable() instruction. 80e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 810ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 82d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isOptionalDef - Set if this operand is a optional def. 83d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 84e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 85d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 86d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 870ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 88d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 89d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Instruction Flags and Description 90d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 91d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 92e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc flags - These should be considered private to the 93e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// implementation of the MCInstrDesc class. Clients should use the predicate 94e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// methods on MCInstrDesc, not use these directly. These all correspond to 95e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// bitfields in the MCInstrDesc::Flags field. 96e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCID { 97d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum { 98d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Variadic = 0, 99d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner HasOptionalDef, 100c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen Pseudo, 101d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Return, 102d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Call, 103d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Barrier, 104d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Terminator, 105d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Branch, 106d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner IndirectBranch, 10773739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling Compare, 108c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MoveImm, 1090f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng Bitcast, 110f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen Select, 111d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner DelaySlot, 11215511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman FoldableAsLoad, 113dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner MayLoad, 114d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner MayStore, 115c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Predicable, 116c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NotDuplicable, 117a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner UnmodeledSideEffects, 118d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Commutable, 119d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner ConvertibleTo3Addr, 120533297b58da8c74bec65551e1aface9801fc2259Dan Gohman UsesCustomInserter, 12137fefc20d3a1e3934a377567d54a141f67752227Evan Cheng HasPostISelHook, 1228370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling Rematerializable, 123799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng CheapAsAMove, 124799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraSrcRegAllocReq, 125799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraDefRegAllocReq 126d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 127d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 128d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 129e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc - Describe properties that are true of each instruction in the 130e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// target description file. This captures information about side effects, 131e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// register use and many other things. There is one instance of this struct 132e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// for each target instruction class, and the MachineInstr class points to 133e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// this struct directly to describe itself. 134e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCInstrDesc { 135d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 136b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short Opcode; // The opcode number 137d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short NumOperands; // Num of args (may be more if variable_ops) 138b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short NumDefs; // Num of args that are definitions 139d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short SchedClass; // enum identifying instr sched class 14016884415db751c75f2133bd04921393c792b1158Owen Anderson unsigned short Size; // Number of bytes in encoding. 141b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned Flags; // Flags identifying machine instr class 14299405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags; // Target Specific Flag values 143fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *ImplicitUses; // Registers implicitly read by this instr 144fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr 145e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 146d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 147d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getOperandConstraint - Returns the value of the specific constraint if 148d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// it is set. Returns -1 if it is not set. 149d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner int getOperandConstraint(unsigned OpNum, 150e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCOI::OperandConstraint Constraint) const { 151d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner if (OpNum < NumOperands && 152d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner (OpInfo[OpNum].Constraints & (1 << Constraint))) { 153d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned Pos = 16 + Constraint * 4; 154d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 155d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 156d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return -1; 157d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 158d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 159d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getOpcode - Return the opcode number for this descriptor. 160d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getOpcode() const { 161d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Opcode; 162d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1630ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 164d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getNumOperands - Return the number of declared MachineOperands for this 165d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// MachineInstruction. Note that variadic (isVariadic() returns true) 166d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions may have additional operands at the end of the list, and note 167d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// that the machine instruction may include implicit register def/uses as 168d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// well. 169d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumOperands() const { 170d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumOperands; 171d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1720ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 173d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// getNumDefs - Return the number of MachineOperands that are register 1740ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// definitions. Register definitions always occur at the start of the 175b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// machine operand list. This is the number of "outs" in the .td file, 176b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// and does not include implicit defs. 177d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumDefs() const { 178d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumDefs; 179d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1800ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 1817c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// getFlags - Return flags of this instruction. 1827c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng /// 1835a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getFlags() const { return Flags; } 1847c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng 185d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isVariadic - Return true if this instruction can have a variable number of 186d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands. In this case, the variable operands will be after the normal 187d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands but before the implicit definitions and uses (if any are 188d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// present). 189d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isVariadic() const { 190e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Variadic); 191d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1920ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 193d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasOptionalDef - Set if this instruction has an optional definition, e.g. 194d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// ARM instructions which can set condition code if 's' bit is set. 195d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasOptionalDef() const { 196e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::HasOptionalDef); 197d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1980ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 199c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// isPseudo - Return true if this is a pseudo instruction that doesn't 200c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// correspond to a real machine instruction. 201c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// 202c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen bool isPseudo() const { 203c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen return Flags & (1 << MCID::Pseudo); 204c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen } 205c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen 206d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isReturn() const { 207e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Return); 208d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2090ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 210d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCall() const { 211e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Call); 212d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2130ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 214d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 215d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from executing the instruction immediately following it. Examples include 216d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// unconditional branches and return instructions. 217d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBarrier() const { 218e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Barrier); 219d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2200ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 221d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isTerminator - Returns true if this instruction part of the terminator for 222d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// a basic block. Typically this is things like return and branch 223d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions. 224d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 225d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Various passes use this to insert code into the bottom of a basic block, 226d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// but before control flow occurs. 227d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isTerminator() const { 228e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Terminator); 229d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2300ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 231d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isBranch - Returns true if this is a conditional, unconditional, or 232d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// indirect branch. Predicates below can be used to discriminate between 233d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 234d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// get more information. 235d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBranch() const { 236e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Branch); 237d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 238d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 239d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isIndirectBranch - Return true if this is an indirect branch, such as a 240d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// branch through a register. 241d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isIndirectBranch() const { 242e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::IndirectBranch); 243d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 24473739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 245d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConditionalBranch - Return true if this is a branch which may fall 246d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// through to the next instruction or may transfer control flow to some other 247d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 248d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// information about this branch. 249d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConditionalBranch() const { 250d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & !isBarrier() & !isIndirectBranch(); 251d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2520ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 253d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isUnconditionalBranch - Return true if this is a branch which always 254d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transfers control flow to some other block. The 255d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 256d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// about this branch. 257d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isUnconditionalBranch() const { 258d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & isBarrier() & !isIndirectBranch(); 259d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2600ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 261dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// isPredicable - Return true if this instruction has a predicate operand 262dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// that controls execution. It may be set to 'always', or may be set to other 263dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// values. There are various methods in TargetInstrInfo that can be used to 264d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// control and modify the predicate in this instruction. 265d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isPredicable() const { 266e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Predicable); 267d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2680ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 26973739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling /// isCompare - Return true if this instruction is a comparison. 27073739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling bool isCompare() const { 271e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Compare); 27273739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling } 2730ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 274c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// isMoveImmediate - Return true if this instruction is a move immediate 2750ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// (including conditional moves) instruction. 276c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isMoveImmediate() const { 277e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MoveImm); 278c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2790f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng 2800f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng /// isBitcast - Return true if this instruction is a bitcast instruction. 2810f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng /// 2820f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng bool isBitcast() const { 283e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Bitcast); 2840f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng } 2850ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 286f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// isSelect - Return true if this is a select instruction. 287f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 288f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen bool isSelect() const { 289f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen return Flags & (1 << MCID::Select); 290f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen } 291f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen 292d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isNotDuplicable - Return true if this instruction cannot be safely 293d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// duplicated. For example, if the instruction has a unique labels attached 294d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// to it, duplicating it would cause multiple definition errors. 295d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isNotDuplicable() const { 296e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::NotDuplicable); 297d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2980ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 299d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 300d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which must be filled by the code generator. 301d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasDelaySlot() const { 302e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::DelaySlot); 303d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3040ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 30515511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman /// canFoldAsLoad - Return true for instructions that can be folded as 30662c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// memory operands in other instructions. The most common use for this 30762c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// is instructions that are simple loads from memory that don't modify 30862c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// the loaded value in any way, but it can also be used for instructions 30962c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// that can be expressed as constant-pool loads, such as V_SETALLONES 31062c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// on x86, to allow them to be folded when it is beneficial. 31162c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// This should only be set on instructions that return a value in their 31262c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// only virtual register definition. 31315511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman bool canFoldAsLoad() const { 314e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::FoldableAsLoad); 315d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3160ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 317d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 318d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Side Effect Analysis 319d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 320dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 321dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// mayLoad - Return true if this instruction could possibly read memory. 322dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// Instructions with this flag set are not necessarily simple load 323dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// instructions, they may load a value and modify it, for example. 324dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner bool mayLoad() const { 325e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayLoad); 326dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner } 3270ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 3280ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 329d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// mayStore - Return true if this instruction could possibly modify memory. 330d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Instructions with this flag set are not necessarily simple store 331d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions, they may store a modified value based on their operands, or 332d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// may not actually modify anything, for example. 333d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool mayStore() const { 334e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayStore); 335d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3360ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 337a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// hasUnmodeledSideEffects - Return true if this instruction has side 338a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// effects that are not modeled by other flags. This does not return true 339a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// for instructions whose effects are captured by: 340d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 341a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 1. Their operand list and implicit definition/use list. Register use/def 342a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// info is explicit for instructions. 343a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 2. Memory accesses. Use mayLoad/mayStore. 344a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 345d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 346a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// Examples of side effects would be modifying 'invisible' machine state like 347a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// a control register, flushing a cache, modifying a register invisible to 348a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// LLVM, etc. 349d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 350a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner bool hasUnmodeledSideEffects() const { 351e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UnmodeledSideEffects); 352d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3530ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 354d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 355d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Flags that indicate whether an instruction can be modified by a method. 356d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 3570ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 358d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isCommutable - Return true if this may be a 2- or 3-address 359d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (of the form "X = op Y, Z, ..."), which produces the same 3600ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// result if Y and Z are exchanged. If this flag is set, then the 361d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::commuteInstruction method may be used to hack on the 362d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 363d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 364d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Note that this flag may be set on instructions that are only commutable 365d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// sometimes. In these cases, the call to commuteInstruction will fail. 366d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Also note that some instructions require non-trivial modification to 367d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// commute them. 368d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCommutable() const { 369e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Commutable); 370d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3710ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 372d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 373d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which can be changed into a 3-address instruction if needed. Doing this 374d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transformation can be profitable in the register allocator, because it 375d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// means that the instruction can use a 2-address form if possible, but 376d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// degrade into a less efficient form if the source and dest register cannot 377d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// be assigned to the same register. For example, this allows the x86 378d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 379d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is the same speed as the shift but has bigger code size. 380d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 381d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this returns true, then the target must implement the 382d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 383d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is allowed to fail if the transformation isn't valid for this specific 384d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (e.g. shl reg, 4 on x86). 385d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 386d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConvertibleTo3Addr() const { 387e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ConvertibleTo3Addr); 388d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3890ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 390533297b58da8c74bec65551e1aface9801fc2259Dan Gohman /// usesCustomInsertionHook - Return true if this instruction requires 391d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 392d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// machine basic block. If this is true for the instruction, it basically 3930ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// means that it is a pseudo instruction used at SelectionDAG time that is 394d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// expanded out into magic code by the target when MachineInstrs are formed. 395d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 396d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 397d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is used to insert this into the MachineBasicBlock. 398533297b58da8c74bec65551e1aface9801fc2259Dan Gohman bool usesCustomInsertionHook() const { 399e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UsesCustomInserter); 400d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4010ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 40283a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// hasPostISelHook - Return true if this instruction requires *adjustment* 40383a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// after instruction selection by calling a target hook. For example, this 40483a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// can be used to fill in ARM 's' optional operand depending on whether 40583a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// the conditional flag register is used. 40683a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick bool hasPostISelHook() const { 40783a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick return Flags & (1 << MCID::HasPostISelHook); 40883a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick } 40983a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick 410d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isRematerializable - Returns true if this instruction is a candidate for 411d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// remat. This flag is deprecated, please don't use it anymore. If this 412d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// flag is set, the isReallyTriviallyReMaterializable() method is called to 413d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// verify the instruction is really rematable. 414d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isRematerializable() const { 415e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Rematerializable); 416d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4178370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling 4188370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 4198370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// less) than a move instruction. This is useful during certain types of 420758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// optimizations (e.g., remat during two-address conversion or machine licm) 421758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// where we would like to remat or hoist the instruction, but not if it costs 422758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// more than moving the instruction into the appropriate register. Note, we 423758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// are not marking copies from and to the same register class with this flag. 4248370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling bool isAsCheapAsAMove() const { 425e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::CheapAsAMove); 4268370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling } 427799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 428799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 429799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 430799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::STRD's two source registers must be an 431799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::STM registers have to be in ascending order. 432799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 433799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for sources of instructions with this flag. 434799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraSrcRegAllocReq() const { 435e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraSrcRegAllocReq); 436799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 437799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 438799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 439799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 440799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::LDRD's two def registers must be an 441799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::LDM registers have to be in ascending order. 442799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 443799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for definitions of instructions with this flag. 444799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraDefRegAllocReq() const { 445e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraDefRegAllocReq); 446799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 4475a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4485a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4495a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getImplicitUses - Return a list of registers that are potentially 4505a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// read by any instance of this machine instruction. For example, on X86, 4515a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// the "adc" instruction adds two register operands and adds the carry bit in 4525a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// from the flags register. In this case, the instruction is marked as 4535a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// implicitly reading the flags. Likewise, the variable shift instruction on 4545a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// X86 is marked as implicitly reading the 'CL' register, which it always 4555a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// does. 4565a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 4575a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit uses. 458fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *getImplicitUses() const { 4595a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return ImplicitUses; 4605a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4615a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4625a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getNumImplicitUses - Return the number of implicit uses this instruction 4635a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// has. 4645a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitUses() const { 4655a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (ImplicitUses == 0) return 0; 4665a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 4675a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; ImplicitUses[i]; ++i) /*empty*/; 4685a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 4695a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4705a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4715a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getImplicitDefs - Return a list of registers that are potentially 4725a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// written by any instance of this machine instruction. For example, on X86, 4735a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// many instructions implicitly set the flags register. In this case, they 4745a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// are marked as setting the FLAGS. Likewise, many instructions always 4755a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// deposit their result in a physical register. For example, the X86 divide 4765a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction always deposits the quotient and remainder in the EAX/EDX 4775a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// registers. For that instruction, this will return a list containing the 4785a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// EAX/EDX/EFLAGS registers. 4795a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 4805a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit defs. 481fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *getImplicitDefs() const { 4825a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return ImplicitDefs; 4835a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4845a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4855a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getNumImplicitDefs - Return the number of implicit defs this instruction 4865a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// has. 4875a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitDefs() const { 4885a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (ImplicitDefs == 0) return 0; 4895a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 4905a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; ImplicitDefs[i]; ++i) /*empty*/; 4915a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 4925a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4935a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4945a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly 4955a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// uses the specified physical register. 4965a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool hasImplicitUseOfPhysReg(unsigned Reg) const { 497fac259814923d091942b230e7bd002a8d1130bc3Craig Topper if (const uint16_t *ImpUses = ImplicitUses) 4985a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpUses; ++ImpUses) 4995a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (*ImpUses == Reg) return true; 5005a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5015a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5025a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 5035a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly 5045a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// defines the specified physical register. 5055a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool hasImplicitDefOfPhysReg(unsigned Reg) const { 506fac259814923d091942b230e7bd002a8d1130bc3Craig Topper if (const uint16_t *ImpDefs = ImplicitDefs) 5075a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpDefs; ++ImpDefs) 5085a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (*ImpDefs == Reg) return true; 5095a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5105a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5115a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 5125a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getSchedClass - Return the scheduling class for this instruction. The 5135a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// scheduling class is an index into the InstrItineraryData table. This 5145a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// returns zero if there is no known scheduling information for the 5155a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction. 5165a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 5175a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getSchedClass() const { 5185a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return SchedClass; 5195a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5205a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 5215a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getSize - Return the number of bytes in the encoding of this instruction, 5225a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// or zero if the encoding size cannot be known from the opcode. 5235a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getSize() const { 5245a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return Size; 5255a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5265a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 5275a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// findFirstPredOperandIdx() - Find the index of the first operand in the 5285a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// operand list that is used to represent the predicate. It returns -1 if 5295a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// none is found. 5305a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng int findFirstPredOperandIdx() const { 5315a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (isPredicable()) { 5325a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5335a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (OpInfo[i].isPredicate()) 5345a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5355a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5365a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return -1; 5375a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 538d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 539d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 540d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} // end namespace llvm 541d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 542d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#endif 543