MCInstrDesc.h revision 0ba45d4fb3e11d8085b01008e31477bece20d01d
1//===-- llvm/Mc/McInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the MCOperandInfo and MCInstrDesc classes, which
11// are used to describe target instructions and their operands.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_MC_MCINSTRDESC_H
16#define LLVM_MC_MCINSTRDESC_H
17
18#include "llvm/Support/DataTypes.h"
19
20namespace llvm {
21
22//===----------------------------------------------------------------------===//
23// Machine Operand Flags and Description
24//===----------------------------------------------------------------------===//
25
26namespace MCOI {
27  // Operand constraints
28  enum OperandConstraint {
29    TIED_TO = 0,    // Must be allocated the same register as.
30    EARLY_CLOBBER   // Operand is an early clobber register operand
31  };
32
33  /// OperandFlags - These are flags set on operands, but should be considered
34  /// private, all access should go through the MCOperandInfo accessors.
35  /// See the accessors for a description of what these are.
36  enum OperandFlags {
37    LookupPtrRegClass = 0,
38    Predicate,
39    OptionalDef
40  };
41
42  /// Operand Type - Operands are tagged with one of the values of this enum.
43  enum OperandType {
44    OPERAND_UNKNOWN,
45    OPERAND_IMMEDIATE,
46    OPERAND_REGISTER,
47    OPERAND_MEMORY,
48    OPERAND_PCREL
49  };
50}
51
52/// MCOperandInfo - This holds information about one operand of a machine
53/// instruction, indicating the register class for register operands, etc.
54///
55class MCOperandInfo {
56public:
57  /// RegClass - This specifies the register class enumeration of the operand
58  /// if the operand is a register.  If isLookupPtrRegClass is set, then this is
59  /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
60  /// get a dynamic register class.
61  short RegClass;
62
63  /// Flags - These are flags from the MCOI::OperandFlags enum.
64  unsigned short Flags;
65
66  /// Lower 16 bits are used to specify which constraints are set. The higher 16
67  /// bits are used to specify the value of constraints (4 bits each).
68  unsigned Constraints;
69
70  /// OperandType - Information about the type of the operand.
71  MCOI::OperandType OperandType;
72  /// Currently no other information.
73
74  /// isLookupPtrRegClass - Set if this operand is a pointer value and it
75  /// requires a callback to look up its register class.
76  bool isLookupPtrRegClass() const { return Flags&(1 <<MCOI::LookupPtrRegClass);}
77
78  /// isPredicate - Set if this is one of the operands that made up of
79  /// the predicate operand that controls an isPredicable() instruction.
80  bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
81
82  /// isOptionalDef - Set if this operand is a optional def.
83  ///
84  bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
85};
86
87
88//===----------------------------------------------------------------------===//
89// Machine Instruction Flags and Description
90//===----------------------------------------------------------------------===//
91
92/// MCInstrDesc flags - These should be considered private to the
93/// implementation of the MCInstrDesc class.  Clients should use the predicate
94/// methods on MCInstrDesc, not use these directly.  These all correspond to
95/// bitfields in the MCInstrDesc::Flags field.
96namespace MCID {
97  enum {
98    Variadic = 0,
99    HasOptionalDef,
100    Return,
101    Call,
102    Barrier,
103    Terminator,
104    Branch,
105    IndirectBranch,
106    Compare,
107    MoveImm,
108    Bitcast,
109    DelaySlot,
110    FoldableAsLoad,
111    MayLoad,
112    MayStore,
113    Predicable,
114    NotDuplicable,
115    UnmodeledSideEffects,
116    Commutable,
117    ConvertibleTo3Addr,
118    UsesCustomInserter,
119    Rematerializable,
120    CheapAsAMove,
121    ExtraSrcRegAllocReq,
122    ExtraDefRegAllocReq
123  };
124}
125
126/// MCInstrDesc - Describe properties that are true of each instruction in the
127/// target description file.  This captures information about side effects,
128/// register use and many other things.  There is one instance of this struct
129/// for each target instruction class, and the MachineInstr class points to
130/// this struct directly to describe itself.
131class MCInstrDesc {
132public:
133  unsigned short  Opcode;        // The opcode number
134  unsigned short  NumOperands;   // Num of args (may be more if variable_ops)
135  unsigned short  NumDefs;       // Num of args that are definitions
136  unsigned short  SchedClass;    // enum identifying instr sched class
137  unsigned short  Size;          // Number of bytes in encoding.
138  const char *    Name;          // Name of the instruction record in td file
139  unsigned        Flags;         // Flags identifying machine instr class
140  uint64_t        TSFlags;       // Target Specific Flag values
141  const unsigned *ImplicitUses;  // Registers implicitly read by this instr
142  const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
143  const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
144
145  /// getOperandConstraint - Returns the value of the specific constraint if
146  /// it is set. Returns -1 if it is not set.
147  int getOperandConstraint(unsigned OpNum,
148                           MCOI::OperandConstraint Constraint) const {
149    if (OpNum < NumOperands &&
150        (OpInfo[OpNum].Constraints & (1 << Constraint))) {
151      unsigned Pos = 16 + Constraint * 4;
152      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
153    }
154    return -1;
155  }
156
157  /// getOpcode - Return the opcode number for this descriptor.
158  unsigned getOpcode() const {
159    return Opcode;
160  }
161
162  /// getName - Return the name of the record in the .td file for this
163  /// instruction, for example "ADD8ri".
164  const char *getName() const {
165    return Name;
166  }
167
168  /// getNumOperands - Return the number of declared MachineOperands for this
169  /// MachineInstruction.  Note that variadic (isVariadic() returns true)
170  /// instructions may have additional operands at the end of the list, and note
171  /// that the machine instruction may include implicit register def/uses as
172  /// well.
173  unsigned getNumOperands() const {
174    return NumOperands;
175  }
176
177  /// getNumDefs - Return the number of MachineOperands that are register
178  /// definitions.  Register definitions always occur at the start of the
179  /// machine operand list.  This is the number of "outs" in the .td file,
180  /// and does not include implicit defs.
181  unsigned getNumDefs() const {
182    return NumDefs;
183  }
184
185  /// isVariadic - Return true if this instruction can have a variable number of
186  /// operands.  In this case, the variable operands will be after the normal
187  /// operands but before the implicit definitions and uses (if any are
188  /// present).
189  bool isVariadic() const {
190    return Flags & (1 << MCID::Variadic);
191  }
192
193  /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
194  /// ARM instructions which can set condition code if 's' bit is set.
195  bool hasOptionalDef() const {
196    return Flags & (1 << MCID::HasOptionalDef);
197  }
198
199  /// getImplicitUses - Return a list of registers that are potentially
200  /// read by any instance of this machine instruction.  For example, on X86,
201  /// the "adc" instruction adds two register operands and adds the carry bit in
202  /// from the flags register.  In this case, the instruction is marked as
203  /// implicitly reading the flags.  Likewise, the variable shift instruction on
204  /// X86 is marked as implicitly reading the 'CL' register, which it always
205  /// does.
206  ///
207  /// This method returns null if the instruction has no implicit uses.
208  const unsigned *getImplicitUses() const {
209    return ImplicitUses;
210  }
211
212  /// getNumImplicitUses - Return the number of implicit uses this instruction
213  /// has.
214  unsigned getNumImplicitUses() const {
215    if (ImplicitUses == 0) return 0;
216    unsigned i = 0;
217    for (; ImplicitUses[i]; ++i) /*empty*/;
218    return i;
219  }
220
221  /// getImplicitDefs - Return a list of registers that are potentially
222  /// written by any instance of this machine instruction.  For example, on X86,
223  /// many instructions implicitly set the flags register.  In this case, they
224  /// are marked as setting the FLAGS.  Likewise, many instructions always
225  /// deposit their result in a physical register.  For example, the X86 divide
226  /// instruction always deposits the quotient and remainder in the EAX/EDX
227  /// registers.  For that instruction, this will return a list containing the
228  /// EAX/EDX/EFLAGS registers.
229  ///
230  /// This method returns null if the instruction has no implicit defs.
231  const unsigned *getImplicitDefs() const {
232    return ImplicitDefs;
233  }
234
235  /// getNumImplicitDefs - Return the number of implicit defs this instruction
236  /// has.
237  unsigned getNumImplicitDefs() const {
238    if (ImplicitDefs == 0) return 0;
239    unsigned i = 0;
240    for (; ImplicitDefs[i]; ++i) /*empty*/;
241    return i;
242  }
243
244  /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly
245  /// uses the specified physical register.
246  bool hasImplicitUseOfPhysReg(unsigned Reg) const {
247    if (const unsigned *ImpUses = ImplicitUses)
248      for (; *ImpUses; ++ImpUses)
249        if (*ImpUses == Reg) return true;
250    return false;
251  }
252
253  /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
254  /// defines the specified physical register.
255  bool hasImplicitDefOfPhysReg(unsigned Reg) const {
256    if (const unsigned *ImpDefs = ImplicitDefs)
257      for (; *ImpDefs; ++ImpDefs)
258        if (*ImpDefs == Reg) return true;
259    return false;
260  }
261
262  /// getSchedClass - Return the scheduling class for this instruction.  The
263  /// scheduling class is an index into the InstrItineraryData table.  This
264  /// returns zero if there is no known scheduling information for the
265  /// instruction.
266  ///
267  unsigned getSchedClass() const {
268    return SchedClass;
269  }
270
271  /// getSize - Return the number of bytes in the encoding of this instruction,
272  /// or zero if the encoding size cannot be known from the opcode.
273  unsigned getSize() const {
274    return Size;
275  }
276
277  bool isReturn() const {
278    return Flags & (1 << MCID::Return);
279  }
280
281  bool isCall() const {
282    return Flags & (1 << MCID::Call);
283  }
284
285  /// isBarrier - Returns true if the specified instruction stops control flow
286  /// from executing the instruction immediately following it.  Examples include
287  /// unconditional branches and return instructions.
288  bool isBarrier() const {
289    return Flags & (1 << MCID::Barrier);
290  }
291
292  /// isTerminator - Returns true if this instruction part of the terminator for
293  /// a basic block.  Typically this is things like return and branch
294  /// instructions.
295  ///
296  /// Various passes use this to insert code into the bottom of a basic block,
297  /// but before control flow occurs.
298  bool isTerminator() const {
299    return Flags & (1 << MCID::Terminator);
300  }
301
302  /// isBranch - Returns true if this is a conditional, unconditional, or
303  /// indirect branch.  Predicates below can be used to discriminate between
304  /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
305  /// get more information.
306  bool isBranch() const {
307    return Flags & (1 << MCID::Branch);
308  }
309
310  /// isIndirectBranch - Return true if this is an indirect branch, such as a
311  /// branch through a register.
312  bool isIndirectBranch() const {
313    return Flags & (1 << MCID::IndirectBranch);
314  }
315
316  /// isConditionalBranch - Return true if this is a branch which may fall
317  /// through to the next instruction or may transfer control flow to some other
318  /// block.  The TargetInstrInfo::AnalyzeBranch method can be used to get more
319  /// information about this branch.
320  bool isConditionalBranch() const {
321    return isBranch() & !isBarrier() & !isIndirectBranch();
322  }
323
324  /// isUnconditionalBranch - Return true if this is a branch which always
325  /// transfers control flow to some other block.  The
326  /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
327  /// about this branch.
328  bool isUnconditionalBranch() const {
329    return isBranch() & isBarrier() & !isIndirectBranch();
330  }
331
332  // isPredicable - Return true if this instruction has a predicate operand that
333  // controls execution.  It may be set to 'always', or may be set to other
334  /// values.   There are various methods in TargetInstrInfo that can be used to
335  /// control and modify the predicate in this instruction.
336  bool isPredicable() const {
337    return Flags & (1 << MCID::Predicable);
338  }
339
340  /// isCompare - Return true if this instruction is a comparison.
341  bool isCompare() const {
342    return Flags & (1 << MCID::Compare);
343  }
344
345  /// isMoveImmediate - Return true if this instruction is a move immediate
346  /// (including conditional moves) instruction.
347  bool isMoveImmediate() const {
348    return Flags & (1 << MCID::MoveImm);
349  }
350
351  /// isBitcast - Return true if this instruction is a bitcast instruction.
352  ///
353  bool isBitcast() const {
354    return Flags & (1 << MCID::Bitcast);
355  }
356
357  /// isNotDuplicable - Return true if this instruction cannot be safely
358  /// duplicated.  For example, if the instruction has a unique labels attached
359  /// to it, duplicating it would cause multiple definition errors.
360  bool isNotDuplicable() const {
361    return Flags & (1 << MCID::NotDuplicable);
362  }
363
364  /// hasDelaySlot - Returns true if the specified instruction has a delay slot
365  /// which must be filled by the code generator.
366  bool hasDelaySlot() const {
367    return Flags & (1 << MCID::DelaySlot);
368  }
369
370  /// canFoldAsLoad - Return true for instructions that can be folded as
371  /// memory operands in other instructions. The most common use for this
372  /// is instructions that are simple loads from memory that don't modify
373  /// the loaded value in any way, but it can also be used for instructions
374  /// that can be expressed as constant-pool loads, such as V_SETALLONES
375  /// on x86, to allow them to be folded when it is beneficial.
376  /// This should only be set on instructions that return a value in their
377  /// only virtual register definition.
378  bool canFoldAsLoad() const {
379    return Flags & (1 << MCID::FoldableAsLoad);
380  }
381
382  //===--------------------------------------------------------------------===//
383  // Side Effect Analysis
384  //===--------------------------------------------------------------------===//
385
386  /// mayLoad - Return true if this instruction could possibly read memory.
387  /// Instructions with this flag set are not necessarily simple load
388  /// instructions, they may load a value and modify it, for example.
389  bool mayLoad() const {
390    return Flags & (1 << MCID::MayLoad);
391  }
392
393
394  /// mayStore - Return true if this instruction could possibly modify memory.
395  /// Instructions with this flag set are not necessarily simple store
396  /// instructions, they may store a modified value based on their operands, or
397  /// may not actually modify anything, for example.
398  bool mayStore() const {
399    return Flags & (1 << MCID::MayStore);
400  }
401
402  /// hasUnmodeledSideEffects - Return true if this instruction has side
403  /// effects that are not modeled by other flags.  This does not return true
404  /// for instructions whose effects are captured by:
405  ///
406  ///  1. Their operand list and implicit definition/use list.  Register use/def
407  ///     info is explicit for instructions.
408  ///  2. Memory accesses.  Use mayLoad/mayStore.
409  ///  3. Calling, branching, returning: use isCall/isReturn/isBranch.
410  ///
411  /// Examples of side effects would be modifying 'invisible' machine state like
412  /// a control register, flushing a cache, modifying a register invisible to
413  /// LLVM, etc.
414  ///
415  bool hasUnmodeledSideEffects() const {
416    return Flags & (1 << MCID::UnmodeledSideEffects);
417  }
418
419  //===--------------------------------------------------------------------===//
420  // Flags that indicate whether an instruction can be modified by a method.
421  //===--------------------------------------------------------------------===//
422
423  /// isCommutable - Return true if this may be a 2- or 3-address
424  /// instruction (of the form "X = op Y, Z, ..."), which produces the same
425  /// result if Y and Z are exchanged.  If this flag is set, then the
426  /// TargetInstrInfo::commuteInstruction method may be used to hack on the
427  /// instruction.
428  ///
429  /// Note that this flag may be set on instructions that are only commutable
430  /// sometimes.  In these cases, the call to commuteInstruction will fail.
431  /// Also note that some instructions require non-trivial modification to
432  /// commute them.
433  bool isCommutable() const {
434    return Flags & (1 << MCID::Commutable);
435  }
436
437  /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
438  /// which can be changed into a 3-address instruction if needed.  Doing this
439  /// transformation can be profitable in the register allocator, because it
440  /// means that the instruction can use a 2-address form if possible, but
441  /// degrade into a less efficient form if the source and dest register cannot
442  /// be assigned to the same register.  For example, this allows the x86
443  /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
444  /// is the same speed as the shift but has bigger code size.
445  ///
446  /// If this returns true, then the target must implement the
447  /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
448  /// is allowed to fail if the transformation isn't valid for this specific
449  /// instruction (e.g. shl reg, 4 on x86).
450  ///
451  bool isConvertibleTo3Addr() const {
452    return Flags & (1 << MCID::ConvertibleTo3Addr);
453  }
454
455  /// usesCustomInsertionHook - Return true if this instruction requires
456  /// custom insertion support when the DAG scheduler is inserting it into a
457  /// machine basic block.  If this is true for the instruction, it basically
458  /// means that it is a pseudo instruction used at SelectionDAG time that is
459  /// expanded out into magic code by the target when MachineInstrs are formed.
460  ///
461  /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
462  /// is used to insert this into the MachineBasicBlock.
463  bool usesCustomInsertionHook() const {
464    return Flags & (1 << MCID::UsesCustomInserter);
465  }
466
467  /// isRematerializable - Returns true if this instruction is a candidate for
468  /// remat.  This flag is deprecated, please don't use it anymore.  If this
469  /// flag is set, the isReallyTriviallyReMaterializable() method is called to
470  /// verify the instruction is really rematable.
471  bool isRematerializable() const {
472    return Flags & (1 << MCID::Rematerializable);
473  }
474
475  /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
476  /// less) than a move instruction. This is useful during certain types of
477  /// optimizations (e.g., remat during two-address conversion or machine licm)
478  /// where we would like to remat or hoist the instruction, but not if it costs
479  /// more than moving the instruction into the appropriate register. Note, we
480  /// are not marking copies from and to the same register class with this flag.
481  bool isAsCheapAsAMove() const {
482    return Flags & (1 << MCID::CheapAsAMove);
483  }
484
485  /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
486  /// have special register allocation requirements that are not captured by the
487  /// operand register classes. e.g. ARM::STRD's two source registers must be an
488  /// even / odd pair, ARM::STM registers have to be in ascending order.
489  /// Post-register allocation passes should not attempt to change allocations
490  /// for sources of instructions with this flag.
491  bool hasExtraSrcRegAllocReq() const {
492    return Flags & (1 << MCID::ExtraSrcRegAllocReq);
493  }
494
495  /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
496  /// have special register allocation requirements that are not captured by the
497  /// operand register classes. e.g. ARM::LDRD's two def registers must be an
498  /// even / odd pair, ARM::LDM registers have to be in ascending order.
499  /// Post-register allocation passes should not attempt to change allocations
500  /// for definitions of instructions with this flag.
501  bool hasExtraDefRegAllocReq() const {
502    return Flags & (1 << MCID::ExtraDefRegAllocReq);
503  }
504};
505
506} // end namespace llvm
507
508#endif
509